PDM41024LA15T

PDM41024 1 Megabit Static RAM 128K x 8-Bit Features n 1 2 3 4 5 6 7 Description The PDM41024 is a high-performance CMOS static RAM organized as 131,072 x 8 bits. Writing is accomplished when the write enable (WE) and the chip enable (CE1) inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE and CE2 remain HIGH and CE1 and OE are both LOW. The PDM41024 operates from a single +5V power supply and all the inputs and outputs are fully TTLcompatible. The PDM41024 comes in two versions: the standard power version (SA) and the low power version (LA). The two versions are functionally the same and differ only in their power consumption. The PDM41024 is available in a 32-pin plastic TSOP (I), and a 300-mil and 400-mil plastic SOJ. High-speed access times Com’l: 10, 12 and 15 ns Ind’l: 12 and 15 ns Low power operation (typical) - PDM41024SA Active: 450 mW Standby: 50 mW - PDM41024LA Active: 400 mW Standby: 25mW Single +5V (±10%) power supply TTL-compatible inputs and outputs Packages Plastic SOJ (300 mil) - TSO Plastic SOJ (400 mil) - SO Plastic TSOP (I)- T n n n n Functional Block Diagram A0 • • • • • A16 Decoder Addresses • • • • • • Memory Matrix 8 9 10 I/O 0 • • I/O 7 ••••• Input Data Control Column I/O • • 11 12 1 CE1 CE2 WE OE • Control Rev. 3.3 - 4/09/98 PDM41024 Pin Configuration TSOP (I) A11 A9 A8 A13 WE CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SOJ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Name A16-A0 I/O7-I/O0 OE WE CE1, CE2 NC VCC VSS Description Address Inputs Data Inputs/Outputs Output Enable Input Write Enable Input Chip Enable Inputs No Connect Power (+5V) Ground Truth Table(1) OE X X L X H WE X X H L H CE1 H X L L L CE2 X L H H H I/O Hi-Z Hi-Z DOUT DIN Hi-Z MODE Standby Standby Read Write Output Disable NOTE: 1. H = VIH, L = VIL, X = DON’T CARE Absolute Maximum Ratings (1) Symbol VTERM TBIAS TSTG PT IOUT Tj Rating Terminal Voltage with Respect to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Maximum Junction Temperature (2) Com’l. –0.5 to +7.0 –55 to +125 –55 to +125 1.0 50 125 Ind. –0.5 to +7.0 –65 to +135 –65 to +150 1.0 50 145 Unit V °C °C W mA °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P is average operating power and θja the thermal resistance of the package. For this product, use the following θja values: SOJ: 72o C/W TSOP: 95o C/W 2 4/09/98 - Rev. 3.3 PDM41024 Recommended DC Operating Condition Symbol VCC VSS Industrial Commercial Parameter Supply Voltage Supply Voltage Ambient Temperature Ambient Temperature Min. 4.5 0 –40 0 Typ. 5.0 0 25 25 Max. 5.5 0 85 70 Unit V V °C °C 1 2 3 DC Electrical Characteristics (VCC = 5.0V ± 10%) PDM41024SA Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Conditions VCC = MAX., VIN = VSS to VCC VCC = MAX., CE1 = VIH and CE2 = VIL, VOUT = VSS to VCC Com’l/ Ind. Com’l/ Ind. Min. –5 –5 Max. 5 5 PDM41024LA Min. –1 –1 Max. 1 1 Unit µA µA 4 5 6 7 VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 8 mA, VCC = Min. IOL = 10 mA, VCC = Min. IOH = –4 mA, VCC = Min. –0.5(1) 2.2 — — 2.4 0.8 6.0 0.4 0.5 — –0.5(1) 2.2 — — 2.4 0.8 6.0 0.4 0.5 — V V V V V NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns Power Supply Characteristics -10 Symbol ICC Parameter Operating Current CE1 = VIL and CE2 = VIH f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE1 = VIH and CE2 = VIL f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE1 ≥ VHC and CE2 ≤ VLC f=0 VCC = Max. VIN ≥ VCC – 0.2V or ≤ 0.2V Power SA LA Com’l. 250 230 -12 Com’l. 230 210 Ind. 240 220 -15 Com’l. 185 165 Ind. 195 175 8 9 10 11 12 3 SA LA SA LA 80 75 20 10 70 65 20 10 70 65 25 10 55 50 10 5 55 50 15 10 SHADED AREAS = PRELIMINARY DATA NOTES: All values are maximum guaranteed values. VLC ≤ 0.2V, VHC ≥ VCC – 0.2V Rev. 3.3 - 4/09/98 PDM41024 Capacitance(1) (TA = +25°C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max. 8 8 Unit pF pF NOTE:1. This parameter is determined by device characterization but is not production tested. AC Test Conditions Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load VSS to 3.0V 3 ns 1.5V 1.5V See Figures 1 and 2 +5V 480Ω DOUT 255Ω 30 pF DOUT 255Ω +5V 480Ω 5 pF Figure 1. Output Load Equivalent Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Delta tAA - ns 5 4 3 2 1 0 0 Typical Delta tAA vs Capacitive Loading 30 60 90 120 Additional Lumped Capacitive Loading (pF) Figure 3. 4 4/09/98 - Rev. 3.3 PDM41024 Read Cycle No. 1(4, 5) tRC ADDR 1 2 DATA VALID tAA tOH DOUT PREVIOUS DATA VALID Read Cycle No. 2(2, 4, 6) tRC 3 4 5 tLZCE tHZCE tAA tACE ADDR CE1 CE2 OE tLZOE DOUT tAOE tHZOE DATA VALID 6 7 8 -15 AC Electrical Characteristics Description READ Cycle READ cycle time Address access time Chip enable access time Output hold from address change Chip enable to output in low Z(1,3) Chip disable to output in high Z(1,2,3) Chip enable to power up time(3) Chip disable to power down time Output enable access time Output enable to output in low Z (1,3) (3) -10(7) Sym tRC tAA tACE tOH tLZCE tHZCE tPU tPD tAOE tLZOE tHZOE 0 6 0 10 6 0 3 5 6 0 -12(7) Min. Max. Min. Max. Min. Max. Units 10 10 10 3 5 6 0 12 6 0 6 6 15 6 12 12 12 3 5 7 15 15 15 ns ns ns ns ns ns ns ns ns ns ns 9 10 11 12 5 Output disable to output in high Z(1,3) SHADED AREA = PRELIMINARY DATA Notes referenced are after Data Retention Table. Rev. 3.3 - 4/09/98 PDM41024 Write Cycle No. 1 (Write Enable Controlled) tWC ADDR tAW tCW CE2 CE1 tAH tAS WE tWP2 tDS DIN DATA VALID tDH tHZWE DOUT HIGH-Z tLZWE Write Cycle No. 2 (Write Enable Controlled) tWC ADDR tAW tCW CE2 CE1 tAH tAS WE tWP1 tDS DIN DATA VALID tDH DOUT HIGH-Z NOTE: Output Enable (OE) is inactive (high) 6 4/09/98 - Rev. 3.3 PDM41024 Write Cycle No. 3 (Chip Enable Controlled) tWC ADDR tAW tAS CE2 CE1 tWP1 WE tDS DIN DATA VALID 1 tAH tCW 2 3 tDH 4 5 6 DOUT NOTE: Output Enable (OE) is inactive (high) HIGH-Z AC Electrical Characteristics Description WRITE Cycle WRITE cycle time Chip enable active time Address valid to end of write Address setup time Address hold from end of write Write pulse width Write pulse width Data setup time Data hold time Write disable to output in low Z Write enable to output in high (1,3) -10(7) Sym tWC tCW tAW tAS tAH tWP1 tWP2 tDS tDH tLZWE tHZWE Z(1,3) -12(7) -15 Min. Max. Min. Max. Min. Max. Units 10 10 10 0 0 8 8 7 0 0 7 12 10 10 0 0 8 8 7 0 0 7 15 11 11 0 0 11 12 7 0 0 7 ns ns ns ns ns ns ns ns ns ns ns 7 8 9 10 11 12 SHADED AREA = PRELIMINARY DATA Notes referenced are after Data Retention Table Rev. 3.3 - 4/09/98 7 PDM41024 Low VCC Data Retention Waveform Data Retention Mode V CC 4.5V 4.5V VDR t CDR VIH IL VDR tR CE1 V CE2 VIH V IL DON'T CARE ≤ 0.2V Data Retention Electrical Characteristics (LA Version Only) for JEDEC Version Symbol VDR ICCDR Parameter VCC for Retention Data Data Retention Current CE1 ≥ VCC – 0.2V or CE2 ≤ VSS + 0.2V VIN ≥ VCC – 0.2V or ≤ 0.2V VCC = 2V VCC = 3V Test Conditions Min. 2 — — Typ. — — — Max. — 500 750 Unit V µA µA tCDR tR (3) Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC — — — — ns ns NOTES: (For three previous Electrical Characteristics tables) 1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE. 3. This parameter is sampled. 4. WE is high for a READ cycle. 5. The device is continuously selected. All the Chip Enables are held in their active state. 6. The address is valid prior to or coincident with the latest occurring Chip Enable. 7. Vcc = 5V ± 5%. Ordering Information XXXXX X Device Type Power XX Speed X X X Package Type Process Temp. Range Preferred Shipping Container Blank Tubes TR Tape & Reel TY Tray Blank Commercial (0° to +70°C) I Industrial (-40° to +85°C) A Automotive (-40° to +105°C) TSO 32-pin 300-mil Plastic SOJ SO 32-pin 400-mil Plastic SOJ T 32-pin Plastic TSOP (I) 10 Commercial Only 12 15 (use 15 ns for slower designs) SA LA Standard Power Low Power PDM41024 - 1 Meg (128Kx8) Static RAM 8 4/09/98 - Rev. 3.3