P4C16825JC

P4C168, P4C169, P4C170 P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 12/15/20/25ns (Commercial) – 20/25/35ns (P4C168 Military) Low Power Operation (Commercial) – 715 mW Active – 193 mW Standby (TTL Input) P4C168 – 83 mW Standby (CMOS Input) P4C168 Single 5V±10% Power Supply Fully TTL Compatible, Common I/O Ports Three Options – P4C168 Low Power Standby Mode – P4C169 Fast Chip Select Control – P4C170 Fast Chip Select, Output Enable Controls Standard Pinout (JEDEC Approved) – P4C168: 20-pin DIP, SOJ and SOIC – P4C169: 20-pin DIP and SOIC – P4C170: 22-pin DIP DESCRIPTION The P4C168, P4C169 and P4C170 are a family of 16,384bit ultra high-speed static RAMs organized as 4K x 4. All three devices have common input/output ports.The P4C168 enters the standby mode when the chip enable (CE) control goes high; with CMOS input levels, power consumption is only 83mW in this mode. Both the P4C169 and the P4C170 offer a fast chip select access time that is only 67% of the address access time. In addition, the P4C170 includes an output enable (OE) control to eliminate data bus contention. The RAMs operate from a single 5V ± 10% tolerance power supply. Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 715 mW active, 193 mW standby. The P4C168 and P4C169 are available in 20-pin (P4C170 in 22-pin) 300 mil DIP packages providing excellent board level densities. The P4C168 is also available in 20-pin 300 mil SOIC and SOJ packages. The P4C169 is also available in a 20-pin 300 mil SOIC package. The P4C170 is also available in a 22-pin 300 mil SOJ package. FUNCTIONAL BLOCK DIAGRAM A ROW SELECT A 16,384-BIT MEMORY ARRAY PIN CONFIGURATIONS (7) A0 A1 A2 INPUT DATA CONTROL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V CC A 11 A 10 A9 A8 I/O4 I/O3 I/O2 I/O1 WE A0 A1 A2 A3 A4 A5 A6 A7 CS OE GND 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 V CC A 11 A 10 A9 A8 NC I/O4 I/O3 I/O2 I/O1 WE I/O 1 I/O 2 I/O 3 I/O 4 COLUMN I/O A3 A4 A5 A6 A7 CE , CS GND POWER DOWN COLUMN SELECT CE or CS WE OE NOTES: CE USED ON P4C168 ALSO FOR POWER DOWN FUNCTIONS CE USED ON P4C169 FAST CHIP SELECT OE OUTPUT ENABLE FUNCTION ON P4C170 ONLY P4C168 ONLY A (5) A P4C168 P4C169 DIP (P2, D2) DIP (P2) SOIC (S2) SOIC (S2) SOJ (J2) TOP VIEW P4C170 DIP (P3) TOP VIEW Means Quality, Service and Speed 1Q97 33 P4C168, P4C169, P4C170 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value – 0.5 to +7 – 0.5 to VCC + 0.5 –55 to +125 Unit V Symbol TBIAS TSTG V °C PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value – 55 to +125 – 65 to +150 1.0 50 Unit °C °C W mA VTERM TA RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Military Ambient Temp 0°C to 70°C –55°C to +125°C Gnd 0V 0V VCC 5.0V ± 10% 5.0V ± 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT= 0V DC ELECTRICAL CHARACTERISTICS P4C168/169/170 Symbol VIH VIL VHC VLC VCD VOL VOLC VOH VOHC ILI ILO ICC ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output Low Voltage (CMOS Load) Output High Voltage (TTL Load) Output High Voltage (CMOS Load) Input Leakage Current Output Leakage Current Dynamic Operating Current Standby Power Supply Current (TTL Input Levels) P4C168 only Standby Power Supply Current (CMOS Input Levels) P4C168 only VCC = Min., IIN = –18 mA IOL = +8 mA, VCC = Min. IOLC = +100 µA, VCC = Min. IOH = –4 mA, VCC = Min. IOHC = –100 µA, VCC = Min. VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC Mil. Comm’l Mil. Comm’l 2.4 VCC –0.2 –10 –5 –10 –5 ___ ___ Test Conditions Min 2.2 –0.5(3) VCC –0.2 –0.5(3) Max VCC +0.5 0.8 VCC +0.5 0.2 –1.2 0.4 0.2 Unit V V V V V V V V V +10 +5 +10 +5 130 35 µA µA mA mA VCC = Max., f = Max., Outputs Open CE ≥ VIH, VCC = Max., f = Max., Outputs Open CE ≥ VHC, VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ISB1 ___ 15 mA 34 P4C168, P4C169, P4C170 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tRC tAA tAC§ tAC‡ tOH tLZ‡ tHZ† tOE† t † OLZ Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Select Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Data Valid Output Enable to Output in Low Z Output Disable to Output in High Z Read Command Setup Time Read Command Hold Time Chip Enable to Power Up Time Chip Disable to Power Down Time 0 0 0 0 2 2 –12 12 12 12 8 2 2 6 8 0 6 0 0 0 12 –15 15 15 15 9 2 2 7 10 0 7 0 0 0 15 –20 20 20 20 12 2 2 9 12 0 9 0 0 0 20 –25 –35 Unit ns Min Max Min Max Min Max Min Max Min Max 25 25 25 15 2 2 10 15 0 11 0 0 0 25 35 15 15 15 35 35 35 20 ns ns ns ns ns ns ns ns ns ns ns ns ns tOHZ† tRCS tRCH t § PU tPD§ § P4C168 only † P4C170 only ‡ Chip Select/Deselect for P4C169 and P4C170 TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6) (9) t RC ADDRESS t AA t OH DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 5. WE is HIGH for READ cycle. 6. CE/CS and OE are LOW for READ cycle. 35 P4C168, P4C169, P4C170 TIMING WAVEFORM OF READ CYCLE NO. 2 (CE/CS CONTROLLED)(5,7) READ CYCLE WAVEFORM NO. 2 (CS Controlled) tRC CE /CS (7) (5,7) t AC DATA VALID t OLZ (7) t HZ (7) t LZ DATA OUT HIGH IMPEDANCE (7) t OHZ t OE OE (P4C170) t RCS WE I CC VCC SUPPLY CURRENT (P4C168 ONLY) I SB t PU t PD t RCH TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE CONTROLLED)(5) (9) t RC ADDRESS t AA OE t OE (8) t OH t OLZ CS AC (8) t LZ t t (8) OHZ (8) t HZ DATA OUT Notes: 7. ADDRESS must be valid prior to, or coincident with CE/CS transition low. For Fast CS, tAA must still be met. 8. Transition is measured ±200mV from steady state voltage prior to change, with loading as specified in Figure 1. 1521 05 9. Read Cycle Time is measured from the last valid address to the first transitioning address. 36 P4C168, P4C169, P4C170 AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 0 –12 12 12 12 0 12 0 7 0 4 0 –15 15 15 15 0 15 0 8 0 5 0 –20 18 18 18 0 18 0 10 0 7 0 –25 20 20 20 0 20 0 10 0 7 0 –35 35 30 30 0 30 0 15 0 13 Min Max Min Max Min Max Min Max Min Max Unit ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10) t WC ADDRESS t CW CE/CS t AW t WP WE t AS DATA IN t WZ DATA OUT DATA UNDEFINED HIGH IMPEDANCE (8) (12) t WR t AH t DW DATA VALID t DH t OW(8,11) Notes: 10. CE/CS and WE must be LOW for WRITE cycle. 11. If CE/CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 12. Write Cycle Time is measured from the last valid address to the first transitioning address. 37 P4C168, P4C169, P4C170 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE/CS CONTROLLED)(10) t WC ADDRESS t AS CE/CS t AW t WP WE t DW DATA IN DATA VALID t DH t CW t AH t WR (12) DATA OUT HIGH IMPEDANCE TRUTH TABLES P4C168 (P4C169) Mode Standby (Deselect) Read Write CE (CS) H L L WE X H L Output High Z DOUT High Z P4C170 Mode Deselect Read Output Inhibit Write GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 CE H L L L WE X H H L OE X L H X Output High Z DOUT High Z High Z AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load +5 R 480Ω D OUT 255Ω 300pF(5pF* for tHZ, tLZ, tOHZ, tOLZ, tWZ and tOW) DOUT TH = 166.5 Ω VTH = 1.73 V 30pF(5pF* for tHZ, tLZ, tOHZ, tOLZ , tWZ and tOW Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C168, P4C169 AND P4C170 care must be taken when testing these devices; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long highinductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF Figure 2. Thevenin Equivalent high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 38 P4C168, P4C169, P4C170 PACKAGE SUFFIX Package Suffix P S J D Description Plastic DIP, 300 mil wide standard Plastic SOIC, 300 mil wide standard Plastic SOJ, 300 mil wide standard CERDIP, 300 mil wide standard TEMPERATURE RANGE SUFFIX Temperature Range Suffix C M MB Description Commercial Temperature Range, 0°C – +70°C. Military Temperature Range, –55°C – +125°C. Mil. Temp. with MIL-STD-883D Class B compliance ORDERING INFORMATION 168 169 170 — P4C ss p t Temperature Range Package Code Speed (Access/Cycle Time) Device Number Static RAM Prefix ss = Speed (access/cycle time in ns), e.g., 15, 20 p = Package code, i.e., P, S,D, J. t = Temperature range, i.e., C, M, MB. The P4C168 is also available per SMD #5962-86705 SELECTION GUIDE The P4C168, P4C169 and P4C170 are available in the following temperature, speed and package options. Temperature Range Package Commercial Plastic DIP Plastic SOIC† Plastic SOJ†† Speed (ns) 12 -12PC -12SC -12JC N/A N/A 15 -15PC -15SC -15JC N/A N/A 20 -20PC -20SC -20JC -20DM -20DMB 25 -25PC -25SC -25JC -25DM 35 N/A N/A N/A -35DM Military Temp. CERDIP (P4C168 only) CERDIP Military Processed* (P4C168 only) -25DMB -35DMB † P4C168 and P4C169 only. †† P4C168 * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available 39 P4C168, P4C169, P4C170 40