TMPA218DS

tai'mec GENERAL DESCRIPTION Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 3.5W/CH STEREO CLASS-D AUDIO POWER AMPLIFIER FEATURES ♦ 2.5V to 6V Single Supply ♦ Up to 3.5W / Ch at 5.5V, 2 ohms ♦ Up to 88% Power Efficiency ♦ Automatic output power control (APC) ♦ Memory of voltage gain at shutdown ♦ 0dB to -60dB attenuation from max. voltage gain ♦ 2.2mA / Ch Quiescent Current at 5V ♦ Less Than 0.2uA / Ch Shutdown Current ♦ Pop-less Power-Up, Shutdown and Recovery ♦ Differential 250 KHz PWM Allows Bridge-Tied Load to increase Output Power and Eliminates LC Output Filter ♦ Thermal Shutoff and Automatic Recovery ♦ Compatible with earphone application ♦ Output Pin Short-Circuit Protection (Short to Other Outputs, Short to VCC, Short to Ground) The TMPA218DS is a stereo class-D audio power amplifier IC with digital volume control. With BTL (Bridge-Tied-Load) configuration, it delivers up to 3.5W/ch (7W in all) into a 2 ohm load. Up and down volume control signals provide -60dB attenuation form maximum voltage gain. No external heat-sink is required. For multiple-input applications, independent gain control and corner frequency can be implemented by summing the input sources through resistor ratio and input capacitor values. Automatic output power control makes the best use of battery. Analog input signal is converted into digital output which drives directly to the speaker. High power efficiency is achieved due to digital output at the load. The audio information is embedded in PWM Pulse Width Modulation） （ . APPLICATIONS Multimedia application includes Cellular Phones, PDAs, DVD/CD players, TFT LCD TVs/Monitors, 2.1 channel audio systems, USB audio. It is also ideal for other portable devices like Wireless Radios. ♦ Differential Signal Processing Improves CMRR Package TSSOP20 Available, pb free【RoHS】 For best performance, please refer to http://www.taimec.com.tw/English/EVM.htm http://www.class-d.com.tw/English/EVM.htm for PCB layout. REFERENCE CIRCUIT（Please refer to TMPA002.APP for application） RIN RIN Ri ROUTP PWM COM COM Power Drive ROUTN LOUTP PWM LIN LIN Ri Power Drive LOUTN 200K SDNB UPB DOWNB MEMO VC C VC C VDD Control Circuitry TO PS 200K 200K GND TMPA218DS Copyright©2005, Tai-1 Microelectronics Corp. 1 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 RIN MEMO DOWNB PVDD ROUTP PGND ROUTN PVDD CAP AGND TMPA218DS 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 COM LIN UPB PVDD LOUTP PGND LOUTN PVDD SDNB AVDD （Please email david@taimec.com.tw for complete datasheet.） Tai-1 Microelectronics reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers are responsible for their products and applications using Tai-1 Microelectronics components. Note that the external components or PCB layout should be designed not to generate abnormal voltages to the chip to prevent from latch up which may cause damage to the device. Typical Application IN1 COM IN2 R9 C15 VC C J1 R11 10K C19 1uF IC1 1 2 MEMO 3 D O WN B 4 P V DD 5 RO UTP 6 P G ND 7 RO UTN 8 P V DD 9 CA P 10A G ND RIN 20k 10k 20k C4 C2 C1 1uF 1uF 1uF 470p C14 20 19 18 PV DD 17 LO UTP 16 PG ND 15 LO UTN 14 PV DD 13 SD NB 12 A V DD 11 CO M LI N U PB R7 R6 470p C5 PHONEJACK STEREO R3 0 R1 R2 330 330 R15 OP EN(Option) R14 OP EN(Option) 2nF C3 2nF UP S3 DOW N C17 1uF R10 L2 L4 L3 R5 S1 33uH 33uH 33uH 33uH L1 1uF 100 1uF C11 1uF C7 S2 10K VC C C16 T218DS VC C VC C C12 1uF 1uF 1uF 470uF C10 1uF 1uF VO1+ LS1 VO1- + C8 C6 C13 switch VO2- LS2 VO2+ C9 Copyright©2005, Tai-1 Microelectronics Corp. 2 tai'mec Supply voltage, VDD, AVDD Input voltage, VI Continuous total power dissipation Operating free-air temperature, TA Operating junction temperature, TJ Storage temperature, Tstg Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted(1) In normal mode In shutdown mode -0.3V to 6V -0.3V to 7V -0.3V to VDD+0.3V V V V See package dissipation ratings 。 -20 to 85 C -20 to 150 -40 to 150 。 C 。 C (1) Stresses beyond those listed under”absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions “is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITONS PARAMETER Supply voltage High-level input voltage, VIH1 Low-level input voltage, VIL1 High-level input voltage, VIH2 Low-level input voltage, VIL2 High-level input voltage, VIH3 Low-level input voltage, VIL3 Operating free-air temperature, TA VDD, AVDD VIH for SDNB VIL for SDNB VIH for MEMO VIL for MEMO VIH for UPB, DOWNB VIL for UPB, DOWNB VDD= AVDD = 5V TEST CONDITIONS MIN 2.5 2 0 70%xVDD 0 70%xVDD 0 -20 NOM MAX 6 VDD 0.8 VDD 30%xVDD VDD 30%xVDD 85 UNIT V 。 C PACKAGE DISSIPATION RATINGS PACKAGE TSSOP20 DERATING FACTOR 8.73 mW/。 C TA ≤ 25。 C POWER RATING 1.09W T A = 7 0。 C POWER RATING 698mW T A = 8 5。 C POWER RATING 567mW ELECTRICAL CHARACTERISTICS TA=25。 (unless otherwise noted) C PARAMETER │VOS│ PSRR CMRR │IIH1│ │IIL1│ │IIH2│ │IIL2│ Output offset voltage (measured differentially) Power supply rejection ratio Common mode rejection ratio High-level input current Low-level input current High-level input current Low-level input current TEST CONDITIONS VI=0V,AV=2, VDD=AVDD=2.5V to 5.5V VDD=AVDD=2.5V to 5.5V VDD=AVDD=2.5V to 5.5V, VIC=1Vpp, RL=8Ω VDD=AVDD=5.5V, VI=5.8V (SDNB) VDD=AVDD=5.5V, VI=-0.3V (SDNB) VDD=AVDD=5.5V, VI=5.8V (MEMO) VDD=AVDD=5.5V, VI=-0.3V (MEMO) MIN TYP 25 -75 -55 30 MAX UNIT mV -55 -50 dB dB µA 1 1 1 µA µA µA Copyright©2005, Tai-1 Microelectronics Corp. 3 tai'mec │IIH3│ │IIL3│ IQ (SD) rDS(on) f(sw) Avmax RSDN Rud ZI High-level input current Low-level input current Shutdown current / Ch Static output resistance Switching frequency Max. BTL Gain Resistance from SDNB to GND Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 VDD=AVDD=5.5V, VI=5.8V (UPB, DOWNB) VDD=AVDD=5.5V, VI=-0.3V (UPB, DOWNB) V( SDN )=0.8V, VDD=AVDD=2.5V to 5.5V VDD=AVDD=5.5V VDD=AVDD=2.5V to 5.5V VDD=AVDD=2.5V to 5.5V, RL=8Ω V(SDNB)= 5V V(UPB)= V(DOWNB)=5V RIN,LIN 200 21 200 200 30 30 0.2 790 250 1 µA µA 0.5 300 25 µA mΩ kHz db kΩ kΩ kΩ Resistance from UpB / DownB to VDD Input impedance OPERATING CHARACTERISTICS TA=25。 RL=8Ω speaker (unless otherwise noted) C, PARAMETER RL=8Ω Output power / Ch PO THD+N=10%,f=1kHz. (Limited by thermal condition) RL=4Ω RL=3Ω RL=2Ω VDD=AVDD=5.5V. VDD=AVDD=5V. TEST CONDITIONS MIN TYP MAX 1.5 2.3 2.7 3.5 0.2 0.2 0.25 95 -68 UNIT W VDD=AVDD=5V, PO=1W, RL=8Ω, f=1kHz THD+N Total harmonic distortion plus noise VDD=AVDD=5V, PO=1.5W, RL=4Ω, f=1kHz VDD=AVDD=5V, PO=1.8W, RL=3Ω, f=1kHz SNR Crosstalk Signal-to-noise ratio Crosstalk between outputs VDD=AVDD=5V, PO=1W, RL=8Ω VDD=AVDD=5V, PO=1W RL=8Ω % dB dB TERMINAL FUNCTIONS TERMINAL I/O NAME AGND AVDD CAP DOWNB PGND COM LIN LOUTN LOUTP RIN MEMO ROUTN ROUTP SDNB PIN NO 10 11 9 3 6,15 20 19 14 16 1 2 7 5 12 I I I I O O I I O O I Analog ground Analog power supply Capacitance for power up delay and UPB/DOWNB reaction time Volume down Digital ground Common ground Left channel input Negative output of left channel Positive output of left channel Right channel input Memory Negative output of right channel Positive output of right channel Shutdown terminal (active low logic) DESCRIPTION Copyright©2005, Tai-1 Microelectronics Corp. 4 tai'mec UPB PVDD 18 4,8,13,17 I - Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 Volume up Digital Power supply TYPICAL CHARACTERISTICS Note 1. Input coupling 1µF capacitors are used for all measurements. 2. Differential inputs are applied and BTL outputs are measured. 3. Balanced LC filter is used for THD+N measurement and power efficiency measurement. 4. Characteristic frequency of the LC filter is set 41 KHz unless otherwise specified. Volume Step and Attenuation at Vdd=5v Step 0 1 2 3 4 5 6 7 8 9 10 ※ Attenuation(dB) 0 1 2 3 4 5 6 7 8 9 10 Overall AV(dB) 23 22 21 20 19 18 17 16 15 14 13 Step 11 ※ 12 13 14 15 16 17 18 19 20 21 Attenuation(dB) 12 14 16 18 20 22 24 26 28 30 33 Overall AV(dB) 11 9 7 5 3 1 -1 -3 -5 -7 -10 Step 22 23 24 25 26 27 28 29 30 31 Attenuation(dB) 36 39 42 45 48 51 54 57 60 ∞ Overall AV(dB) -13 -16 -19 -22 -25 -28 -31 -34 -37 -∞ Overall gain is preset at 5db at power up. Volume UP/DOWN Control ‧ Volume up and down control is executed by UPB and DOWNB digital input signals. ‧ UPB and DOWNB are “low” active. ‧ Continuous “low” at UPB or DOWNB will make volume to change continuously. ‧ A “low” at DOWNB overwrites a “low” at UPB. ‧ Timing diagram(capacitance at CAP pin has to be 1uF for following timing relationship) UPB/DOWNB Volume Level t0 tx Copyright©2005, Tai-1 Microelectronics Corp. 5 tai'mec 1. 2. 3. Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 First volume change is set at falling edge of UPB/DOWNB input. Second volume change is set at ~0.5s(t0) after falling edge of UPB/DOWNB input. Following volume changes are set at ~0.1s(tx) from previous change. Note that the capacitance at pin CAP=1uF for t0=0.5s & t1=0.1s. The delay time t0 & t1 change linearly with capacitance at CAP pin, i.e. t0=1s & t1=0.2s if CAP=2uF. APPLICATION INFORMATION Copyright©2005, Tai-1 Microelectronics Corp. 6 tai'mec DETAILED DESCRIPTION Efficiency Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 The output transistors of a class D amplifier act as switches. The power loss is mainly due to the turn on resistance of the output transistors when driving current to the load. As the turn on resistance is so small that the power loss is small and the power efficiency is high. With 8 ohm load the power efficiency can be up to 88%. Shutdown The shutdown mode reduces power consumption. A LOW at shutdown pin forces the device in shutdown mode and a HIGH forces the device in normal operating mode. Shutdown mode is useful for power saving when not in use. This function is useful when other devices like earphone amplifier on the same PCB are used but class D amplifier is not necessary. Internal circuit for shutdown is shown below. Note that shutdown pin or SDNB is also used for volume control. Please refer to Voltage Gain section for details. Pop-less A soft start capacitor can be added to the CAP pin. This capacitor introduces delay for the internal circuit to be stable before driving the load. The pop or click noise when power up/down or switching in between shutdown mode can be thus eliminated. The delay time is proportional to the value of the capacitance. It is about 500ms for a capacitor of 1uF at 5v. CAP Cap provides a way of soft startup delay. A 5uA current source and a half_Vcc detector are integrated in the chip. The charged capacitor is externally hooked up. For C=1uF the half_Vcc delay is T = CV / I = （1uF × 2.5V）/ 5uA = 0.5 seconds Copyright©2005, Tai-1 Microelectronics Corp. 7 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 Voltage gain The voltage gain is preset, at power up, to 5db typical with 8 ohms load. The voltage gain can be increased by applying a LOW at UPB or decreased by applying a LOW at DOWNB. The maximum gain it can reach is 23db and the minimum gain is -55db. Beyond -55db is a MUTE. Memory of voltage gain The voltage gain is preset to 5db at power up. The voltage gain can be changed to higher or lower value by applying a LOW at UPB or DOWNB. The changed voltage gain can be memorized during shutdown if MEMO=Vcc. In other words the voltage gain is the same before and after shutdown operation with MEMO=Vcc. Note that a RC delay is necessary between Vcc & MEMO at power up to ensure proper operation of the memory. Copyright©2005, Tai-1 Microelectronics Corp. 8 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 During shutdown mode, memory of voltage gain is still in effect even battery is removed for some time. The time period in which the voltage gain is still memorized during battery removed depends on the Vcc-GND capacitance and Vcc voltage. Example 1. Four-battery power supply with Vcc-GND capacitance equals 1000uF. If the voltage of each exhausted battery to be replaced is 1.0v on average then the voltage on the 1000uF capacitor is 4.0v. Since the chip can keep memory for down to 0.5v, the voltage allowed to drop is 4.0v-0.5v=3.5v. The voltage drop is caused by the small leakage of the chip, typical 0.2uA, during shutdown. So the time to survive is CV/I =1000uF x 3.5v/ 0.2uA = 17500 sec = 4.8 hrs Example 2. Two-battery power supply with Vcc-GND capacitance equals 1000uF. If the voltage of each exhausted battery to be replaced is 1.0v on average then the voltage on the 1000uF capacitor is 2.0v. The voltage allowed to drop is 2.0v-0.5v=1.5v. With typical leakage current of 0.2uA the time to survive is CV/I =1000uF x 1.5v / 0.2uA = 7500 sec = 2.08 hrs Automatic output Power Control (APC) The voltage gain is self adjusted in the chip over voltage range. This means that, regardless supply voltage change, the output power keeps about the same for a given input level from VDD=5.5v to 2.5v. It allows the best use of the battery. Input filter Input filter is not required for most of the applications. However in some designs if it is necessary to reduce overall voltage gain, one can add an external input resistor as a voltage divider. It is advantageous to add a capacitor in between positive input and negative input to form an input filter. An example to reduce voltage gain to 60%, as shown in the schematic on page 2, is also shown below. Note that the layout of input traces has to be symmetric. Copyright©2005, Tai-1 Microelectronics Corp. 9 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 Output filter Ferrite bead filter can be used for EMI purpose. The ferrite filter reduces EMI around 1 MHz and higher（FCC and CE only test radiated emissions greater than 30 MHz）. When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use an LC output filter if there are low frequency（＜1 MHz）EMI sensitive circuits and/or there are long wires from the amplifier to the speaker. EMI is also affected by PCB layout and the placement of the surrounding components. The suggested LC values for different speaker impendence are showed in following figures for reference. Typical LC Output Filter (1) 33μH Vo+ 0.47µ F 33μH Vo0.1µ F 0.1µ F Copyright©2005, Tai-1 Microelectronics Corp. 10 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 Typical LC Output Filter (2) Over temperature protection A temperature sensor is built in the device to detect the temperature inside the device. When a high temperature around 145oC and above is detected the switching output signals are disabled to protect the device from over temperature. Automatic recovery circuit enables the device to come back to normal operation when the internal temperature of the device is below around 120 oC. Over current protection A current detection circuit is built in the device to detect the switching current of the output stages of the device. It disables the device when the current is beyond about 3.5amps. It protects the device when there is an accident short between outputs or between output and power/gnd pins. It also protects the device when an abnormal low impedance is tied to the output. High current beyond the specification may potentially causes electron migration and permanently damage the device. Shutdown or power down is necessary to resolve the protection situation. There is no automatic recovery from over current protection. Copyright©2005, Tai-1 Microelectronics Corp. 11 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 Physical Dimensions (IN MILLIMETERS) ± 7.72 TYP 4.16 TYP (1.78 TYP) 0.42 TYP 0.65 TYP LAND PATTERN TSSOP20 Copyright©2005, Tai-1 Microelectronics Corp. 12 tai'mec Preliminary www.taimec.com.tw / www.class-d.com.tw TMPA218DS Rev.1.0 December 24, 2007 IMPORTANT NOTICE Tai-1 Microelectronics Corp. reserves the right to make changes to its products and services and to discontinue any product or service without notice. Customers should obtain the latest relevant information for reference. Testing and quality control techniques are used to screen the parameters. Testing of all parameters of each product is not necessarily performed. Tai-1 Microelectronics Corp. assumes no liability for applications assistance or customer product design. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. Reproduction of information in data sheets or related documentation is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Tai-1 Microelectronics Corp. is not responsible or liable for such altered documentation. Resale of Tai-1 Microelectronics Corp. products or services with statements different from the parameters stated by Tai-1 Microelectronics Corp. for that product or service voids all express and any implied warranties. Tai-1 Microelectronics Corp. is not responsible or liable for any such statements. Copyright ©2005,Tai-1 Microelectronics Corp. Copyright©2005, Tai-1 Microelectronics Corp. 13