IPB025N08N3G

IPB025N08N3G MOSFET OptiMOSª3Power-Transistor,80V D²PAK Features •N-channel,normallevel •ExcellentgatechargexRDS(on)product(FOM) •Verylowon-resistanceRDS(on) •175°Coperatingtemperature •Pb-freeleadplating;RoHScompliant •QualifiedaccordingtoJEDEC1)fortargetapplication •Idealforhigh-frequencyswitchingandsynchronousrectification •Halogen-freeaccordingtoIEC61249-2-21 Table1KeyPerformanceParameters Parameter Value Unit VDS 80 V RDS(on),max 2.5 mΩ ID 120 A Drain Pin 2, Tab Gate Pin 1 Source Pin 3 Type/OrderingCode Package Marking RelatedLinks IPB025N08N3 G PG-TO 263 025N08N - 1) J-STD20 and JESD22 Final Data Sheet 1 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Final Data Sheet 2 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current Values Unit Note/TestCondition 120 120 A TC=25°C1) TC=100°C - 480 A TC=25°C - - 1430 mJ ID=100A,RGS=25Ω VGS -20 - 20 V - Power dissipation Ptot - - 300 W TC=25°C Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - Pulsed drain current1) ID,pulse - Avalanche energy, single pulse EAS Gate source voltage 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Values Min. Typ. Max. RthJC - - 0.5 K/W - Thermal resistance, junction - ambient, RthJA minimal footprint - - 62 K/W - Thermal resistance, junction - ambient, RthJA 6 cm2 cooling area2) - - 40 K/W - Unit Note/TestCondition 3Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Min. Typ. Max. V(BR)DSS 80 - - V VGS=0V,ID=1mA Gate threshold voltage VGS(th) 2 2.8 3.5 V VDS=VGS,ID=270µA Zero gate voltage drain current IDSS - 0.1 10 1 100 µA VDS=80V,VGS=0V,Tj=25°C VDS=80V,VGS=0V,Tj=125°C Gate-source leakage current IGSS - 1 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 2.0 2.4 2.5 3.9 mΩ VGS=10V,ID=100A VGS=6V,ID=50A Gate resistance RG - 2.7 - Ω - Transconductance gfs 94 187 - S |VDS|>2|ID|RDS(on)max,ID=100A 1) See Diagram 3 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) Final Data Sheet 3 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G Table5Dynamiccharacteristics Parameter Symbol Input capacitance Values Max. Unit Note/TestCondition Min. Typ. Ciss - 10700 14200 pF VGS=0V,VDS=40V,f=1MHz Output capacitance Coss - 2890 3840 pF VGS=0V,VDS=40V,f=1MHz Reverse transfer capacitance Crss - 100 150 pF VGS=0V,VDS=40V,f=1MHz Turn-on delay time td(on) - 28 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Rise time tr - 73 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Turn-off delay time td(off) - 86 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Fall time tf - 33 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Unit Note/TestCondition Table6Gatechargecharacteristics1) Parameter Symbol Gate to source charge Values Min. Typ. Max. Qgs - 50 67 nC VDD=40V,ID=100A,VGS=0to10V Gate to drain charge Qgd - 30 45 nC VDD=40V,ID=100A,VGS=0to10V Switching charge Qsw - 50 72 nC VDD=40V,ID=100A,VGS=0to10V Gate charge total Qg - 155 206 nC VDD=40V,ID=100A,VGS=0to10V Gate plateau voltage Vplateau - 4.7 - V VDD=40V,ID=100A,VGS=0to10V Output charge Qoss - 210 279 nC VDD=40V,VGS=0V Unit Note/TestCondition Table7Reversediode Parameter Symbol Diode continous forward current Values Min. Typ. Max. IS - - 100 A TC=25°C Diode pulse current IS,pulse - - 400 A TC=25°C Diode forward voltage VSD - 1.0 1.2 V VGS=0V,IF=100A,Tj=25°C Reverse recovery time trr - 113 - ns VR=40V,IF=IS,diF/dt=100A/µs Reverse recovery charge Qrr - 317 - nC VR=40V,IF=IS,diF/dt=100A/µs 1) See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G 4Electricalcharacteristicsdiagrams Diagram2:Draincurrent 350 140 300 120 250 100 200 80 ID[A] Ptot[W] Diagram1:Powerdissipation 150 60 100 40 50 20 0 0 50 100 150 0 200 0 50 100 TC[°C] 150 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 100 10 1 µs 10 µs 100 µs 0.5 102 ID[A] ZthJC[K/W] 1 ms 10 ms 10-1 0.2 0.1 DC 1 10 0.05 0.02 0.01 single pulse 0 10 10-1 100 101 102 10 -2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 5 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 480 15 10 V 440 7V 6V 400 12 4.5 V 360 5V ID[A] 280 RDS(on)[mΩ] 320 5.5 V 240 200 160 9 6 5V 120 3 80 7V 4.5 V 40 0 5.5 V 0 1 6V 10 V 2 3 4 0 5 0 50 100 VDS[V] 150 200 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 300 250 250 200 200 gfs[S] ID[A] 150 150 100 100 175 °C 25 °C 50 50 0 0 2 4 6 8 0 0 VGS[V] 100 150 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 50 gfs=f(ID);Tj=25°C 6 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 6 4.0 3.5 5 3.0 2700 µA 4 VGS(th)[V] RDS(on)[mΩ] 2.5 98 % 3 270 µA 2.0 1.5 typ 2 1.0 1 0.5 0 -60 -20 20 60 100 140 0.0 -60 180 -20 20 Tj[°C] 60 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=100A;VGS=10V VGS(th)=f(Tj);VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 5 103 10 25 °C 175 °C 25 °C, 98% 175 °C, 98% Ciss 104 102 IF[A] C[pF] Coss 103 Crss 101 102 101 0 20 40 60 80 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 7 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 3 10 12 40 V 10 20 V 25 °C 102 100 °C VGS[V] IAV[A] 150 °C 60 V 8 101 6 4 2 100 10-1 100 101 102 103 0 0 tAV[µs] 50 100 150 200 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=50Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Gate charge waveforms 90 VBR(DSS)[V] 80 70 60 -60 -20 20 60 100 140 180 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 8 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G 5PackageOutlines Figure1OutlinePG-TO263,dimensionsinmm/inches Final Data Sheet 9 2016-03-31 OptiMOSª3Power-Transistor,80V IPB025N08N3G RevisionHistory IPB025N08N3 G Revision:2016-03-31 Previous Revision Date Subjects (major changes since last revision) 2016-03-31 Update SOA Diagram TrademarksofInfineonTechnologiesAG AURIX™,C166™,CanPAK™,CIPOS™,CoolGaN™,CoolMOS™,CoolSET™,CoolSiC™,CORECONTROL™,CROSSAVE™,DAVE™,DI-POL™,DrBlade™, EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,HITFET™,HybridPACK™,Infineon™, ISOFACE™,IsoPACK™,i-Wafer™,MIPAQ™,ModSTACK™,my-d™,NovalithIC™,OmniTune™,OPTIGA™,OptiMOS™,ORIGA™,POWERCODE™, PRIMARION™,PrimePACK™,PrimeSTACK™,PROFET™,PRO-SIL™,RASIC™,REAL3™,ReverSave™,SatRIC™,SIEGET™,SIPMOS™,SmartLEWIS™, SOLIDFLASH™,SPOC™,TEMPFET™,thinQ™,TRENCHSTOP™,TriCore™. TrademarksupdatedAugust2015 OtherTrademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2016InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.With respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. 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