IR3541MGB03TRP

Digital Multi-Phase Buck Controller FEATURES IR3541 CHL8325A/B DESCRIPTION  5-phase dual output PWM Controller  Phases are flexibly assigned between Loops 1 & 2  Intel® VR12, AMD® 400kHz & 3.4MHz SVI and Memory modes The IR3541 and CHL8325A/B are dual-loop digital multi-phase buck controllers that drive up to 5 phases. The IR3541 and CHL8325A/B are fully Intel® VR12 and AMD® SVI compliant on both loops and provides a Vtt tracking function for DDR memory.  Dual OCP support for I-spike enhanced AMD CPUs  SMB_Alert Pin for Servers NVM storage saves pins and enables a small package size.  PMBus Address pin or Variable Gate Drive (IR3541/CHL8325A) The IR3541 and CHL8325A/B include the IR Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. IR Variable Gate Drive optimizes the MOSFET gate drive voltage as a function of real-time load current. IR Dynamic Phase Control adds/drops active phases based upon load current. The IR3541 and CHL8325A/B can be configured to enter 1-phase operation and active diode emulation mode automatically or by command.  2 Temperature Sense for VR12 Desktop (CHL8325B) nd  Overclocking & Gaming Mode with Vmax setting  Switching frequency from 200kHz to 1.2MHz per phase  IR Efficiency Shaping Features including Variable Gate Drive (IR3541/CHL8325A only) and Dynamic Phase Control  Programmable 1-phase or 2-phase for Light Loads and Active Diode Emulation for Very Light Loads  IR Adaptive Transient Algorithm (ATA) on both loops minimizes output bulk capacitors and system cost  Auto-Phase Detection with auto-compensation  Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP  I2C/SMBus/PMBus system interface for telemetry of Temperature, Voltage, Current & Power for both loops  Non-Volatile Memory (NVM) for custom configuration  Compatible with IR ATL and 3.3V Tri-state Drivers  +3.3V supply voltage; -20ºC to 85ºC ambient operation IR’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors. The I2C/PMBus interface can communicate with up to 16 IR3541 and CHL8325A/B based VR loops. Device configuration and fault parameters are easily defined using the IR Intuitive Power Designer (DPDC) GUI and stored in on-chip NVM. The IR3541 and CHL8325A/B also include numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying VRD design and enabling fastest time-to-market with its “set-and-forget” methodology. PIN DIAGRAM  Pb-Free, RoHS, 6x6 40-pin QFN, MSL2 package APPLICATIONS  Intel ® VR12 & AMD® SVI based systems  DDR Memory with Vtt tracking  Overclocked & Gaming platforms Figure 1: IR3541 Package Top View 1 June 21, 2013 | FINAL | V1.09 IR3541 CHL8325A/B Digital Multi-Phase Buck Controller ORDERING INFORMATION IR3541M          P/PBF – Lead Free TR – Tape & Reel / TY - Tray yy – Configuration File ID xx – Customer ID Package Packing Qty Part Number QFN TR=3000 TY=4900 IR3541MTRPBF IR3541MTYPBF QFN TR=3000 IR3541MxxyyTRP Programming Default Customer Configuration 1 Notes: 1. Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing). Package Type (QFN) Package Packing Qty T=3000 TY=4900 T=3000 T=3000 TY=4900 T=3000 QFN CHL8325 ―      QFN QFN T – Tape & Reel / TY - Tray R – Package Type (QFN) C – Operating Temperature, Commercial QFN Part Number CHL8325A-00CRT CHL8325A-00CRTY CHL8325A-xxCRT1 CHL8325B-00CRT CHL8325B-00CRTY CHL8325B-xxCRT1 Notes: 1. “xx” indicates a customer specific configuration file. xx – Configuration File Figure 2: IR3541 Package Top View, Enlarged 2 June 21, 2013 | FINAL | V1.09 IRTN1 ISEN1 IRTN2 ISEN2 IRTN3 ISEN3 IRTN4 ISEN4 IRTN5 ISEN5 Part – A: CHL8325A B: CHL8328B 40 39 38 37 36 35 34 33 32 31 RCSP 1 30 RCSP_L2 RCSM 2 29 RCSM_L2 VCC 3 28 VCC VSEN 4 27 VSEN_L2 VRTN 5 26 VRTN_L2 RRES 6 25 PWM5 TSEN 7 24 PWM4 V18A 8 23 PWM3 VR_READY_L11 / PWRGD2 9 22 PWM2 VR_READY_L212 / PWROK 10 21 PWM1 CHL8325A/B 40 Pin 6x6 QFN Top View Notes 1 Pin definition in Intel & MPoL modes 2 Pin definition in AMD mode 11 12 13 14 15 16 17 18 19 20 VINSEN SV_ALERT1 / VFIXEN2 SV_CLK1 / SVC2 SV_DIO1 / SVD2 VR_HOT#1 / VRHOT_ICRIT#2 ENABLE SMB_ALERT# SMB_DIO SMB_CLK VAR_GATE_PM_ADDR (CHL8325A) TSEN2 (CHL8325B) 41 GND Figure 3: CHL8325A/B Package Top View, Enlarged Digital Multi-Phase Buck Controller IR3541 CHL8325A/B FUNCTIONAL BLOCK DIAGRAM V18A RCSP_L2 VCC VID_2 RSCM_L2 1.8V AFE_2 LDO VSEN_L2 VRTN_L2 ITOT_2 RCSP Vout1_Error Voltage ADC PWM1 RSCM Vout2_Error AFE_1 PWM2 VSEN VID_1 VRTN PWM3 PWM Generator ISEN1 PWM4 IP1 Mode Control IRTN1 PWM5 ISEN2 Control and Monitoring IP2 IRTN2 Σ ISEN3 Phase_ Period_1 Phase_ Period_2 VAR_GATE_PM_ADDR (CHL8325A) (IR3541 & CHL8325A) ITOT_1 IP3 IRTN3 ISEN4 Iout IP4 Vin IRTN4 ITOT_2 ISEN5 IP5 IRTN5 Σ Vout Temp Current ADC Fault Bus System Clock IP1 IP2 IP3 System Clock ADC Clocks IP4 MUX Clocks IP5 Phase_Period_1 TSEN2 (CHL8325B) Phase_Period_2 TSEN VINSEN Monitor ADC V3_3 SMB_DIO SMB_CLK SV_CLK1/SVC2 SV_DIO1/SVD2 EN Reference, Oscillator, State Control, Interfaces, Registers and NVM VID_1 VID_2 Iout Vin Temp Fault Bus SMB_ALERT# SV_ALERT#1/VFIXEN2 VR_HOT#1/VRHOT_ICRIT#2 VR_READY_L11/PWRGD2 VR_READY_L21/PWROK2 Notes 1 Pin definition in Intel & MPoL modes 2 Pin definition in AMD mode RRES Figure 4: IR3541 and CHL8325A/B Functional Block Diagram 3 June 21, 2013 | FINAL | V1.09