TDK5111
ASK/FSK Transmitter 315 MHz
Data Sheet
Revision 1.1, 2002-10-31
Wireless Control
Revision History
Current Version: Version 1.1 as of 31.10.2002
Previous Version: 1.0 as of March 2002
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
5-4, 5-7
5-4, 5-7
Tolerances of Lcosc specified
Value of Iclkout corrected
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Edition 31.10.2002
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TDK 5111
Product Info
Product Info
General Description
Features
Applications
The TDK 5111 is a single chip ASK/ Package
FSK transmitter for the frequency band
314-317 MHz. The IC offers a high
level of integration and needs only a
few external components. The device
contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special
circuit design and an unique power
amplifier design are used to save current consumption and therefore to save
battery life. Additionally features like a
power down mode, a low power detect
and a divided clock output are implemented. The IC can be used for both
ASK and FSK modulation.
■
fully integrated frequency synthesizer
■
voltage supply range 2.1 - 4 V
■
VCO without external components
■
power down mode
■
high efficiency power amplifier
typically 10 dBm @ 3 V
■
low voltage sensor
■
programmable divided clock output
for µC
■
frequency range 314-317 MHz
■
ASK/FSK modulation
■
low external component count
■
low supply current typ. 13 mA@3V
■
Keyless entry systems
■
Alarm systems
■
Remote control systems
■
Communication systems
Ordering Information
Type
Ordering Code
Package
TDK 5111
Q67100-H2046
P-TSSOP-16
available on tape and reel
Wireless Components
Product Info
Specification, October 2002
2
Product Description
Contents of this Chapter
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDK 5111
Product Description
2.1 Overview
The TDK 5111 is a single chip ASK/FSK transmitter for the frequency band 314317 MHz. The IC offers a high level of integration and needs only a few external
components. The device contains a fully integrated PLL synthesizer and a high
efficiency power amplifier to drive a loop antenna. A special circuit design and
an unique power amplifier design are used to save current consumption and
therefore to save battery life. Additional features like a power down mode, a low
power detect and a divided clock output are implemented. The IC can be used
for both ASK and FSK modulation.
2.2 Applications
■
Keyless entry systems
■
Remote control systems
■
Alarm systems
■
Communication systems
2.3 Features
Wireless Components
■
fully integrated frequency synthesizer
■
VCO without external components
■
high efficiency power amplifier typ. 10 dBm @ 3 V
■
frequency range 314-317 MHz
■
ASK/FSK modulation
■
low supply current typ. 13 mA @ 3 V
■
voltage supply range 2.1 - 4 V
■
power down mode
■
low voltage sensor
■
programmable divided clock output for µC
■
low external component count
2-2
Specification, October 2002
TDK 5111
Product Description
2.4 Package Outlines
Figure 2-1
Wireless Components
P-TSSOP-16
2-3
Specification, October 2002
3
Functional Description
Contents of this Chapter
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.5.1
3.4.5.2
3.4.5.3
3.4.5.4
3.4.6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Recommended timing diagrams for ASK- and FSK-Modulation . . 3-12
TDK 5111
Functional Description
3.1 Pin Configuration
PDWN
1
16
CSEL
LPD
2
15
FSEL
VS
3
14
PAOUT
LF
4
13
PAGND
TDK 5111
GND
5
12
FSKGND
ASKDTA
6
11
FSKOUT
FSKDTA
7
10
COSC
CLKOUT
8
9
CLKDIV
Pin_config.wmf
Figure 3-1
IC Pin Configuration
Table 3-1
Wireless Components
Pin No.
Symbol
Function
1
PDWN
Power Down Mode Control
2
LPD
Low Power Detect Output
3
VS
Voltage Supply
4
LF
Loop Filter
5
GND
6
ASKDTA
Amplitude Shift Keying Data Input
7
FSKDTA
Frequency Shift Keying Data Input
8
CLKOUT
Clock Driver Output
9
CLKDIV
Clock Divider Control
10
COSC
11
FSKOUT
Frequency Shift Keying Switch Output
12
FSKGND
Frequency Shift Keying Ground
13
PAGND
Power Amplifier Ground
14
PAOUT
Power Amplifier Output
15
FSEL
Frequency Range Selection: Has to be shorted to
ground for 315 MHz operation
16
CSEL
Crystal Frequency Selection: Has to be left open
Ground
Crystal Oscillator Input
3-2
Specification, October 2002
TDK 5111
Functional Description
3.2 Pin Definitions and Functions
Table 3-2
Pin
No.
Symbol
1
PDWN
Function
Interface Schematic1)
Disable pin for the complete transmitter circuit.
VS
40 µA ∗ (ASKDTA+FSKDTA) A logic low (PDWN < 0.7 V) turns off all
transmitter functions.
A logic high (PDWN > 1.5 V) gives access to
all transmitter functions.
5 kΩ
1
"ON"
150 kΩ
PDWN input will be pulled up by 40 µA internally by setting FSKDTA or ASKDTA to a
logic high-state.
250 kΩ
2
LPD
This pin provides an output indicating the
low-voltage state of the supply voltage VS.
VS
VS < 2.15 V will set LPD to the low-state.
40 µA
2
300 Ω
3
VS
Wireless Components
An internal pull-up current of 40 µA gives the
output a high-state at supply voltages above
2.15 V.
This pin is the positive supply of the transmitter electronics.
An RF bypass capacitor should be connected directly to this pin and returned to
GND (pin 5) as short as possible.
3-3
Specification, October 2002
TDK 5111
Functional Description
4
LF
Output of the charge pump and input of the
VCO control voltage.
The loop bandwidth of the PLL is 150 kHz
when only the internal loop filter is used.
The loop bandwidth may be reduced by
applying an external RC network referencing
to the positive supply VS (pin 3).
VS
140 pF
15 pF
35 kΩ
10 kΩ
VS
4
5
GND
6
ASKDTA
General ground connection.
VS
Digital amplitude modulation can be
imparted to the Power Amplifier through this
pin.
+1.2 V
A logic high (ASKDTA > 1.5 V or open)
enables the Power Amplifier.
60 kΩ
6
+1.1 V
90 kΩ
2.3 pF
7
30 µA
FSKDTA
VS
A logic low (ASKDTA < 0.5 V)
disables the Power Amplifier.
Digital frequency modulation can be
imparted to the Xtal Oscillator by this pin.
The VCO-frequency varies in accordance to
the frequency of the reference oscillator.
+1.2 V
60 kΩ
7
+1.1 V
90 kΩ
30 µA
A logic high (FSKDTA > 1.5V or open)
sets the FSK switch to a high impedance
state.
A logic low (FSKDTA < 0.5 V)
closes the FSK switch
from FSKOUT (pin 11) to FSKGND (pin 12).
A capacitor can be switched to the reference
crystal network this way. The Xtal Oscillator
frequency will be shifted giving the designed
FSK frequency deviation.
Wireless Components
3-4
Specification, October 2002
TDK 5111
Functional Description
8
CLKOUT
Clock output to supply an external device.
An external pull-up resistor has to be added
in accordance to the driving requirements of
the external device.
A clock frequency of 2.46 MHz is selected
by a logic low at CLKDIV input (pin 9).
A clock frequency of 615 kHz is selected by
a logic high at CLKDIV input (pin 9).
VS
8
300 Ω
9
CLKDIV
This pin is used to select the desired clock
division rate for the CLKOUT signal.
VS
+1.2 V
VS
A logic low (CLKDIV < 0.2 V) applied to this
pin selects the 2.46 MHz output signal at
5 µA
CLKOUT (pin 8).
60 kΩ
A logic high (CLKDIV open) applied to this
+0.8 V pin selects the 615 kHz output signal at
CLKOUT (pin 8).
60 kΩ
9
10
COSC
This pin is connected to the reference oscillator circuit.
The reference oscillator is working as a negative impedance converter. It presents a
negative resistance in series to an inductance at the COSC pin.
VS
VS
6 kΩ
10
100 µA
11
FSKOUT
This pin is connected to a switch to
FSKGND (pin 12).
VS
VS
The switch is closed when the signal at
FSKDTA (pin 7) is in a logic low state.
The switch is open when the signal at
FSKDTA (pin 7) is in a logic high state.
200 µA
1.5 kΩ
11
FSKOUT can switch an additional capacitor
to the reference crystal network to pull the
crystal frequency by an amount resulting in
the desired FSK frequency shift of the transmitter output frequency.
12
12
FSKGND
Wireless Components
Ground connection for FSK modulation output FSKOUT.
3-5
Specification, October 2002
TDK 5111
Functional Description
13
PAGND
Ground connection of the power amplifier.
The RF ground return path of the power
amplifier output PAOUT (pin 14) has to be
concentrated to this pin.
14
PAOUT
RF output pin of the transmitter.
14
A DC path to the positive supply VS has to
be supplied by the antenna matching network.
13
15
FSEL
This pin has to be shorted to ground to
select the 315 MHz transmitter frequency
range.
+1.2 V
VS
30 kΩ
15
+1.1 V
A logic low (FSEL < 0.5 V) applied to this pin
sets the transmitter to the 315 MHz frequency range.
90 kΩ
30 µA
16
CSEL
VS
+1.2 V
A logic high (FSEL open) applied to this pin
sets the transmitter to the 630 MHz frequency range.
This pin is used to select the desired reference frequency.
VS
5 µA
60 kΩ
16
A logic high (CSEL open) applied to this pin
sets the internal frequency divider to accept
a reference frequency of 9.84 MHz.
+0.8 V
60 kΩ
1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode.
In Power Down Mode, the values are zero or high-ohmic.
Wireless Components
3-6
Specification, October 2002
Figure 3-2
Wireless Components
3-7
Clock Output
Frequency
Select
0.615/2.46 MHz
9
10
11
FSK
Switch
Crystal
9,84 MHz
12
FSK
Ground
XTAL
Osc
Clock
Output
8
:2/8
:4/16
PFD
7
FSK
Data
Input
OR
1
Power
Down
Control
Crystal
Select
always open
16
:128/64
6
ASK
Data
Input
Loop
Filter
4
LF
VCO
15
:1/2
On
Ground
5
Power
AMP
Low Voltage
Sensor 2.2V
2
Low Power
Detect Output
Frequency Select
low for 315 MHz
Power
Supply
3
Positive
Supply
VS
Power
Amplifier
Output
Power
Amplifier
Ground
14
13
TDK 5111
Functional Description
3.3 Functional Block diagram
Funct_Block_Diagram.wmf
Functional Block diagram
Specification, October 2002
TDK 5111
Functional Description
3.4 Functional Blocks
3.4.1 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator
(VCO), an asynchronous divider chain, a phase detector, a charge pump and a
loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the
VCO is 630 MHz. The oscillator signal is fed both, to the synthesizer divider
chain and to the power amplifier. The overall division ratio of the asynchronous
divider chain is 64. The phase detector is a Type IV PD with charge pump. The
passive loop filter is realized on chip. In all 315 MHz applications, the CSEL pin
is not connected (logic high).
3.4.2 Crystal Oscillator
The crystal oscillator operates at 9.84 MHz. Frequencies of 615 kHz or 2.46
MHz are available at the clock output CLKOUT (pin 8) to drive the clock input
of a micro controller.
The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 3-3
CLKDIV (pin 9)
1)
2.46 MHz
615 kHz
Low
Open2)
1) Low:
2) Open:
CLKOUT Frequency
Voltage at pin < 0.2 V
Pin open
To achieve FSK transmission, the oscillator frequency can be detuned by a
fixed amount by switching an external capacitor via FSKOUT (pin 11).
The condition of the switch is controlled by the signal at FSKDTA (pin 7).
Table 3-4
FSKDTA (pin7)
1)
Low
Open2), High3)
1) Low:
2) Open:
3) High:
Wireless Components
FSK Switch
CLOSED
OPEN
Voltage at pin < 0.5 V
Pin open
Voltage at pin > 1.5 V
3-8
Specification, October 2002
TDK 5111
Functional Description
3.4.3 Power Amplifier
For operation at 315 MHz, the power amplifier is fed with the VCO frequency
divided by 2. It is possible to feed the power amplifier directly from the voltage
controlled oscillator. This is controlled by FSEL (pin 15) as described in the
table below. This is not recommended for this frequency range.
Table 3-5
FSEL (pin 15)
1)
315 MHz
630 MHz (not recommended)
Low
Open2)
1) Low:
2) Open:
Radiated Frequency Band
Voltage at pin < 0.5 V
Pin open
The Power Amplifier can be switched on and off
by the signal at ASKDTA (pin 6).
Table 3-6
ASKDTA (pin 6)
1)
Low
Open2), High3)
1) Low:
2) Open:
3) High:
Power Amplifier
OFF
ON
Voltage at pin < 0.5 V
Pin open
Voltage at pin > 1.5 V
The Power Amplifier has an Open Collector output at PAOUT (pin 14) and
requires an external pull-up coil to provide bias. The coil is part of the tuning and
matching LC circuitry to get best performance with the external loop antenna.
To achieve the best power amplifier efficiency, the high frequency voltage swing
at PAOUT (pin 14) should be twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 13) in order to reduce
the amount of coupling to the other circuits.
In all 315 MHz applications, the pin FSEL is connected to ground.
3.4.4 Low Power Detect
The supply voltage is sensed by a low power detector. When the supply voltage
drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To minimize the external component count, an internal pull-up current of 40 µA gives
the output a high-state at supply voltages above 2.15 V.
The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off
the PA as soon as the supply voltage drops below 2.15 V or it can be used to
inform a micro-controller to stop the transmission after the current data packet.
Wireless Components
3-9
Specification, October 2002
TDK 5111
Functional Description
3.4.5 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL
ENABLE MODE and the TRANSMIT MODE.
3.4.5.1 Power Down Mode
In the POWER DOWN MODE the complete chip is switched off.
The current consumption is typically 0.25 nA at 3 V 25°C.
This current doubles every 8°C. The values for higher temperatures are
typically 14 nA at 85°C and typically 600 nA at 125°C.
3.4.5.2 PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is
turned off to avoid undesired power radiation during the time the PLL needs to
settle. The turn on time of the PLL is determined mainly by the turn on time of
the crystal oscillator and is less than 1 msec when the specified crystal is used.
The current consumption is typically 4 mA.
3.4.5.3 Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is
turned on too.
The current consumption of the IC is typically 13 mA when using a proper transforming network at PAOUT, see Figure 4-1.
3.4.5.4 Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are
pulled up internally.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the
PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open.
The principle schematic of the power mode control circuitry is shown in
Figure 3-5.
Wireless Components
3 - 10
Specification, October 2002
TDK 5111
Functional Description
PDWN
ASKDTA
OR
FSKDTA
On
Bias
Source
Bias Voltage
120 kΩ
120 kΩ
FSKOUT
FSK
On
PLL
315
MHz
PA
PAOUT
IC
Power_Mode.wmf
Figure 3-5
Power mode control circuitry
Table 3-7 provides a listing of how to get into the different power modes
Table 3-7
PDWN
FSKDTA
ASKDTA
Low1)
Low, Open
Low, Open
Open2)
Low
Low
High3)
Low, Open, High
Low
Open
High
Low
High
Low, Open, High
Open, High
Open
High
Open, High
Open
Low, Open, High
High
1) Low:
2) Open:
3) High:
MODE
POWER DOWN
PLL ENABLE
TRANSMIT
Voltage at pin < 0.7 V (PDWN)
Voltage at pin < 0.5 V (FSKDTA, ASKDTA)
Pin open
Voltage at pin > 1.5 V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.
Wireless Components
3 - 11
Specification, October 2002
TDK 5111
Functional Description
3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
High
FSKDTA
Low
to
t
DATA
Open, High
ASKDTA
Low
to
t
min. 1 msec.
ASK_mod.wmf
Figure 3-6
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
DATA
High
FSKDTA
Low
to
t
to
t
High
ASKDTA
Low
min. 1 msec.
FSK_mod.wmf
Figure 3-7
Wireless Components
FSK Modulation
3 - 12
Specification, October 2002
TDK 5111
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to
t
DATA
Open, High
ASKDTA
Low
to
t
min. 1 msec.
Alt_ASK_mod.wmf
Figure 3-8
Alternative ASK Modulation
Alternative FSK Modulation
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to
t
to
t
Open, High
ASKDTA
Low
DATA
Open, High
FSKDTA
Low
to
t
min. 1 msec.
Alt_FSK_mod.wmf
Figure 3-9
Wireless Components
Alternative FSK Modulation
3 - 13
Specification, October 2002
4
Applications
Contents of this Chapter
4.1
4.2
4.3
4.4
4.5
4.6
4.7
50 Ohm-Output Testboard: Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2
50 Ohm-Output Testboard: Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
50 Ohm-Output Testboard: Bill of material . . . . . . . . . . . . . . . . . . . . . 4-4
50 Ohm-Output Testboard: Measurement results . . . . . . . . . . . . . . . 4-5
Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 4-6
Design hints on the buffered clock output (CLKOUT). . . . . . . . . . . . . 4-8
Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . 4-9
TDK 5111
Applications
4.1 50 Ohm-Output Testboard: Schematic
X2SMA
C8
C2
C4
L2
L1
VCC
C7
C3
C6
10
9
7
8
11
12
13
14
15
16
Q1
0.615 (2.46)
MHz
VCC
T1
6
5
4
3
VCC
2
1
TDK5111
C1
R3A
R3F
R4
R2
FSK
ASK
R1
C5
X1SMA
50ohm_test_v5.wmf
Figure 4-1
Wireless Components
50 Ω-Output testboard schematic
4-2
Specification, October 2002
TDK 5111
Applications
4.2 50 Ohm-Output Testboard: Layout
tda5110_v1_pcboben.pdf
Figure 4-2
Top Side of TDK 5111-Testboard with 50 Ω-Output.
It is the same board as used for the TDK5110.
tda5110_v1_pcbunten.pdf
Figure 4-3
Wireless Components
Bottom Side of TDK 5111-Testboard with 50 Ω-Output.
It is the same board as used for the TDK5110.
4-3
Specification, October 2002
TDK 5111
Applications
4.3 50 Ohm-Output Testboard: Bill of material
Table 4-1 Bill of material
Part
Value
R1
4.7kΩ
ASK
Specification
0805, ± 5%
R2
12kΩ
15kΩ
R3A
R3F
Wireless Components
FSK
0805, ± 5%
0805, ± 5%
15kΩ
0805, ± 5%
R4
open
0805, ± 5%
C1
47nF
0805, X7R, ± 10%
C2
47pF
0805, COG, ± 5%
C3
10pF
0805, COG, ± 1%
C4
330pF
0805, COG, ± 5%
C5
1nF
0805, X7R, ± 10%
C6
8.2pF
15pF
15pF: 0805, COG, ± 1%
8.2pF: 0805, COG, ± 0.1pF
C7
0Ω
Jumper
6.8pF
0805, COG, ± 0.1pF
0805, 0Ω Jumper
C8
22pF
0805, COG, ± 5%
L1
120nH
TOKO LL2012-J
L2
33nH
TOKO LL2012-J
Q1
9843.75 kHz,
CL=12pF
Tokyo Denpa TSS-3B
9843.75 kHz
Spec.No. 10-50221
IC1
TDK5111
T1
Push-button
replaced by a short
X1
SMA-S
SMA standing
X2
SMA-S
SMA standing
4-4
Specification, October 2002
TDK 5111
Applications
4.4 50 Ohm-Output Testboard: Measurement results
Note the specified operating range: 2.1 V to 4.0 V and −40°C to +125°C.
Pout over temperature TDK5111 315 MHz
14,00
Pout [dBm]
12,00
10,00
4,0V
8,00
3,0V
2,1V
6,00
2,0V
4,00
1,9V
2,00
0,00
-50
0
50
100
150
T [°C]
Pout_over_Temp_315.wmf
Figure 4-4
Pout over Temperature of the 50Ω-testboard with TDK5111 at 315 MHz
Is over temperature TDK5111 315 MHz
18,00
16,00
4,0V
Is [mA]
14,00
3,0V
2,1V
12,00
2,0V
10,00
1,9V
8,00
6,00
-50
0
50
100
150
T [°C]
is_over_temp_315.wmf
Figure 4-5
Wireless Components
Is over temperature of the 50Ω-testboard with TDK5111 at 315 MHz
4-5
Specification, October 2002
TDK 5111
Applications
4.5 Application Hints on the Crystal Oscillator
The crystal oscillator achieves a turn on time less than 1 msec when the
specified crystal is used. To achieve this, a NIC oscillator type is implemented
in the TDK 5111. The input impedance of this oscillator is a negative resistance
in series to an inductance. Therefore the load capacitance of the crystal CL
(specified by the crystal supplier) is transformed to the capacitance Cv.
-R
L
f, CL Cv
IC
Cv =
1
1
+ ω 2L
CL
(1)
CL:
crystal load capacitance for nominal frequency
ω:
angular frequency
L:
inductance of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced
by a short to ground. Assume a crystal frequency of 9.84 MHz and a crystal load
capacitance of CL = 12 pF. The inductance L at 9.84 MHz is about 4.4 µH.
Therefore C6 is calculated to 10 pF.
Cv =
Wireless Components
4-6
1
1
+ω 2L
CL
= C6
Specification, October 2002
TDK 5111
Applications
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as
shown below.
FSKDTA
FSKOUT
Csw
-R
L
f, CL Cv1
Cv2
COSC
IC
The frequency deviation of the crystal oscillator is multiplied with the divider
factor N of the Phase Locked Loop to the output of the power amplifier. In case
of small frequency deviations (up to +/- 1000 ppm), the two desired load
capacitances can be calculated with the formula below.
2(C 0 + CL )
∆f
)
(1 +
N * f1
C1
2(C 0 + CL )
∆f
)
1±
(1 +
N * f1
C1
CL # C 0
CL ± =
C L:
C 0:
f:
ω:
N:
df:
crystal load capacitance for nominal frequency
shunt capacitance of the crystal
frequency
ω = 2πf: angular frequency
division ratio of the PLL
peak frequency deviation
Because of the inductive part of the TDK 5111, these values must be corrected
by formula (1). The value of Cv± can be calculated.
Wireless Components
4-7
Specification, October 2002
TDK 5111
Applications
If the FSK switch is closed, Cv- is equal to Cv1 (C6 in the application diagram).
If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Cv 2 = C 7 =
Csw ∗ Cv1 − (Cv + ) ∗ (Cv1 + Csw)
(Cv + ) − Cv1
Csw:
parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
Remark:
These calculations are only approximations. The necessary values
depend on the layout also and must be adapted for the specific
application board.
The 50Ω-Output testboard shows an FSK-deviation of +/- 22.5 kHz, typically.
4.6 Design hints on the buffered clock output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL)
should be connected between this pin and the positive supply voltage. The
value of RL is depending on the clock frequency and the load capacitance CLD
(PCB board plus input capacitance of the microcontroller). RL can be calculated
to:
RL =
1
fCLKOUT * 8 * CLD
Table 4-2
fCLKOUT=
615 kHz
CL[pF]
RL[kOhm]
CL[pF]
RL[kOhm]
5
39
5
10
10
18
10
4.7
20
10
20
2.2
Remark:
Wireless Components
fCLKOUT=
2.46 MHz
To achieve a low current consumption and a low
spurious radiation, the largest possible RL should be chosen.
4-8
Specification, October 2002
TDK 5111
Applications
4.7 Application Hints on the Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is
characterized by a pulsed operation of the power amplifier transistor at a current
flow angle of θ Minimum Tamb + 10°C
Maximum fOUT + 1 MHz => Maximum Tamb − 10°C
Maximum fOUT + 1 MHz => Minimum VS + 50 mV, max. + 20 MHz.
Wireless Components
5-6
Specification, October 2002
TDK 5111
Reference
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C
Parameter
Symbol
Limit Values
Min
Typ
Unit
Test Conditions
Max
FSK Modulation Data Input (Pin 7)
FSK Switch on
VFSKDTA
0
0.5
V
FSK Switch off
VFSKDTA
1.5
VS
V
Input bias current FSKDTA
IFSKDTA
35
µA
VFSKDTA = VS
Input bias current FSKDTA
IFSKDTA
µA
VFSKDTA = 0 V
FSK data rate
fFSKDTA
20
kHz
Output current (High)
ICLKOUT
5
µA
VCLKOUT = VS
Saturation Voltage (Low)1)
VSATL
0.5
V
ICLKOUT = 0.6 mA
0.2
V
-20
Clock Driver Output (Pin 8)
Clock Divider Control (Pin 9)
Setting Clock Driver output
frequency fCLKOUT=2.46 MHz
VCLKDIV
Setting Clock Driver output
frequency fCLKOUT=615 kHz
VCLKDIV
Input bias current CLKDIV
ICLKDIV
Input bias current CLKDIV
ICLKDIV
0
30
-20
V
pin open
µA
VCLKDIV = VS
µA
VCLKDIV = 0 V
Crystal Oscillator Input (Pin 10)
Load capacitance
CCOSCmax
Serial Resistance of the crystal
3
Input inductance of the
COSC pin
4.4
5
pF
100
Ω
f = 9.84 MHz
6.1
µH
f = 9.84 MHz
FSK Switch Output (Pin 11)
On resistance
RFSKOUT
280
Ω
VFSKDTA = 0 V
On capacitance
CFSKOUT
6
pF
VFSKDTA = 0 V
Off resistance
RFSKOUT
kΩ
VFSKDTA = VS
Off capacitance
CFSKOUT
pF
VFSKDTA = VS
10
1.5
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA
Wireless Components
5-7
Specification, October 2002
TDK 5111
Reference
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C
Parameter
Symbol
Limit Values
Min
Typ
Max
Unit
Test Conditions
Power Amplifier Output (Pin 14)
Output Power 1) at 315 MHz
transformed to 50 Ohm.
POUT, 315
5.9
7.5
8.7
dBm
VS = 2.1 V
POUT, 315
7.7
10.4
12.4
dBm
VS = 3.0 V
VFSEL = 0 V
POUT, 315
8.4
11.7
14.2
dBm
VS = 4.0 V
0.5
V
35
µA
VFSEL = VS
µA
VFSEL = 0 V
V
pin open
µA
VCSEL = VS
µA
VCSEL = 0 V
Frequency Range Selection (Pin 15)
Transmit frequency 315 MHz
VFSEL
Input bias current FSEL
IFSEL
Input bias current FSEL
IFSEL
0
-20
Crystal Frequency Selection (Pin 16)
Crystal frequency 9.84 MHz
VCSEL
Input bias current CSEL
ICSEL
Input bias current CSEL
ICSEL
55
-25
1) Matching circuitry as used in the 50 Ohm-Output Testboard.
Range @ 2.1 V, +25°C: 7.5 dBm +/- 1 dBm
Typ. temperature dependency at 2.1 V: +0.2 dBm@-40°C and -0.6 dBm@+125°C, reference +25°C
Range @ 3.0 V, +25°C: 10.4 dBm +/- 2.0 dBm
Typ. temperature dependency at 3.0 V: -0.2 dBm@-40°C and -0.7 dBm@+125°C, reference +25°C.
Range @ 4.0 V, +25°C: 11.7 dBm +/- 2.5 dBm
Typ. temperature dependency at 4.0 V: -0.8 dBm@-40°C and -0.6 dBm@+125°C, reference +25°C.
Tolerances of the passive elements not taken into account.
A smaller load impedance reduces the supply-voltage dependency.
A higher load impedance reduces the temperature dependency.
Wireless Components
5-8
Specification, October 2002
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