W256H

W256 12 Output Buffer for 2 DDR and 3 SRAM DIMMS Features Functional Description • One input to 12 output buffer/drivers • Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS • One additional output for feedback • SMBus interface for individual output control • Low skew outputs (< 100 ps) The W256 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 12 outputs. Designers can configure these outputs to support 3 unbuffered standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can be used in conjunction with the W250-02 or similar clock synthesizer for the VIA Pro 266 chipset. The W256 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull-up). • Supports 266 MHz and 333 MHz DDR SDRAM • Dedicated pin for power management support • Space-saving 28-pin SSOP package Pin Configuration[1] Block Diagram VDD3.5_2.5 FBOUT BUF_IN SSOP Top View DDR0T_SDRAM0 DDR0C_SDRAM1 DDR1T_SDRAM2 SDATA SCLOCK PWR_DWN# DDR1C_SDRAM3 SMBus Decoding & Powerdown Control DDR2T_SDRAM4 DDR2C_SDRAM5 DDR3T_SDRAM6 FBOUT *PWR_DWN# DDR0T_SDRAM0 DDR0C_SDRAM1 VDD3.3_2.5 GND DDR1T_SDRAM2 DDR1C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR2T_SDRAM4 DDR2C_SDRAM5 VDD3.3_2.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SEL_DDR* DDR5T_SDRAM10 DDR5C_SDRAM11 VDD3.3_2.5 GND DDR4T_SDRAM8 DDR4C_SDRAM9 VDD3.3_2.5 GND DDR3T_SDRAM6 DDR3C_SDRAM7 GND SCLK SDATA DDR3C_SDRAM7 DDR4T_SDRAM8 DDR4C_SDRAM9 DDR5T_SDRAM10 DDR5C_SDRAM11 SEL_DDR Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. Cypress Semiconductor Corporation Document #: 38-07256 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 30, 2004 W256 Pin Summary Name Pins Description SEL_DDR 28 Input to configure for DDR-ONLY mode or STANDARD SDRAM mode. 1 = DDR-ONLY mode. 0 = STANDARD SDRAM mode. When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, all the buffers will be configured as DDR outputs. Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode. When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, all the buffers will be configured as STANDARD SDRAM outputs. Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode. SCLK 16 SMBus clock input. SDATA 15 SMBus data input. BUF_IN 10 Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V input for STANDARD SDRAM mode. FBOUT 1 Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V. PWR_DWN# 2 Active LOW input to enable Power Down mode; all outputs will be pulled LOW. DDR[0:5]T_SDRAM [0,2,4,6,8,10] 3, 7, 12, 19, 23, 27 Clock outputs. These outputs provide copies of BUF_IN. Voltage swing depends on VDD3.3_2.5 power supply. DDR[0:5]C_SDRAM 4, 8, 13, 18, 22, 26 [1,3,5,7,9, 11] Clock outputs. These outputs provide complementary copies of BUF_IN when SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is inactive. Voltage swing depends on VDD3.3_2.5 power supply. VDD3.3_2.5 5, 9, 14, 21, 25 Connect to 2.5V power supply when W256 is configured for DDR-ONLY mode. Connect to 3.3V power supply, when W256 is configured for standard SDRAM mode. GND 6, 11, 17, 20, 24 Ground. Document #: 38-07256 Rev. *C Page 2 of 9 W256 Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 — Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 — Bits 7, 6, 5, 4, 3, 2, 1, 0 .– . Byte N — Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0”. • SMBus Address for the W256 is: Table 1. A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 –– Byte 6: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description Bit 7 – Reserved, drive to 0 0 Bit 6 – Reserved, drive to 0 0 Bit 5 – Reserved, drive to 0 0 Bit 4 1 FBOUT 1 1 Bit 2 1 Reserved, drive to 0 Bit 1 23, 22 DDR4T_SDRAM8, DDR4C_SDRAM9 1 Bit 0 1 – Reserved, drive to 0 Document #: 38-07256 Rev. *C Bit Pin # Bit 7 – Bit 6 Description Default Reserved, drive to 0 1 19, 18 DDR3T_SDRAM6, DDR3C_SDRAM7 1 Bit 5 12, 13 DDR2T_SDRAM4, DDR2C_SDRAM5 1 Bit 4 – Reserved, drive to 0 1 Bit 3 – Reserved, drive to 0 1 Bit 2 7, 8 DDR1T_SDRAM2, DDR1C_SDRAM3 1 Bit 1 – Reserved, drive to 0 1 Bit 0 3, 4 DDR0T_SDRAM0, DDR0C_SDRAM1 1 Default Bit 3 27, 26 DDR5T_SDRAM10, DDR5C_SDRAM11 – Byte 7: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Page 3 of 9 W256 Maximum Ratings Supply Voltage to Ground Potential ..................–0.5 to +7.0V DC Input Voltage (except BUF_IN) ............ –0.5V to VDD+0.5 Storage Temperature .................................. –65°C to +150°C Static Discharge Voltage ............................................>2000V (per MIL-STD-883, Method 3015) Operating Conditions[2] Parameter Description Min. Typ. Max. Unit V VDD3.3 Supply Voltage 3.135 3.465 VDD2.5 Supply Voltage 2.375 2.625 V TA Operating Temperature (Ambient Temperature) 0 70 °C COUT Output Capacitance 6 pF CIN Input Capacitance 5 pF Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. Unit 0.8 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50 µA IIH Input HIGH Current VIN = VDD 50 µA IOH Output HIGH Current VDD = 2.375V VOUT = 1V –18 –32 mA IOL Output LOW Current VDD = 2.375V VOUT = 1.2V 26 35 mA VOL Output LOW Voltage[3] IOL = 12 mA, VDD = 2.375V VOH Voltage[3] IOH = –12 mA, VDD = 2.375V Output HIGH Current[3] For all pins except SMBus Max. 2.0 V 0.6 V 1.7 V IDD Supply (DDR-Only mode) Unloaded outputs, 133 MHz 400 mA IDD Supply Current (DDR-Only mode) Loaded outputs, 133 MHz 500 mA IDDS Supply Current PWR_DWN# = 0 100 µA VOUT Output Voltage Swing See Test Circuity (Refer to Figure 1) VDD + 0.6 V VOC Output Crossing Voltage (VDD/2) +0.1 V INDC Input Clock Duty Cycle 52 % 0.7 (VDD/2) –0.1 48 VDD/2 Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07256 Rev. *C Page 4 of 9 W256 Switching Characteristics[4] Parameter Name Test Conditions Min. Measured at 1.4V for 3.3V outputs Measured at VDD/2 for 2.5V outputs. Typ. Max. Unit 66 180 MHz INDC –5% INDC +5% % – Operating Frequency – Duty Cycle[4,5] = t2 ÷ t1 t3 SDRAM Rising Edge Rate[4] Measured between 0.4V and 2.4V 1.0 2.50 V/ns t4 SDRAM Falling Edge Rate [4] Measured between 2.4V and 0.4V 1.0 2.50 V/ns t3d DDR Rising Edge Rate[4] Measured between 20% to 80% of output (Refer to Figure 1) 0.5 1.50 V/ns t4d DDR Falling Edge Rate[4] Measured between 20% to 80% of output (Refer to Figure 1) 0.5 1.50 V/ns t5 Output to Output Skew[4] All outputs equally loaded 100 ps t6 Output t4o Output Skew for SDRAM[2] All outputs equally loaded 150 ps t7 SDRAM Buffer HH Prop. Delay[4] Input edge greater than 1 V/ns 5 10 ns t8 SDRAM Buffer LLProp. Delay[4] 5 10 ns Input edge greater than 1 V/ns Switching Waveforms Duty Cycle Timing t1 t2 All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V 2.4V 0.4V 3.3V 0V t4 t3 Output-Output Skew OUTPUT OUTPUT t5 Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns. Document #: 38-07256 Rev. *C Page 5 of 9 W256 Switching Waveforms (continued) SDRAM Buffer HH and LL Propagation Delay 1.5V INPUT 1.5V OUTPUT t6 t7 Figure 1 shows the differential clock directly terminated by a 120 Ω resistor. VCC Device Under Test Out VCC ) 60Ω VTR RT =120Ω Out ) 60Ω Receiver VCP Figure 1. Differential Signal Using Direct Termination Resistor Document #: 38-07256 Rev. *C Page 6 of 9 W256 Layout Example Single Voltage +3.3V Supply or 2.5V Supply FB VDD C2 0.005 µF G G G C1 G 1 G 2 3 4 G 5 V 6 G 7 8 9 V 10 11 G 12 13 14 V 28 27 26 V 25 G 24 23 22 V 21 G 20 19 18 G 17 16 15 G W256 G 10 µF G G G FB = Dale ILB1206 – 300 (300Ω @ 100 MHz) Cermaic Caps C1 = 10–22 µF G = VIA to GND plane layer C2 = 0.005 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 µF ceramic Ordering Information Ordering Code Package Type Operating Range W256H 28-pin SSOP Commercial W256HT 28-pin SSOP – Tape and Reel Commercial CYW256OXC 28-pin SSOP Commercial CYW256OXCT 28-pin SSOP – Tape and Reel Commercial Lead Free Document #: 38-07256 Rev. *C Page 7 of 9 W256 Package Drawings and Dimension 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Document #: 38-07256 Rev. *C Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. W256 Document History Page Document Title: W256 12 Output Buffer for 2 DDR and 3 SRAM DIMMS Document Number: 38-07256 REV. ECN NO. Issue Date Orig. of Change ** 110521 12/04/01 SZV Change from Spec number: 38-01083 to 38-07256 *A 112153 03/01/02 IKA Added 333 MHz for SDRAM Description of Change *B 122858 12/19/02 RBI Added power requirements to operating conditions information. *C 258671 See ECN RGL Added Lead Free Devices Document #: 38-07256 Rev. *C Page 9 of 9