XC866L2FRA5VBELXUMA1

8-Bit SAL-XC866 8-Bit Single-Chip Microcontroller Data Sheet V1.1 2012-12 Microcontrollers Edition 2012-12 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 8-Bit SAL-XC866 8-Bit Single-Chip Microcontroller Data Sheet V1.1 2012-12 Microcontrollers SAL-XC866 SAL-XC866 Data Sheet Revision History: 2012-12 V1.1 Previous Version: V1.0 2011-02 Page Subjects (major changes since last revision) - Removed the “preliminary” wording from the data sheet. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.1, 2012-12 SAL-XC866 Table of Contents Page 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2.1 2.2 2.3 2.4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 9 3 3.1 3.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.4.3 3.5 3.6 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.11.1 3.11.2 3.12 3.13 3.13.1 3.14 3.15 3.16 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAL-XC866 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 17 19 19 21 25 26 38 40 41 42 42 47 49 50 53 54 56 56 57 59 61 63 64 67 68 71 71 72 72 74 76 77 Data Sheet 1 V1.1, 2012-12 SAL-XC866 3.17 3.18 3.18.1 3.18.2 3.19 3.19.1 3.20 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.2.3.1 4.2.4 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5 5.1 5.2 5.3 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters (PG-TSSOP-38) . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 2 78 80 81 82 83 84 85 106 106 107 108 V1.1, 2012-12 8-Bit Single-Chip Microcontroller XC800 Family 1 SAL-XC866 Summary of Features • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers • On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 512 bytes of XRAM – 4/8/16 Kbytes of Flash (includes memory protection strategy) • I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (further features are on next page) 4K/ 8K/16K Bytes Flash On-Chip Debug Support Boot ROM 8K Bytes UART SSC Port 0 6-bit Digital I/O Capture/Compare Unit 16-bit Port 1 5-bit Digital I/O Compare Unit 16-bit Port 2 8-bit Digital/Analog Input Port 3 8-bit Digital I/O XC800 Core XRAM 512 Bytes RAM 256 Bytes Figure 1 Data Sheet Timer 0 16-bit Timer 1 16-bit Timer 2 16-bit Watchdog Timer ADC 10-bit 8-channel SAL-XC866 Functional Units 3 V1.1, 2012-12 SAL-XC866 Summary of Features Features (continued): • Reset generation – Power-On reset – Hardware reset – Brownout reset for core logic supply – Watchdog timer reset – Power-Down Wake-up reset • On-chip OSC and PLL for clock generation – PLL loss-of-lock detection • Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral • Programmable 16-bit Watchdog Timer (WDT) • Four ports – 19 pins as digital I/O – 8 pins as digital/analog input • 8-channel, 10-bit ADC • Three 16-bit timers – Timer 0 and Timer 1 (T0 and T1) – Timer 2 • Capture/compare unit for PWM signal generation (CCU6) • Full-duplex serial interface (UART) • Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • PG-TSSOP-38 pin package • Temperature range TA: – SAL (-40 to 150 °C) Data Sheet 4 V1.1, 2012-12 SAL-XC866 Summary of Features SAL-XC866 Variant Devices The SAL-XC866 product family features devices with different configurations and program memory sizes, offering cost-effective solution for different application requirements. The list of SAL-XC866 devices and their differences are summarized in Table 1. Table 1 Device Summary Device Type Device Name Power P-Flash Supply (V) Size (Kbytes) D-Flash Size (Kbytes) LIN BSL Support Flash1) SAL-XC866L-4FRA 5.0 12 4 Yes SAL-XC866L-2FRA 5.0 4 4 Yes SAL-XC866L-4FRA 3.3 12 4 Yes SAL-XC866L-2FRA 3.3 4 4 Yes 1) The flash memory (P-Flash and D-Flash) can be used for code or data. Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the type of delivery For the available ordering codes for the SAL-XC866, please refer to your responsible sales representative or your local distributor. As this document refers to all the derivatives, some descriptions may not apply to a specific product. For simplicity all versions are referred to by the term SAL-XC866 throughout this document. Data Sheet 5 V1.1, 2012-12 SAL-XC866 General Device Information 2 General Device Information 2.1 Block Diagram SAL-XC866 T0 & T1 UART Port 0 TMS MBC RESET VDDP VSSP VDDC VSSC 256-byte RAM + 64-byte monitor RAM P0.0 - P0.5 Port 1 XC800 Core P1.0 - P1.1 P1.5-P1.7 Port 2 Internal Bus 8-Kbyte Boot ROM 1) P2.0 - P2.7 CCU6 512-byte XRAM SSC 4/8/16-Kbyte Flash Timer 2 WDT 10 MHz On-chip OSC OCDS PLL Port 3 XTAL1 XTAL2 ADC Clock Generator VAREF VAGND P3.0 - P3.7 1) Includes 1-Kbyte monitor ROM Figure 2 Data Sheet SAL-XC866 Block Diagram 6 V1.1, 2012-12 SAL-XC866 General Device Information 2.2 Logic Symbol VDDP VSSP VAREF Port 0 6-Bit VAGND Port 1 5-Bit RESET XC866 MBC Port 2 8-Bit TMS XTAL1 Port 3 8-Bit XTAL2 VDDC Figure 3 Data Sheet VSSC SAL-XC866 Logic Symbol 7 V1.1, 2012-12 SAL-XC866 General Device Information 2.3 Pin Configuration MBC 1 38 RESET P0.3/SCLK_1/COUT63_1 2 37 P3.5/COUT62_0 P0.4/MTSR_1/CC62_1 3 36 P3.4/CC62_0 P0.5/MRST_1/EXINT0_0/COUT62_1 4 35 P3.3/COUT61_0 XTAL2 5 34 P3.2/CCPOS2_2/CC61_0 XTAL1 6 33 P3.1/CCPOS0_2/CC61_2/COUT60_0 VSSC 7 32 P3.0/CCPOS1_2/CC60_0 VDDC 8 31 P3.7/EXINT4/COUT63_0 P1.6/CCPOS1_1/T12HR_0/EXINT6 9 30 P3.6/CTRAP_0 P1.7/CCPOS2_1/T13HR_0 10 29 P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0 P1.1/EXINT3/TDO_1/TXD_0 XC866 TMS 11 28 P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1 12 27 P1.0/RXD_0/T2EX P0.2/CTRAP_2/TDO_0/TXD_1 13 26 P2.7/AN7 P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1 14 25 VAREF P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0 15 24 VAGND P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1 16 23 P2.6/AN6 P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2 17 22 P2.5/AN5 VDDP 18 21 P2.4/AN4 VSSP 19 20 P2.3/AN3 Figure 4 Data Sheet SAL-XC866 Pin Configuration, PG-TSSOP-38 Package (top view) 8 V1.1, 2012-12 SAL-XC866 General Device Information 2.4 Pin Definitions and Functions Table 2 Pin Definitions and Functions Symbol Pin Type Reset Function Number State P0 P0.0 I/O 12 Port 0 Port 0 is a 6-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC. Hi-Z TCK_0 T12HR_1 CC61_1 CLKOUT RXDO_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/Compare channel 1 Clock Output UART Transmit Data Output P0.1 14 Hi-Z TDI_0 T13HR_1 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Data Input COUT61_1 Output of Capture/Compare channel 1 EXF2_1 Timer 2 External Flag Output P0.2 13 PU CTRAP_2 TDO_0 TXD_1 P0.3 2 Hi-Z SCK_1 SSC Clock Input/Output COUT63_1 Output of Capture/Compare channel 3 P0.4 3 Hi-Z MTSR_1 CC62_1 P0.5 Data Sheet 4 Hi-Z CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/ Clock Output SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 MRST_1 SSC Master Receive Input/ Slave Transmit Output EXINT0_0 External Interrupt Input 0 COUT62_1 Output of Capture/Compare channel 2 9 V1.1, 2012-12 SAL-XC866 General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P1 I/O Port 1 Port 1 is a 5-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC. P1.0 27 PU RXD_0 T2EX UART Receive Data Input Timer 2 External Trigger Input P1.1 28 PU EXINT3 TDO_1 TXD_0 External Interrupt Input 3 JTAG Serial Data Output UART Transmit Data Output/ Clock Output P1.5 29 PU CCPOS0_1 EXINT5 EXF2_0 RXDO_0 CCU6 Hall Input 0 External Interrupt Input 5 TImer 2 External Flag Output UART Transmit Data Output P1.6 9 PU CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6 External Interrupt Input 6 P1.7 10 PU CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input P1.5 and P1.6 can be used as a software chip select output for the SSC. Data Sheet 10 V1.1, 2012-12 SAL-XC866 General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. P2.0 15 Hi-Z CCPOS0_0 CCU6 Hall Input 0 EXINT1 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0 P2.1 16 Hi-Z CCPOS1_0 CCU6 Hall Input 1 EXINT2 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1 P2.2 17 Hi-Z CCPOS2_0 CTRAP_1 CC60_3 AN2 CCU6 Hall Input 2 CCU6 Trap Input Input of Capture/Compare channel 0 Analog Input 2 P2.3 20 Hi-Z AN3 Analog Input 3 P2.4 21 Hi-Z AN4 Analog Input 4 P2.5 22 Hi-Z AN5 Analog Input 5 P2.6 23 Hi-Z AN6 Analog Input 6 P2.7 26 Hi-Z AN7 Analog Input 7 Data Sheet 11 V1.1, 2012-12 SAL-XC866 General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State P3 I Port 3 Port 3 is a bidirectional general purpose I/O port. It can be used as alternate functions for the CCU6. P3.0 32 Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/Compare channel 0 P3.1 33 Hi-Z CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/Compare channel 1 COUT60_0 Output of Capture/Compare channel 0 P3.2 34 Hi-Z CCPOS2_2 CCU6 Hall Input 2 CC61_0 Input/Output of Capture/Compare channel 1 P3.3 35 Hi-Z COUT61_0 Output of Capture/Compare channel 1 P3.4 36 Hi-Z CC62_0 P3.5 37 Hi-Z COUT62_0 Output of Capture/Compare channel 2 P3.6 30 PD CTRAP_0 P3.7 31 Hi-Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture/Compare channel 3 Data Sheet 12 Input/Output of Capture/Compare channel 2 CCU6 Trap Input V1.1, 2012-12 SAL-XC866 General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Function Number State VDDP 18 – – I/O Port Supply (3.3 V/5.0 V) Also used by EVR and analog modules. VSSP VDDC VSSC VAREF VAGND 19 – – I/O Port Ground 8 – – Core Supply Monitor (2.5 V) XTAL1 7 – – Core Supply Ground 25 – – ADC Reference Voltage 24 – – ADC Reference Ground 6 I Hi-Z External Oscillator Input (NC if not needed) XTAL2 5 O Hi-Z External Oscillator Output (NC if not needed) TMS 11 I PD Test Mode Select RESET 38 I PU Reset Input MBC1) 1 I PU Monitor & BootStrap Loader Control 1) An external pull-up device in the range of 4.7 kΩ to 100 kΩ is required to enter user mode. Alternatively MBC can be tied to high if alternate functions (for debugging) of the pin are not utilized. Data Sheet 13 V1.1, 2012-12 SAL-XC866 Functional Description 3 Functional Description 3.1 Processor Architecture The SAL-XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the SAL-XC866 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The SAL-XC866 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs. Figure 5 shows the CPU functional blocks. Internal Data Memory Core SFRs Register Interface External Data Memory External SFRs 16-bit Registers & Memory Interface ALU Opcode & Immediate Registers Multiplier / Divider Opcode Decoder Timer 0 / Timer 1 State Machine & Power Saving UART Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt Figure 5 Data Sheet Interrupt Controller CPU Block Diagram 14 V1.1, 2012-12 SAL-XC866 Functional Description 3.2 Memory Organization The SAL-XC866 CPU operates in the following five address spaces: • • • • • 8 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 512 bytes of XRAM memory a 128-byte Special Function Register area 4/8/16 Kbytes of Flash program memory Data Sheet 15 V1.1, 2012-12 SAL-XC866 Functional Description Figure 6 illustrates the memory address spaces of the SAL-XC866-4FR devices. FFFF H F200H XRAM 512 bytes F000H FFFF H F200H XRAM 512 bytes F000H E000H Boot ROM 8 Kbytes C000H B000H D-Flash Bank 4 Kbytes 1) A000H 3000H Indirect Address 2000H Internal RAM P-Flash Bank 2 4 Kbytes2) Direct Address FFH Special Function Registers 80H P-Flash Bank 1 4 Kbytes2) 1000H 7FH P-Flash Bank 0 4 Kbytes 1) Internal RAM 0000H 0000H 00H Program Space External Data Space Internal Data Space 1) For SAA -XC866-1FR device, physically one 4KByte D-Flash bank is mapped to both address range 0000H - 0FFFH and A000H AFFFH, and the shaded banks are not available. 2) For SAA -XC866-2FR device, the shaded banks are not available. Figure 6 Data Sheet Memory Map of SAL-XC866 Flash Devices 16 V1.1, 2012-12 SAL-XC866 Functional Description 3.2.1 Memory Protection Strategy The SAL-XC866 memory protection strategy includes: • Read-out protection: The Flash Memory can be enabled for read-out protection and ROM memory is always protected. • Program and erase protection: The Flash memory in all devices can be enabled for program and erase protection. Flash memory protection is available in two modes: • Mode 0: Only the P-Flash is protected; the D-Flash is unprotected • Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 3. Table 3 Flash Protection Modes Mode 0 1 Activation Program a valid password via BSL mode 6 Selection MSB of password = 0 MSB of password = 1 P-Flash contents Read instructions in the can be read by P-Flash Read instructions in the P-Flash or D-Flash P-Flash program Not possible and erase Not possible D-Flash contents Read instructions in any program can be read by memory Read instructions in the P-Flash or D-Flash D-Flash program Possible Not possible D-Flash erase Not possible Possible, on the condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the read-protected Flash contents, see Table 4, and the programmed password is erased. The Flash protection is then disabled upon the next reset. For XC866-2FR and XC866-4FR devices: The selection of protection type is summarized in Table 4. Data Sheet 17 V1.1, 2012-12 SAL-XC866 Functional Description Table 4 Flash Protection Type for XC866-2FR and XC866-4FR devices PASSWORD Type of Protection Flash Banks to Erase when Unprotected 1XXXXXXXB Flash Protection Mode 1 All Banks 0XXXXXXXB Flash Protection Mode 0 P-Flash Bank Although no protection scheme can be considered infallible, the SAL-XC866 memory protection strategy provides a very high level of protection for a general purpose microcontroller. Data Sheet 18 V1.1, 2012-12 SAL-XC866 Functional Description 3.2.2 Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: • Mapping • Paging 3.2.2.1 Address Extension by Mapping Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 7. SYSCON0 System Control Register 0 7 6 Reset Value: 00H 5 4 3 2 1 0 0 1 0 RMAP r rw r rw Field Bits Type Description RMAP 0 rw Special Function Register Map Control 0 The access to the standard SFR area is enabled. 1 The access to the mapped SFR area is enabled. 1 2 rw Reserved Returns the last value if read; should be written with 1. 0 1,[7:3] r Reserved Returns 0 if read; should be written with 0. Data Sheet 19 V1.1, 2012-12 SAL-XC866 Functional Description Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of SYSCON0 should not be modified. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Standard Area (RMAP = 0) FFH Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw …... Module n SFRs 80H SFR Data (to/from CPU) Mapped Area (RMAP = 1) FFH Module (n+1) SFRs Module (n+2) SFRs …... Module m SFRs 80H Direct Internal Data Memory Address Figure 7 Data Sheet Address Extension by Mapping 20 V1.1, 2012-12 SAL-XC866 Functional Description 3.2.2.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the SAL-XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 8. SFR Address (from CPU) PAGE 0 MOD_PAGE.PAGE SFR0 rw SFR1 …... SFRx PAGE 1 SFR0 SFR Data (to/from CPU) SFR1 …... SFRy …... PAGE q SFR0 SFR1 …... SFRz Module Figure 8 Data Sheet Address Extension by Paging 21 V1.1, 2012-12 SAL-XC866 Functional Description In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields MOD_STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: • Save the contents of PAGE in MOD_STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or • Overwrite the contents of PAGE with the contents of MOD_STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred) MOD_ST3 MOD_ST2 MOD_ST1 MOD_ST0 STNR PAGE value update from CPU Figure 9 Storage Elements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The SAL-XC866 supports local address extension for: • • • • Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers Data Sheet 22 V1.1, 2012-12 SAL-XC866 Functional Description The page register has the following definition: MOD_PAGE Page Register for module MOD 7 6 Reset Value: 00H 5 4 3 2 1 OP STNR 0 PAGE w w r rw 0 Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in MOD_STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of MOD_STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 Data Sheet MOD_ST0 is selected. MOD_ST1 is selected. MOD_ST2 is selected. MOD_ST3 is selected. 23 V1.1, 2012-12 SAL-XC866 Functional Description Field Bits Type Description OP [7:6] w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field MOD_STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field MOD_STx indicated by STNR. 0 3 r Reserved Returns 0 if read; should be written with 0. Data Sheet 24 V1.1, 2012-12 SAL-XC866 Functional Description 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD. PASSWD Password Register 7 Reset Value: 07H 6 5 4 3 2 1 0 PASS PROTECT _S MODE wh rh rw Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control bits 00 Scheme Disabled 11 Scheme Enabled (default) Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2 rh Bit Protection Signal Status bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. PASS [7:3] wh Password bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits. Data Sheet 25 V1.1, 2012-12 SAL-XC866 Functional Description 3.2.4 SAL-XC866 Register Overview The SFRs of the SAL-XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 5 to Table 13, with the addresses of the bitaddressable SFRs appearing in bold typeface. The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 Addr CPU Register Overview Register Name RMAP = 0 or 1 SP 81H Stack Pointer Register Bit Reset: 07H 82H DPL Reset: 00H Data Pointer Register Low 83H DPH Reset: 00H Data Pointer Register High 87H PCON Power Control Register Reset: 00H 88H TCON Timer Control Register Reset: 00H 89H TMOD Timer Mode Register Reset: 00H 8AH TL0 Timer 0 Register Low Reset: 00H 8BH TL1 Timer 1 Register Low Reset: 00H 8CH TH0 Timer 0 Register High Reset: 00H 8DH TH1 Timer 1 Register High Reset: 00H 98H SCON Reset: 00H Serial Channel Control Register 99H SBUF Reset: 00H Serial Data Buffer Register A2H EO Reset: 00H Extended Operation Register A8H IEN0 Reset: 00H Interrupt Enable Register 0 B8H IP Reset: 00H Interrupt Priority Register B9H IPH Reset: 00H Interrupt Priority Register High D0H PSW Reset: 00H Program Status Word Register E0H ACC Accumulator Register E8H IEN1 Reset: 00H Interrupt Enable Register 1 Reset: 00H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Data Sheet 7 6 DPL7 DPL6 rw rw DPH7 DPH6 rw rw SMOD rw TF1 TR1 rwh rw GATE1 0 rw r 5 4 3 1 SP rw DPL5 DPL4 DPL3 DPL2 rw rw rw rw DPH5 DPH4 DPH3 DPH2 rw rw rw rw 0 GF1 GF0 r rw rw TF0 TR0 IE1 IT1 rwh rw rwh rw T1M GATE0 0 rw rw r VAL rwh VAL rwh VAL rwh VAL rwh SM0 SM1 SM2 REN TB8 rw rw rw rw rw VAL rwh 0 TRAP_ EN r rw EA 0 ET2 ES ET1 rw r rw rw rw 0 PT2 PS PT1 r rw rw rw 0 PT2H PSH PT1H r rw rw rw CY AC F0 RS1 RS0 rw rwh rwh rw rw ACC7 ACC6 ACC5 ACC4 ACC3 rw rw rw rw rw ECCIP ECCIP ECCIP ECCIP EXM 3 2 1 0 rw rw rw rw rw 26 2 RB8 rwh 0 r EX1 rw PX1 rw PX1H rw OV rwh ACC2 rw EX2 rw 0 DPL1 DPL0 rw rw DPH1 DPH0 rw rw 0 IDLE r rw IE0 IT0 rwh rw T0M rw TI rwh RI rwh DPSEL 0 rw ET0 EX0 rw rw PT0 PX0 rw rw PT0H PX0H rw rw F1 P rwh rh ACC1 ACC0 rw rw ESSC EADC rw rw V1.1, 2012-12 SAL-XC866 Functional Description Table 5 CPU Register Overview (cont’d) Addr Register Name F0H B B Register Bit F8H IP1 Reset: 00H Interrupt Priority Register 1 F9H IPH1 Reset: 00H Interrupt Priority Register 1 High Reset: 00H Bit Field Type Bit Field Type Bit Field Type 7 6 5 4 3 B7 B6 B5 B4 B3 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP PXM 3 2 1 0 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP PXMH 3H 2H 1H 0H rw rw rw rw rw 2 1 0 B2 rw PX2 B1 rw PSSC B0 rw PADC rw rw rw PX2H PSSCH PADC H rw rw rw The system control SFRs can be accessed in the standard memory area (RMAP = 0). Table 6 Addr System Control Register Overview Register Name Bit 7 6 RMAP = 0 or 1 SYSCON0 Reset: 00H 8FH System Control Register 0 Bit Field Type RMAP = 0 SCU_PAGE Reset: 00H BFH Page Register for System Control Bit Field Type OP w Bit Field 0 RMAP = 0, Page 0 MODPISEL Reset: 00H B3H Peripheral Input Select Register Type B4H IRCON0 Reset: 00H Interrupt Request Register 0 Bit Field B5H IRCON1 Reset: 00H Interrupt Request Register 1 B7H EXICON0 Reset: 00H External Interrupt Control Register 0 BAH EXICON1 Reset: 00H External Interrupt Control Register 1 BBH NMICON NMI Control Register Reset: 00H Type Bit Field Type Bit Field Type Bit Field BCH NMISR NMI Status Register Reset: 00H Type Bit Field BDH BCON Reset: 00H Baud Rate Control Register BEH BG Reset: 00H Baud Rate Timer/Reload Register E9H FDCON Reset: 00H Fractional Divider Control Register EAH FDSTEP Reset: 00H Fractional Divider Reload Register EBH FDRES Reset: 00H Fractional Divider Result Register Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 5 4 3 2 1 0 r r STNR w JTAG TDIS rw JTAG TCKS rw 0 RMAP rw 0 r PAGE rwh 0 EXINT URRIS 0IS r rw rw EXINT EXINT EXINT EXINT EXINT EXINT EXINT 6 5 4 3 2 1 0 r rwh rwh rwh rwh rwh rwh rwh 0 ADCS ADCS RIR TIR EIR RC1 RC0 r rwh rwh rwh rwh rwh EXINT3 EXINT2 EXINT1 EXINT0 rw rw rw rw 0 EXINT6 EXINT5 EXINT4 r rw rw rw 0 NMI NMI NMI NMI NMI NMI NMI ECC VDDP VDD OCDS FLASH PLL WDT r rw rw rw rw rw rw rw 0 FNMI FNMI FNMI FNMI FNMI FNMI FNMI ECC VDDP VDD OCDS FLASH PLL WDT r rwh rwh rwh rwh rwh rwh rwh BGSEL 0 BREN BRPRE R rw r rw rw rw BR_VALUE rw BGS SYNEN ERRSY EOFSY BRK NDOV FDM FDEN N N rw rw rwh rwh rwh rwh rw rw STEP rw RESULT rh 0 RMAP = 0, Page 1 Data Sheet 27 V1.1, 2012-12 SAL-XC866 Functional Description Table 6 System Control Register Overview (cont’d) Addr Register Name B3H ID Identity Register Bit B4H PMCON0 Reset: 00H Power Mode Control Register 0 B5H PMCON1 Reset: 00H Power Mode Control Register 1 B6H OSC_CON OSC Control Register Reset: 08H Bit Field 0 Type r B7H PLL_CON PLL Control Register Reset: 20H Bit Field BAH CMCON Clock Control Register Reset: 00H Type Bit Field BBH PASSWD Password Register Reset: 07H Bit Field BCH FEAL Reset: 00H Flash Error Address Register Low BDH FEAH Reset: 00H Flash Error Address Register High BEH COCON Reset: 00H Clock Output Control Register E9H MISC_CON Reset: 00H Miscellaneous Control Register Reset: 01H Bit Field Type Bit Field Type Bit Field 7 6 0 r Type Type 5 4 PRODID r WDT WKRS WK RST SEL rwh rwh rw 0 3 PD rw T2_DIS rwh CCU _DIS rw OSC SS rw XPD OSC PD rw rw VCO BYP rw NDIV rw 0 r PASS Type Type Bit Field r Type rw SSC _DIS rw ORD RES rw PROTE CT_S rw COREL rw DFLAS HEN rwh r RMAP = 0, Page 3 B3H XADDRH Reset: F0H Bit Field On-Chip XRAM Address Higher Order Type ADC _DIS rw OSCR MODE rh ECCERRADDR[7:0] rh ECCERRADDR[15:8] rh TLEN COUT S rw rw 0 0 0 rw rwh rh OSC RESLD LOCK DISC rw rwh rh CLKREL w Bit Field Type Bit Field Type Bit Field 1 VERID r WS SD r VCO SEL rw 2 ADDRH rw The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 7 Addr WDT Register Overview Register Name RMAP = 1 WDTCON Reset: 00H BBH Watchdog Timer Control Register BCH WDTREL Reset: 00H Watchdog Timer Reload Register BDH WDTWINB Reset: 00H Watchdog Window-Boundary Count Register BEH WDTL Reset: 00H Watchdog Timer Register Low BFH WDTH Reset: 00H Watchdog Timer Register High Data Sheet Bit 7 6 Bit Field 0 Type Bit Field Type r 5 WINB EN rw 4 3 Bit Field WDT 0 PR rh r WDTREL rw WDTWINB Type Bit Field Type Bit Field Type WDT[7:0] rh WDT[15:8] rh 2 1 0 WDT EN rw WDT RS rwh WDT IN rw rw 28 V1.1, 2012-12 SAL-XC866 Functional Description The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 8 Addr Port Register Overview Register Name Bit 7 6 RMAP = 0 PORT_PAGE Reset: 00H B2H Page Register for PORT Bit Field Type OP w RMAP = 0, Page 0 P0_DATA 80H P0 Data Register Reset: 00H Bit Field Type 0 r 0 r 86H P0_DIR P0 Direction Register Reset: 00H Bit Field Type 90H P1_DATA P1 Data Register Reset: 00H Bit Field Type 91H P1_DIR P1 Direction Register Reset: 00H Bit Field Type A0H P2_DATA P2 Data Register Reset: 00H Bit Field Type A1H P2_DIR P2 Direction Register Reset: 00H Bit Field Type B0H P3_DATA P3 Data Register Reset: 00H Bit Field Type B1H P3_DIR P3 Direction Register Reset: 00H Bit Field Type RMAP = 0, Page 1 P0_PUDSEL Reset: FFH 80H P0 Pull-Up/Pull-Down Select Register P0_PUDEN Reset: C4H Bit Field P0 Pull-Up/Pull-Down Enable Register Type 90H P1_PUDSEL Reset: FFH P1 Pull-Up/Pull-Down Select Register A0H A1H B0H B1H Bit Field Type P1_PUDEN Reset: FFH Bit Field P1 Pull-Up/Pull-Down Enable Register Type P2_PUDSEL Reset: FFH Bit Field P2 Pull-Up/Pull-Down Select Register Type P2_PUDEN Reset: 00H Bit Field P2 Pull-Up/Pull-Down Enable Register Type P3_PUDSEL Reset: BFH Bit Field P3 Pull-Up/Pull-Down Select Register Type P3_PUDEN Reset: 40H Bit Field P3 Pull-Up/Pull-Down Enable Register Type RMAP = 0, Page 2 P0_ALTSEL0 Reset: 00H 80H P0 Alternate Select 0 Register 86H P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register 90H P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register 91H P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register B0H P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register Data Sheet Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P6 rwh P6 rw P6 rwh P6 rw P6 rwh P6 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw 29 P5 rwh P5 rw P5 rwh P5 rw P5 rwh P5 rw P5 rwh P5 rw P4 rwh P4 rw P5 rw P5 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P5 rw P5 rw 0 r 0 r P7 rw P7 rw P7 rw 4 STNR w 0 r 0 r Bit Field Type 86H 91H P7 rwh P7 rw P7 rwh P7 rw P7 rwh P7 rw 5 3 0 r P4 rwh P4 rw P4 rwh P4 rw P3 rwh P3 rw 0 r 0 r P3 rwh P3 rw P3 rwh P3 rw P4 rw P4 rw P3 rw P3 rw P4 rw P4 rw P4 rw P4 rw 0 r 0 r P3 rw P3 rw P3 rw P3 rw P4 rw P4 rw P4 rw 2 P3 rw P3 rw 0 r 0 r P3 rw 1 0 PAGE rwh P2 rwh P2 rw P2 rwh P2 rw P2 rwh P2 rw P1 rwh P1 rw P1 rwh P1 rw P1 rwh P1 rw P1 rwh P1 rw P0 rwh P0 rw P0 rwh P0 rw P0 rwh P0 rw P0 rwh P0 rw P2 rw P2 rw P1 rw P1 rw P0 rw P0 rw P2 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw P2 rw P2 rw P2 rw V1.1, 2012-12 SAL-XC866 Functional Description Table 8 Port Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0 B1H P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register Bit Field Type P7 rw P6 rw P5 rw P4 rw P3 rw P2 rw P1 rw P0 rw P4 rw P3 rw 0 r P3 rw P2 rw P6 rw P6 rw P5 rw P5 rw P5 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw 1 0 RMAP = 0, Page 3 P0_OD Reset: 00H 80H P0 Open Drain Control Register 90H P1_OD Reset: 00H P1 Open Drain Control Register B0H P3_OD Reset: 00H P3 Open Drain Control Register Bit Field Type Bit Field Type Bit Field Type 0 r P7 rw P7 rw P4 rw P2 rw The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 9 Addr ADC Register Overview Register Name Bit 7 6 5 RMAP = 0 ADC_PAGE D1H Page Register for ADC Reset: 00H Bit Field Type RMAP = 0, Page 0 CAH ADC_GLOBCTR Global Control Register Reset: 30H ANON rw CBH ADC_GLOBSTR Global Status Register Reset: 00H Bit Field Type Bit Field CCH ADC_PRAR Reset: 00H Priority and Arbitration Register CDH ADC_LCBR Reset: B7H Limit Check Boundary Register r ASEN1 ASEN0 0 rw rw r BOUND1 rw CEH ADC_INPCR0 Input Class Register 0 Type Bit Field Type Bit Field Type Bit Field CFH ADC_ETRCR Reset: 00H External Trigger Control Register Reset: 00H Type Bit Field Type RMAP = 0, Page 1 ADC_CHCTR0 Reset: 00H CAH Channel Control Register 0 CBH ADC_CHCTR1 Reset: 00H Channel Control Register 1 CCH ADC_CHCTR2 Reset: 00H Channel Control Register 2 CDH ADC_CHCTR3 Reset: 00H Channel Control Register 3 CEH ADC_CHCTR4 Reset: 00H Channel Control Register 4 CFH ADC_CHCTR5 Reset: 00H Channel Control Register 5 D2H ADC_CHCTR6 Reset: 00H Channel Control Register 6 D3H ADC_CHCTR7 Reset: 00H Channel Control Register 7 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type OP w 4 STNR w DW rw 2 0 r PAGE rwh CTC rw CHNR 0 0 r 0 SAM BUSY PLE rh r rh rh ARBM CSM1 PRIO1 CSM0 PRIO0 rw rw rw rw rw BOUND0 rw STC rw ETRSEL1 SYNEN SYNEN 1 0 rw rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 3 ETRSEL0 rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RMAP = 0, Page 2 Data Sheet 30 V1.1, 2012-12 SAL-XC866 Functional Description Table 9 ADC Register Overview (cont’d) Addr Register Name CAH ADC_RESR0L Result Register 0 Low Reset: 00H Bit CBH ADC_RESR0H Result Register 0 High Reset: 00H CCH ADC_RESR1L Result Register 1 Low Reset: 00H CDH ADC_RESR1H Result Register 1 High Reset: 00H CEH ADC_RESR2L Result Register 2 Low Reset: 00H CFH ADC_RESR2H Result Register 2 High Reset: 00H D2H ADC_RESR3L Result Register 3 Low Reset: 00H D3H ADC_RESR3H Result Register 3 High Reset: 00H RMAP = 0, Page 3 ADC_RESRA0L Reset: 00H CAH Result Register 0, View A Low CBH ADC_RESRA0H Reset: 00H Result Register 0, View A High CCH ADC_RESRA1L Reset: 00H Result Register 1, View A Low CDH ADC_RESRA1H Reset: 00H Result Register 1, View A High CEH ADC_RESRA2L Reset: 00H Result Register 2, View A Low CFH ADC_RESRA2H Reset: 00H Result Register 2, View A High D2H ADC_RESRA3L Reset: 00H Result Register 3, View A Low D3H ADC_RESRA3H Reset: 00H Result Register 3, View A High RMAP = 0, Page 4 ADC_RCR0 Reset: 00H CAH Result Control Register 0 CBH ADC_RCR1 Reset: 00H Result Control Register 1 CCH ADC_RCR2 Reset: 00H Result Control Register 2 CDH ADC_RCR3 Reset: 00H Result Control Register 3 CEH ADC_VFCR Reset: 00H Valid Flag Clear Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 7 6 5 RESULT[1:0] rh 0 r RESULT[1:0] rh 0 r RESULT[1:0] rh 0 r RESULT[1:0] rh 0 r Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field RESULT[2:0] rh RESULT[2:0] rh RESULT[2:0] rh Type Bit Field 3 2 Type VF DRC rh rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh VF DRC rh rh CHNR rh CHNR rh CHNR rh CHNR rh CHNR rh CHNR rh VFCTR WFR 0 IEN 0 Type Bit Field rw rw VFCTR WFR r 0 rw IEN r 0 Type Bit Field rw rw VFCTR WFR r 0 rw IEN r 0 Type Bit Field rw rw VFCTR WFR r 0 rw IEN r 0 r rw rw rw 0 r VFC3 w 0 CHNR rh Bit Field Type Bit Field Type 1 CHNR rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh RESULT[2:0] rh Type Bit Field 4 VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh r VFC2 w VFC1 w DRCT R rw DRCT R rw DRCT R rw DRCT R rw VFC0 w RMAP = 0, Page 5 Data Sheet 31 V1.1, 2012-12 SAL-XC866 Functional Description Table 9 ADC Register Overview (cont’d) Addr Register Name Bit CAH ADC_CHINFR Reset: 00H Channel Interrupt Flag Register Bit Field CBH ADC_CHINCR Reset: 00H Channel Interrupt Clear Register CCH ADC_CHINSR Reset: 00H Channel Interrupt Set Register Bit Field CDH ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register Bit Field CEH ADC_EVINFR Reset: 00H Event Interrupt Flag Register CFH ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register Bit Field D2H ADC_EVINSR Reset: 00H Event Interrupt Set Flag Register Bit Field D3H ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register Type Bit Field Type Type Type Bit Field Type Type Type Bit Field Type RMAP = 0, Page 6 CAH ADC_CRCR1 Reset: 00H Bit Field Conversion Request Control Register 1 Type ADC_CRPR1 Reset: 00H Bit Field CBH Conversion Request Pending Register 1 Type ADC_CRMR1 Reset: 00H Bit Field CCH Conversion Request Mode Register 1 Type CDH ADC_QMR0 Reset: 00H Bit Field Queue Mode Register 0 Type CEH ADC_QSR0 Reset: 20H Bit Field Queue Status Register 0 Type CFH ADC_Q0R0 Reset: 00H Bit Field Queue 0 Register 0 Type D2H ADC_QBUR0 Reset: 00H Bit Field Queue Backup Register 0 Type D2H ADC_QINR0 Reset: 00H Bit Field Queue Input Register 0 Type 7 6 5 4 3 2 1 CHINF CHINF CHINF CHINF CHINF CHINF CHINF 7 6 5 4 3 2 1 rh rh rh rh rh rh rh CHINC CHINC CHINC CHINC CHINC CHINC CHINC 7 6 5 4 3 2 1 w w w w w w w CHINS CHINS CHINS CHINS CHINS CHINS CHINS 7 6 5 4 3 2 1 w w w w w w w CHINP CHINP CHINP CHINP CHINP CHINP CHINP 7 6 5 4 3 2 1 rw rw rw rw rw rw rw EVINF EVINF EVINF EVINF 0 EVINF 7 6 5 4 1 rh rh rh rh r rh EVINC EVINC EVINC EVINC 0 EVINC 7 6 5 4 1 w w w w r w EVINS EVINS EVINS EVINS 7 6 5 4 w w w w EVINP EVINP EVINP EVINP 7 6 5 4 rw rw rw rw CH7 CH6 CH5 0 CHINF 0 rh CHINC 0 w CHINS 0 w CHINP 0 rw EVINF 0 rh EVINC 0 w EVINS EVINS 1 0 w w EVINP EVINP 1 0 rw rw 0 r 0 r CH4 0 rwh rwh rwh rwh r CHP7 CHP6 CHP5 CHP4 0 rwh Rsv rwh LDEV r CEV w Rsv r EXTR rh EXTR rh EXTR w w TREV w 0 r ENSI rh ENSI rh ENSI w rwh rwh r CLR SCAN ENSI ENTR ENGT PND w rw rw rw rw FLUSH CLRV TRMD ENTR ENGT w w rw rw rw EMPTY EV 0 rh rh r RF V 0 REQCHNR rh rh r rh RF V 0 REQCHNR rh rh r rh RF 0 REQCHNR w r w The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 10 Timer 2 Register Overview Addr Register Name Bit 7 6 3 2 1 0 C0H T2_T2CON Reset: 00H Timer 2 Control Register Bit Field TF2 EXF2 0 EXEN2 TR2 0 Type rwh rwh r rw rwh r CP/ RL2 rw Data Sheet 32 5 4 V1.1, 2012-12 SAL-XC866 Functional Description Table 10 Timer 2 Register Overview (cont’d) C1H T2_T2MOD Timer 2 Mode Register Reset: 00H Bit Field C2H T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low Bit Field Type C3H T2_RC2H Reset: 00H Bit Field Timer 2 Reload/Capture Register High Type T2_T2L Reset: 00H Bit Field Timer 2 Register Low Type T2_T2H Reset: 00H Bit Field Timer 2 Register High Type Type C4H C5H T2 T2 EDGE PREN REGS RHEN SEL rw rw rw rw RC2[7:0] rwh RC2[15:8] rwh THL2[7:0] rwh THL2[15:8] rwh T2PRE DCEN rw rw The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 Addr CCU6 Register Overview Register Name RMAP = 0 CCU6_PAGE Reset: 00H A3H Page Register for CCU6 Bit 7 Bit Field Type 6 OP w 5 4 STNR w RMAP = 0, Page 0 CCU6_CC63SRL Reset: 00H Bit Field 9AH Capture/Compare Shadow Register for Channel CC63 Low Type 9BH 9CH 9DH 9EH 9FH A4H A5H A6H A7H FAH CCU6_CC63SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC63 High Type CCU6_TCTR4L Reset: 00H Bit Field Timer Control Register 4 Low Type CCU6_TCTR4H Reset: 00H Bit Field Timer Control Register 4 High Type CCU6_MCMOUTSL Reset: 00H Bit Field Multi-Channel Mode Output Shadow Register Low Type CCU6_MCMOUTSH Reset: 00H Bit Field Multi-Channel Mode Output Shadow Type Register High CCU6_ISRL Reset: 00H Bit Field Capture/Compare Interrupt Status Reset Register Low Type CCU6_ISRH Reset: 00H Bit Field Capture/Compare Interrupt Status Reset Register High Type CCU6_CMPMODIFL Reset: 00H Bit Field Compare State Modification Register Low Type CCU6_CMPMODIFH Reset: 00H Bit Field Compare State Modification Register High Type CCU6_CC60SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 Low Type Data Sheet 3 2 1 0 r 0 PAGE rwh CC63SL rw CC63SH T12 STD w T13 STD w STRM CM w STRHP w T12 STR w T13 STR w 0 r 0 r rw DTRES 0 T12 RES w w T13 RES w MCMPS r 0 r T12RS T12RR w w T13RS T13RR w w rw CURHS rw EXPHS rw RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60 RCC60 M M F R F R F R w w w w w w w w RSTR RIDLE RWHE RCHE 0 RTRPF RT13 RT13 PM CM w w w w r w w w 0 MCC63 0 MCC62 MCC61 MCC60 S S S S r w r w w w 0 MCC63 0 MCC62 MCC61 MCC60 R R R R r w r w w w CC60SL rwh 33 V1.1, 2012-12 SAL-XC866 Functional Description Table 11 CCU6 Register Overview (cont’d) Addr Register Name FBH CCU6_CC60SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 High Type CCU6_CC61SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 Low Type CCU6_CC61SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 High Type CC60SH CCU6_CC62SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 Low Type CCU6_CC62SRH Reset: 00H Bit Field FFH Capture/Compare Shadow Register for Channel CC62 High Type RMAP = 0, Page 1 CCU6_CC63RL Reset: 00H Bit Field 9AH Capture/Compare Register for Channel CC63 Low Type CCU6_CC63RH Reset: 00H Bit Field 9BH Capture/Compare Register for Channel CC63 High Type CCU6_T12PRL Reset: 00H Bit Field 9CH Timer T12 Period Register Low Type CCU6_T12PRH Reset: 00H Bit Field 9DH Timer T12 Period Register High Type CCU6_T13PRL Reset: 00H Bit Field 9EH Timer T13 Period Register Low Type CC62SL FCH FDH Bit 7 6 5 CCU6_T13PRH Reset: 00H Timer T13 Period Register High A4H CCU6_T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low CCU6_T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High A5H A6H CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low A7H CCU6_TCTR0H Reset: 00H Timer Control Register 0 High FAH FBH FCH 2 1 0 DTE2 DTE1 DTE0 rw rw T12CLK rw rwh CC61SH rwh rwh CC62SH rwh CC63VL rh CC63VH rh T12PVL rwh T12PVH rwh T13PVL rwh Bit Field Type Bit Field Type T13PVH rwh DTM rw Bit Field 0 DTR2 DTR1 DTR0 Type Bit Field r CTM rh CDIR rh STE12 rh T12R Type Bit Field rw rh 0 rh STE13 r rh Type CCU6_CC60RL Reset: 00H Bit Field Capture/Compare Register for Channel CC60 Low Type CCU6_CC60RH Reset: 00H Bit Field Capture/Compare Register for Channel CC60 High Type CCU6_CC61RL Reset: 00H Bit Field Capture/Compare Register for Channel CC61 Low Type Data Sheet 3 rwh CC61SL FEH 9FH 4 0 r T12 PRE rh rw T13R T13 PRE rh rw CC60VL rw T13CLK rw rh CC60VH rh CC61VL rh 34 V1.1, 2012-12 SAL-XC866 Functional Description Table 11 CCU6 Register Overview (cont’d) Addr Register Name FDH CCU6_CC61RH Reset: 00H Bit Field Capture/Compare Register for Channel CC61 High Type CCU6_CC62RL Reset: 00H Bit Field Capture/Compare Register for Channel CC62 Low Type CCU6_CC62RH Reset: 00H Bit Field Capture/Compare Register for Channel CC62 High Type FEH FFH RMAP = 0, Page 2 CCU6_T12MSELL Reset: 00H 9AH T12 Capture/Compare Mode Select Register Low Bit 7 6 5 4 3 2 1 0 CC61VH rh CC62VL rh CC62VH rh Bit Field MSEL61 Type MSEL60 rw HSYNC CCU6_T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High Bit Field 9CH CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low Bit Field 9DH CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High 9EH CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low Bit Field Type rw rw 9FH CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High Bit Field 0 INPT13 rw INPT12 rw INPERR r rw rw rw A4H A5H A6H A7H FAH FBH Type Type Bit Field Type Type CCU6_ISSL Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register Low Type CCU6_ISSH Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register High Type CCU6_PSLR Reset: 00H Bit Field Passive State Level Register Type CCU6_MCMCTR Reset: 00H Bit Field Multi-Channel Mode Control Register Type CCU6_TCTR2L Reset: 00H Bit Field Timer Control Register 2 Low Type CCU6_TCTR2H Reset: 00H Bit Field Timer Control Register 2 High Type FCH CCU6_MODCTRL Reset: 00H Modulation Control Register Low FDH CCU6_MODCTRH Reset: 00H Modulation Control Register High FEH CCU6_TRPCTRL Reset: 00H Trap Control Register Low Data Sheet Bit Field Type Bit Field Type Bit Field Type DBYP rw MSEL62 9BH rw rw rw ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw ENSTR EN EN EN 0 EN ENT13 ENT13 IDLE WHE CHE TRPF PM CM rw rw rw rw r rw rw rw INPCHE INPCC62 INPCC61 INPCC60 ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60 M M F R F R F R w w w w w w w w SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13 PM CM w w w w w w w w PSL63 0 PSL rwh r rwh 0 SWSYN 0 SWSEL r rw r rw 0 T13TED T13TEC T13 T12 SSC SSC r rw rw rw rw 0 T13RSEL T12RSEL r rw rw MC 0 T12MODEN MEN rw r rw ECT13 0 T13MODEN O rw r rw 0 TRPM2 TRPM1 TRPM0 r rw rw rw 35 V1.1, 2012-12 SAL-XC866 Functional Description Table 11 CCU6 Register Overview (cont’d) Addr Register Name Bit FFH CCU6_TRPCTRH Reset: 00H Trap Control Register High Bit Field Type RMAP = 0, Page 3 CCU6_MCMOUTL Reset: 00H 9AH Multi-Channel Mode Output Register Low 9BH CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High 9CH CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low 9DH CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High 9EH CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low 9FH CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High A4H CCU6_PISEL2 Reset: 00H Port Input Select Register 2 FAH CCU6_T12L Reset: 00H Timer T12 Counter Register Low FBH CCU6_T12H Reset: 00H Timer T12 Counter Register High FCH CCU6_T13L Reset: 00H Timer T13 Counter Register Low FDH CCU6_T13H Reset: 00H Timer T13 Counter Register High FEH CCU6_CMPSTATL Reset: 00H Compare State Register Low FFH CCU6_CMPSTATH Reset: 00H Compare State Register High 7 6 Bit Field 0 Type r Type Bit Field Type 4 3 2 1 0 TRPEN rw R MCMP rh Bit Field Type Bit Field 5 TRPPE TRPEN N 13 rw rw rh 0 CURH EXPH r rh rh T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60 R R R rh rh rh rh rh rh rh rh STR IDLE WHE CHE TRPS TRPF T13PM T13CM rh rh rh rh Bit Field ISTRP ISCC62 rh rh ISCC61 rh rh ISCC60 Type Bit Field rw IST12HR rw ISPOS2 rw ISPOS1 rw ISPOS0 Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field rw rw 0 r rw rw IST13HR rw Type Bit Field Type Bit Field Type T12CVL rwh T12CVH rwh T13CVL rwh T13CVH rwh 0 CC63 CCPO CCPO CCPO ST S2 S1 S0 r rh rh rh rh T13IM COUT COUT CC62 COUT 63PS 62PS PS 61PS rwh rwh rwh rwh rwh CC62 ST rh CC61 PS rwh CC61 ST rh COUT 60PS rwh CC60 ST rh CC60 PS rwh 2 1 0 CIS rw SIS rw MIS rw The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 Addr SSC Register Overview Register Name Bit RMAP = 0 SSC_PISEL Reset: 00H A9H Port Input Select Register AAH SSC_CONL Control Register Low Programming Mode Operating Mode Data Sheet Reset: 00H Bit Field Type Bit Field Type 7 LB rw Bit Field Type 6 5 PO rw 0 r PH rw 0 r 36 4 HB rw 3 BM rw BC rh V1.1, 2012-12 SAL-XC866 Functional Description Table 12 SSC Register Overview Bit Field EN MS 0 Operating Mode Type Bit Field Type rw EN rw rw MS rw r 0 r ACH SSC_TBL Reset: 00H Transmitter Buffer Register Low Bit Field Type ADH SSC_RBL Reset: 00H Receiver Buffer Register Low Bit Field Type AEH SSC_BRL Reset: 00H Baudrate Timer Reload Register Low Bit Field Type AFH SSC_BRH Reset: 00H Baudrate Timer Reload Register High Bit Field Type ABH SSC_CONH Control Register High Programming Mode Reset: 00H AREN BEN rw rw BSY BE rh rwh TB_VALUE rw RB_VALUE rh BR_VALUE[7:0] rw BR_VALUE[15:8] rw PEN REN TEN rw PE rwh rw RE rwh rw TE rwh 1 0 The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Table 13 Addr OCDS Register Overview Register Name RMAP = 1 MMCR2 Reset: 0UH E9H Monitor Mode Control Register 2 Bit Bit Field Type F1H MMCR Reset: 00H Monitor Mode Control Register Bit Field F2H MMSR Reset: 00H Monitor Mode Status Register Bit Field F3H MMBPCR Reset: 00H BreakPoints Control Register Type F4H F5H F6H F7H Type Bit Field Type MMICR Reset: 00H Bit Field Monitor Mode Interrupt Control Register Type MMDR Reset: 00H Bit Field Monitor Mode Data Register Receive Type Transmit Bit Field Type HWBPSR Reset: 00H Bit Field Hardware Breakpoints Select Register Type HWBPDR Reset: 00H Bit Field Hardware Breakpoints Data Register Type Data Sheet 7 6 5 4 3 2 EXBC_ EXBC MBCO MBCO MMEP MMEP MMOD JENA P N_P N _P E w rw w rwh w rwh rh rh MEXIT MEXIT MSTEP MSTEP MRAM MRAM TRF RRF _P _P S_P S w rwh w rw w rwh rh rh MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0 M F F F F rw rh rwh rwh rwh rwh rwh rwh SWBC HWB3C rw rw DVECT DRETR rwh rwh 0 r 37 HWB2C 0 r HWB1 HWB0C C rw rw rw MMUIE MMUIE RRIE_ RRIE _P P w rw w rw MMRR rh MMTR w BPSEL _P w HWBPxx rw BPSEL rw V1.1, 2012-12 SAL-XC866 Functional Description 3.3 Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sectorization of the Flash memory allows each sector to be erased independently. Features • • • • • • • • • • • • • In-System Programming (ISP) via UART In-Application Programming (IAP) Error Correction Code (ECC) for dynamic correction of single-bit errors Background program and erase operations for CPU load minimization Support for aborting erase operation Minimum program width1) of 32-byte for D-Flash and 32-byte for P-Flash 1-sector minimum erase width 1-byte read access Flash is delivered in erased state (read all zeros) Operating supply voltage: 2.5 V ± 7.5 % Read access time: 3 × tCCLK = 120 ns2) Program time: 209440 / fSYS = 2.8 ms3) Erase time: 8175360 / fSYS = 109 ms3) 1) P-Flash: 32-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. 2) fsys = 75 MHz ± 7.5% (fCCLK = 25 MHz ± 7.5 %) is the maximum frequency range for Flash read access. fsys = 75 MHz ± 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for 3) obtaining the worst case timing. Data Sheet 38 V1.1, 2012-12 SAL-XC866 Functional Description Table 14 shows the Flash data retention and endurance targets. Table 14 Flash Data Retention and Endurance Retention Endurance1) Size TA=- 40 to 125 °C Remarks TA= 125 to 150 °C Program Flash 20 years 1,000 cycles up to 16 Kbytes2) for 16-Kbyte Variant 20 years 1,000 cycles up to 8 Kbytes2) for 8-Kbyte Variant 1,000 cycles3) Data Flash 4 Kbytes 1 Kbytes 10,000 cycles3) 1 Kbyte 256 bytes 2 years 70,000 cycles3) 512 bytes 128 bytes 2 years 100,000 cycles3) 128 bytes 20 years 5 years 32 bytes 1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance data specified in Table 14 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles. - the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles. 2) If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the device variant. Having more Data Flash will mean less Flash is available for Program Flash. 3) For TA=125 to 150°C, refers to programming of second 8 bytes (bytes 8 to 15) per WL Data Sheet 39 V1.1, 2012-12 SAL-XC866 Functional Description 3.3.1 Flash Bank Sectorization The SAL-XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of embedded Flash memory. These Flash memory sizes are made up of two or four 4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash (P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization shown in Figure 10. Both types can be used for code and data storage. The label “Data” neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations. Sector 2: 128-byte Sector 1: 128-byte Sector 9: Sector 8: Sector 7: Sector 6: 128-byte 128-byte 128-byte 128-byte Sector 5: 256-byte Sector 4: 256-byte Sector 3: 512-byte Sector 0: 3.75-Kbyte Sector 2: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte P-Flash Figure 10 D-Flash Flash Bank Sectorization The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to standard EPROMs, erased Flash memory cells contain 0s. The D-Flash bank is divided into more physical sectors for extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements. Data Sheet 40 V1.1, 2012-12 SAL-XC866 Functional Description 3.3.2 Flash Programming Width For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 11). 16 bytes 16 bytes 0000 ….. 0000 H 32 bytes (1 WL) 0000 ….. 0000 H Program 1 0000 ….. 0000 H 1111 ….. 1111 H 0000 ….. 0000 H 1111 ….. 1111 H Program 2 1111 ….. 0000 H 0000 ….. 0000 H 1111 ….. 0000 H 1111 ….. 1111 H Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0. Flash memory cells Figure 11 32-byte write buffers D-Flash Programming Note: When programming a D-Flash WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent “over-programming”. Data Sheet 41 V1.1, 2012-12 SAL-XC866 Functional Description 3.4 Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC866 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source. 3.4.1 Interrupt Source Figure 12 to Figure 16 give a general overview of the interrupt sources and illustrates the request and control flags. WDT Overflow FNMIWDT NMIISR.0 NMIWDT NMICON.0 PLL Loss of Lock FNMIPLL NMIISR.1 NMIPLL NMICON.1 Flash Operation Complete FNMIFLASH NMIISR.2 NMIFLASH >=1 VDD Pre-Warning 0073 FNMIVDD NMIISR.4 H Non Maskable Interrupt NMIVDD NMICON.4 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIVDDP NMICON.5 Flash ECC Error FNMIECC NMIISR.6 NMIECC NMICON.6 Figure 12 Data Sheet Non-Maskable Interrupt Request Sources 42 V1.1, 2012-12 SAL-XC866 Functional Description Highest Timer 0 Overflow TF0 TCON.5 ET0 000B H IEN0.1 Timer 1 Overflow IP.1/ IPH.1 TF1 TCON.7 ET1 001B H IEN0.3 UART Receive IP.3/ IPH.3 RI SCON.0 UART Transmit EINT0 Lowest Priority Level P o l l i n g >=1 TI ES SCON.1 IEN0.4 EXINT0 IE0 IRCON0.0 TCON.1 IT0 EX0 0023 H 0003 H IEN0.0 TCON.0 IP.4/ IPH.4 S e q u e n c e IP.0/ IPH.0 EXINT0 EXICON0.0/1 EINT1 EXINT1 IE1 IRCON0.1 TCON.3 IT1 EX1 0013 H IEN0.2 TCON.2 IP.2/ IPH.2 EXINT1 EA EXICON0.2/3 IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 13 Data Sheet Interrupt Request Sources (Part 1) 43 V1.1, 2012-12 SAL-XC866 Functional Description Timer 2 Overflow Highest TF2 T2_T2CON.7 T2EX EXF2 ET2 EXEN2 T2_T2CON.6 EDGES EL T2MOD.5 002B Lowest Priority Level H IEN0.5 T2_T2CON.3 IP.5/ IPH.5 >=1 Normal Divider Overflow NDOV FDCON.2 End of Synch Byte EOFSYN Synch Byte Error ERRSYN FDCON.6 SYNEN FDCON.5 FDCON.6 >=1 FDCON.4 EINT2 EXINT2 IRCON0.2 EX2 0043 H IP1.2/ IPH1.2 IEN1.2 EXINT2 S e q u e n c e EXICON0.4/5 EXINT3 EINT3 P o l l i n g IRCON0.3 EXINT3 EXICON0.6/7 EXINT4 EINT4 IRCON0.4 EXM EXINT4 >=1 EXICON1.0/1 004B H IEN1.3 IP1.3/ IPH1.3 EXINT5 EINT5 IRCON0.5 EXINT5 EXICON1.2/3 EA IEN0.7 EXINT6 EINT6 Bit-addressable IRCON0.6 EXINT6 Request flag is cleared by hardware EXICON1.4/5 Bit-addressable Request flag is cleared by hardware Figure 14 Data Sheet Interrupt Request Sources (Part 2) 44 V1.1, 2012-12 SAL-XC866 Functional Description Highest ADC Service Request 0 ADCSRC0 IRCON1.3 ADC Service Request 1 EADC 0033 H IEN1.0 IRCON1.4 SSC Error Lowest Priority Level >=1 ADCSRC1 IP1.0/ IPH1.0 EIR IRCON1.0 SSC Transmit TIR >=1 IRCON1.1 SSC Receive RIR ESSC 003B H IEN1.1 IP1.1/ IPH1.1 IRCON1.2 CCU6 Node 0 CCU6SR0 IRCON3.0 ECCIP0 0053 H IEN1.4 CCU6 Node 1 CCU6SR1 IRCON3.4 ECCIP1 005B H IEN1.5 CCU6 Node 2 IP1.5/ IPH1.5 S e q u e n c e CCU6SR2 IRCON4.0 ECCIP2 0063 H IEN1.6 CCU6 Node 3 IP1.4/ IPH1.4 P o l l i n g IP1.6/ IPH1.6 CCU6SR3 IRCON4.4 ECCIP3 006B H IEN1.7 IP1.7/ IPH1.7 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 15 Data Sheet Interrupt Request Sources (Part 3) 45 V1.1, 2012-12 SAL-XC866 Functional Description ICC60R CC60 ISL.0 ENCC60R IENL.0 >=1 ICC60F ISL.1 ENCC60F IENL.1 INPL.1 INPL.0 INPL.3 INPL.2 INPL.5 INPL.4 INPH.3 INPH.2 INPH.5 INPH.4 INPH.1 INPH.0 INPL.7 INPL.6 ICC61R CC61 ISL.2 ENCC61R IENL.2 >=1 ICC61F ISL.3 ENCC61F IENL.3 ICC62R CC62 ISL.4 ENCC62R IENL.4 >=1 ICC62F ISL.5 T12 One match T12OM T12 Period match T12PM ISL.6 ISL.7 T13 Compare match T13CM T13 Period match T13PM ISH.0 ISH.1 CTRAP Correct Hall Event >=1 ENT12PM IENL.7 ENT13CM IENH.0 >=1 ENT13PM IENH.1 ENTRPF IENH.2 >=1 WHE ISH.5 ENWHE IENH.5 CHE ISH.4 Multi-Channel Shadow Transfer ENT12OM IENL.6 TRPF ISH.2 Wrong Hall Event ENCC62F IENL.5 ENCHE IENH.4 >=1 STR ISH.7 ENSTR IENH.7 CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3 Figure 16 Data Sheet Interrupt Request Sources (Part 4) 46 V1.1, 2012-12 SAL-XC866 Functional Description 3.4.2 Interrupt Source and Vector Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the SAL-XC866 interrupt sources to the interrupt vector addresses and the corresponding interrupt source enable bits are summarized in Table 15. Table 15 Interrupt Source NMI Interrupt Vector Addresses Vector Address Assignment for SALXC866 Enable Bit SFR 0073H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMIPLL Flash NMI NMIFLASH VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003H External Interrupt 0 EX0 XINTR1 000BH Timer 0 ET0 XINTR2 0013H External Interrupt 1 EX1 XINTR3 001BH Timer 1 ET1 XINTR4 0023H UART ES XINTR5 002BH T2 ET2 IEN0 Fractional Divider (Normal Divider Overflow) LIN Data Sheet 47 V1.1, 2012-12 SAL-XC866 Functional Description Table 15 Interrupt Vector Addresses (cont’d) XINTR6 0033H ADC EADC XINTR7 003BH SSC ESSC XINTR8 0043H External Interrupt 2 EX2 XINTR9 004BH External Interrupt 3 EXM IEN1 External Interrupt 4 External Interrupt 5 External Interrupt 6 XINTR10 0053H CCU6 INP0 ECCIP0 XINTR11 005BH CCU6 INP1 ECCIP1 XINTR12 0063H CCU6 INP2 ECCIP2 XINTR13 006BH CCU6 INP3 ECCIP3 Data Sheet 48 V1.1, 2012-12 SAL-XC866 Functional Description 3.4.3 Interrupt Priority Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are available to program the priority level of each non-NMI interrupt vector. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 16. Table 16 Priority Structure within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2,Fractional Divider, LIN Interrupts 6 ADC Interrupt 7 SSC Interrupt 8 External Interrupt 2 9 External Interrupt [6:3] 10 CCU6 Interrupt Node Pointer 0 11 CCU6 Interrupt Node Pointer 1 12 CCU6 Interrupt Node Pointer 2 13 CCU6 Interrupt Node Pointer 3 14 Data Sheet 49 V1.1, 2012-12 SAL-XC866 Functional Description 3.5 Parallel Ports The SAL-XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, providing general purpose input functions, alternate input functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features: • • • • • Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals Input Port Features: • • • • • Configurable input driver Configurable pull-up/pull-down devices Receive of data through digital input (general purpose input) Alternate input for on-chip peripherals Analog input for ADC module Data Sheet 50 V1.1, 2012-12 SAL-XC866 Functional Description Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 VDDP Px_ALTSEL1 Alternate Select Register 1 enable AltDataOut 3 AltDataOut 2 AltDataOut1 enable 11 10 Pull Up Device Output Driver Pin 01 00 Px_Data Data Register enable Out In Input Driver Schmitt Trigger AltDataIn enable Pull Down Device Pad Figure 17 Data Sheet General Structure of Bidirectional Port 51 V1.1, 2012-12 SAL-XC866 Functional Description Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register VDDP enable enable Px_DATA Data Register In Input Driver Pull Up Device Pin Schmitt Trigger AltDataIn AnalogIn enable Pull Down Device Pad Figure 18 Data Sheet General Structure of Input Port 52 V1.1, 2012-12 SAL-XC866 Functional Description 3.6 Power Supply System with Embedded Voltage Regulator The SAL-XC866 microcontroller requires two different levels of power supply: • 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 19 shows the SAL-XC866 power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption. CPU & Memory On-chip OSC Peripheral logic ADC V D D C (2.5V) FLASH PLL GPIO Ports (P0-P3) XTAL1& XTAL2 EVR VD D P VSSP Figure 19 SAL-XC866 Power Supply System EVR Features: • • • • • Input voltage (VDDP): 3.3 V/5.0 V Output voltage (VDDC): 2.5 V ± 7.5% Low power voltage regulator provided in power-down mode VDDC and VDDP prewarning detection VDDC brownout detection Data Sheet 53 V1.1, 2012-12 SAL-XC866 Functional Description 3.7 Reset Control The SAL-XC866 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the SAL-XC866 is first powered up, the status of certain pins (see Table 18) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 20. VDDP capacitor value is 300 nF. VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF. Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 μs once VDDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 μs, the RESET pin should be held low for 500 μs typically. See Figure 21. 3.3/5V e.g. 300nF VSSP typ. 100nF VDDP 220nF VDDC VSSC RESET EVR 30k XC866 Figure 20 Data Sheet Reset Circuitry 54 V1.1, 2012-12 SAL-XC866 Functional Description Voltage 5V VDDP 2.5V 2.3V 0.9*VDDC VDDC Time Voltage RESET with capacitor 5V < 0.4V 0V Time typ. < 50 us Figure 21 VDDP, VDDC and VRESET during Power-on Reset The second type of reset in SAL-XC866 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. To ensure the recognition of the hardware reset, pin RESET must be held low for at least 100 ns. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode. Data Sheet 55 V1.1, 2012-12 SAL-XC866 Functional Description 3.7.1 Module Reset Behavior Table 17 shows how the functions of the SAL-XC866 are affected by the various reset types. A “ ” means that this function is reset to its default state. Table 17 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset CPU Core Peripherals On-Chip Static RAM Not affected, Not affected, Not affected, Affected, un- Affected, unreliable reliable reliable reliable reliable Oscillator, PLL Not affected Port Pins EVR The voltage Not affected regulator is switched on FLASH NMI Disabled 3.7.2 Disabled Booting Scheme When the SAL-XC866 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 18 shows the available boot options in the SAL-XC866. Table 18 MBC SAL-XC866 Boot Selection TMS P0.0 Type of Mode PC Start Value 1 0 x User Mode; on-chip OSC/PLL non-bypassed 0000H 0 0 x BSL Mode; on-chip OSC/PLL non-bypassed 0000H 0 1 0 OCDS Mode1); on-chip OSC/PLL nonbypassed 0000H 1 1 0 Standalone User (JTAG) Mode2); on-chip OSC/PLL non-bypassed (normal) 0000H 1) 2) The OCDS mode is not accessible if Flash is protected. Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose. Data Sheet 56 V1.1, 2012-12 SAL-XC866 Functional Description 3.8 Clock Generation Unit The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the SAL-XC866. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state. Features: • • • • • Phase-Locked Loop (PLL) for multiplying clock source by different factors PLL Base Mode Prescaler Mode PLL Mode Power-down mode support The CGU consists of an oscillator circuit and a PLL.In the SAL-XC866, the oscillator can be from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator (4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down. OSC fosc P:1 fp fn osc fail detect OSCR lock detect LOCK PLL core fvco 1 0 K:1 fsys N:1 OSCDISC Figure 22 Data Sheet NDIV VCOBYP CGU Block Diagram 57 V1.1, 2012-12 SAL-XC866 Functional Description The clock system provides three ways to generate the system clock: PLL Base Mode The system clock is derived from the VCO base (free running) frequency clock divided by the K factor. 1 f SYS = f VCObase × ---K Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. 1 f SYS = f OSC × ------------P×K PLL Mode The system clock is derived from the oscillator clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. N f SYS = f OSC × ------------P×K Table 19 shows the settings of bits OSCDISC and VCOBYP for different clock mode selection. Table 19 Clock Mode Selection OSCDISC VCOBYP Clock Working Modes 0 0 PLL Mode 0 1 Prescaler Mode 1 0 PLL Base Mode 1 1 PLL Base Mode Note: When oscillator clock is disconnected from PLL, the clock mode is PLL Base mode regardless of the setting of VCOBYP bit. System Frequency Selection For the SAL-XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to obtain the required system frequency, fsys, the value of N can be selected by bit NDIV for different oscillator inputs. Table 20 provides examples on how fsys = 75 MHz can be obtained for the different oscillator sources. Data Sheet 58 V1.1, 2012-12 SAL-XC866 Functional Description Table 20 System frequency (fsys = 75 MHz) Oscillator fosc N P K fsys On-chip 10 MHz 15 1 2 75 MHz External 10 MHz 15 1 2 75 MHz 5 MHz 30 1 2 75 MHz Table 21 shows the VCO range for the SAL-XC866. Table 21 VCO Range fVCOmin fVCOmax fVCOFREEmin fVCOFREEmax Unit 150 200 20 80 MHz 100 150 10 80 MHz 3.8.1 Recommended External Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz to 12 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 23 can be used as starting points for the negative resistance evaluation and for non-productive systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor. Figure 23 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. Data Sheet 59 V1.1, 2012-12 SAL-XC866 Functional Description fO SC XTAL1 4 - 12 MHz RQ Ex ternal Cloc k Signal XC866 Oscillator XC866 Oscillator RX2 XTAL2 CX1 XTAL2 CX2 Fundamental Mode Cry s tal VSS VSS Cry s tal Frequenc y C X1 , C X2 4 MHz 8 MHz 10 MHz 12 MHz 33 18 15 12 1) pF pF pF pF RX2 1) 0 0 0 0 Clock_EXOSC 1) Note that these are evaluation start values! Figure 23 fO SC XTAL1 External Oscillator Circuitries Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Data Sheet 60 V1.1, 2012-12 SAL-XC866 Functional Description 3.8.2 Clock Management The CGU generates all clock signals required within the microcontroller from a single clock, fsys. During normal system operation, the typical frequencies of the different modules are as follow: • • • • CPU clock: CCLK, SCLK = 25 MHz CCU6 clock: FCLK = 25 MHz Other peripherals: PCLK = 25 MHz Flash Interface clock: CCLK3 = 75 MHz and CCLK = 25 MHz In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the resulting output frequency has 50% duty cycle. Figure 24 shows the clock distribution of the SAL-XC866. CLKREL FCLK OSC fosc PLL CCU6 PCLK fsys /3 Peripherals SCLK CCLK N,P,K CCLK3 CORE FLASH Interface COREL COUTS TLEN Toggle Latch CLKOUT Figure 24 Data Sheet Clock Generation from fsys 61 V1.1, 2012-12 SAL-XC866 Functional Description For power saving purposes, the clocks may be disabled or slowed down according to Table 22. Table 22 System frequency (fsys = 75 MHz) Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the peripherals, including CCU6, are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator and PLL are switched off. Data Sheet 62 V1.1, 2012-12 SAL-XC866 Functional Description 3.9 Power Saving Modes The power saving modes of the SAL-XC866 provide flexible power consumption through a combination of techniques, including: • • • • Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power-down of the entire system with fast restart capability After a reset, the active mode (normal operating mode) is selected by default (see Figure 25) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are: • Idle mode • Slow-down mode • Power-down mode ACTIVE any interrupt & SD=0 set PD bit set IDLE bit set SD bit IDLE clear SD bit set IDLE bit any interrupt & SD=1 Figure 25 Data Sheet EXINT0/RXD pin & SD=0 POWER-DOWN set PD bit SLOW-DOWN EXINT0/RXD pin & SD=1 Transition between Power Saving Modes 63 V1.1, 2012-12 SAL-XC866 Functional Description 3.10 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an SAL-XC866 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the SAL-XC866 will be aborted in a user-specified time period. In debug mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features: • • • • • 16-bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary Selectable input frequency of fPCLK/2 or fPCLK/128 Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 26 shows the block diagram of the WDT unit. WDT Control Clear 1:2 MUX f PCLK WDTREL WDT Low Byte WDT High Byte 1:128 Overflow/Time-out Control & Window-boundary control WDTTO WDTRST WDTIN ENWDT Logic ENWDT_P Figure 26 Data Sheet WDTWINB WDT Block Diagram 64 V1.1, 2012-12 SAL-XC866 Functional Description If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is entered. The prewarning period lasts for 30H count, after which the system is reset (assert WDTRST). The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value ( * 28). The time period for an overflow of the WDT is programmable in two ways: • the input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128 • the reload value WDTREL for the high byte of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: ( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 ) P WDT = 2----------------------------------------------------------------------------------------------------f PCLK If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 27. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not be smaller than WDTREL. Count FFFF H WDTWINB WDTREL time No refresh allowed Figure 27 Data Sheet Refresh allowed WDT Timing Diagram 65 V1.1, 2012-12 SAL-XC866 Functional Description Table 23 lists the possible watchdog time range that can be achieved for different module clock frequencies. Some numbers are rounded to 3 significant digits. Table 23 Reload value in WDTREL Watchdog Time Ranges Prescaler for fPCLK 2 (WDTIN = 0) 128 (WDTIN = 1) 25 MHz 25 MHz FFH 20.5 μs 1.31 ms 7FH 2.64 ms 169 ms 00H 5.24 ms 336 ms Data Sheet 66 V1.1, 2012-12 SAL-XC866 Functional Description 3.11 Universal Asynchronous Receiver/Transmitter The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. Features: • Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first – fixed or variable baud rate • Receive buffered • Multiprocessor communication • Interrupt generation on the completion of a data transmission or reception The UART can operate in four asynchronous modes as shown in Table 24. Data is transmitted on TXD and received on RXD. Table 24 UART Modes Operating Mode Mode 0: 8-bit shift register Baud Rate fPCLK/2 Mode 1: 8-bit shift UART Variable Mode 2: 9-bit shift UART fPCLK/32 or fPCLK/64 Mode 3: 9-bit shift UART Variable There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to either fPCLK/32 or fPCLK/64. The variable baud rate is set by either the underflow rate on the dedicated baud-rate generator, or by the overflow rate on Timer 1. Data Sheet 67 V1.1, 2012-12 SAL-XC866 Functional Description 3.11.1 Baud-Rate Generator The baud-rate generator is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 28. Fractional Divider 8-Bit Reload Value FDSTEP 1 FDM 1 FDEN&FDM 0 Adder fDIV 00 01 FDRES FDEN 0 1 0 11 fMOD (overflow) 10 8-Bit Baud Rate Timer fBR R fPCLK Prescaler fDIV clk 11 10 NDOV 01 ‘0’ Figure 28 00 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and is clocked by either the output of the fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12. The baud rate (fBR) value is dependent on the following parameters: • Input clock fPCLK • Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON • Fractional divider (STEP/256) defined by register FDSTEP (to be considered only if fractional divider is enabled and operating in fractional divider mode) Data Sheet 68 V1.1, 2012-12 SAL-XC866 Functional Description • 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG The following formulas calculate the final baud rate without and with the fractional divider respectively: f PCLK BRPRE - where 2 baud rate = ---------------------------------------------------------------------------------× ( BR_VALUE + 1 ) > 1 BRPRE 16 × 2 × ( BR_VALUE + 1 ) f PCLK - × STEP --------------baud rate = ---------------------------------------------------------------------------------BRPRE 256 16 × 2 × ( BR_VALUE + 1 ) The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 25 MHz, the maximum achievable baud rate is 0.78 MBaud. Standard LIN protocol can support a maximum baud rate of 20kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for greater accuracy. Table 25 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractional divider is disabled and a module clock of 25 MHz is used. Table 25 Typical Baud rates for UART with Fractional Divider disabled Baud rate Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) Deviation Error 19.2 kBaud 1 (BRPRE=000B) 81 (51H) -0.47 % 9600 Baud 1 (BRPRE=000B) 162 (A2H) -0.47 % 4800 Baud 2 (BRPRE=001B) 162 (A2H) -0.47 % 2400 Baud 4 (BRPRE=010B) 162 (A2H) -0.47 % The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 26 lists the resulting deviation errors from generating a baud rate of 115.2 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Data Sheet 69 V1.1, 2012-12 SAL-XC866 Functional Description Table 26 fPCLK 25 MHz Deviation Error for UART with Fractional Divider enabled STEP Prescaling Factor Reload Value (BR_VALUE + 1) (2BRPRE) 1 Deviation Error 10 (AH) 189 (BDH) +0.14 % 12.5 MHz 1 6 (6H) 226 (E2H) -0.22 % 6.25 MHz 1 3 (3H) 226 (E2H) -0.22 % Data Sheet 70 V1.1, 2012-12 SAL-XC866 Functional Description 3.11.2 Baud Rate Generation using Timer 1 In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: [3.1] SMOD 2 × f PCLK Mode 1, 3 baud rate = ---------------------------------------------------32 × 2 × ( 256 – TH1 ) 3.12 Normal Divider Mode (8-bit Auto-reload Timer) Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 28). Once the fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: [3.2] f MOD Data Sheet 1 = f DIV × -----------------------------256 – STEP 71 V1.1, 2012-12 SAL-XC866 Functional Description 3.13 LIN Protocol The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 29. The frame consists of the: • • • • header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field response time data bytes (according to UART protocol) checksum Frame slot Frame Header Synch Figure 29 3.13.1 Response space Protected identifier Interframe space Response Data 1 Data 2 Data N Checksum Structure of LIN Frame LIN Header Transmission LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. Data Sheet 72 V1.1, 2012-12 SAL-XC866 Functional Description The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame. Data Sheet 73 V1.1, 2012-12 SAL-XC866 Functional Description 3.14 High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Features: • Master and slave mode operation – Full-duplex or half-duplex operation • Transmit and receive buffered • Flexible data format – Programmable number of data bits: 2 to 8 bits – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock • Variable baud rate • Compatible with Serial Peripheral Interface (SPI) • Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error) Data Sheet 74 V1.1, 2012-12 SAL-XC866 Functional Description Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 30 shows the block diagram of the SSC. PCLK Baud-rate Generator SS_CLK Clock Control MS_CLK Shift Clock RIR SSC Control Block Register CON Status Receive Int. Request TIR Transmit Int. Request EIR Error Int. Request Control TXD(Master) RXD(Slave) Pin Control 16-Bit Shift Register TXD(Slave) RXD(Master) Transmit Buffer Register TB Receive Buffer Register RB Internal Bus Figure 30 Data Sheet SSC Block Diagram 75 V1.1, 2012-12 SAL-XC866 Functional Description 3.15 Timer 0 and Timer 1 Timers 0 and 1 are count-up timers which are incremented every machine cycle, or in terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be configured in four different operating modes for use in a variety of applications, see Table 27. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 27 Timer 0 and Timer 1 Modes Mode Operation 0 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 1 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow. 3 Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled. Data Sheet 76 V1.1, 2012-12 SAL-XC866 Functional Description 3.16 Timer 2 Timer 2 is a 16-bit general purpose timer (THL2) that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as long as it is enabled. Table 28 Timer 2 Modes Mode Description Auto-reload Up/Down Count Disabled • Count up only • Start counting from 16-bit reload value, overflow at FFFFH • Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well • Programmble reload value in register RC2 • Interrupt is generated with reload event Up/Down Count Enabled • Count up or down, direction determined by level at input pin T2EX • No interrupt is generated • Count up – Start counting from 16-bit reload value, overflow at FFFFH – Reload event triggered by overflow condition – Programmble reload value in register RC2 • Count down – Start counting from FFFFH, underflow at value defined in register RC2 – Reload event triggered by underflow condition – Reload value fixed at FFFFH Channel capture Data Sheet • • • • • • • Count up only Start counting from 0000H, overflow at FFFFH Reload event triggered by overflow condition Reload value fixed at 0000H Capture event triggered by falling/rising edge at pin T2EX Captured timer value stored in register RC2 Interrupt is generated with reload or capture event 77 V1.1, 2012-12 SAL-XC866 Functional Description 3.17 Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. Timer T12 Features: • Three capture/compare channels, each channel can be used either as a capture or as a compare channel • Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches) • 16-bit resolution, maximum count frequency = peripheral clock frequency • Dead-time control for each channel to avoid short-circuits in the power stage • Concurrent update of the required T12/13 registers • Generation of center-aligned and edge-aligned PWM • Supports single-shot mode • Supports many interrupt request sources • Hysteresis-like control mode Timer T13 Features: • • • • • One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock frequency Can be synchronized to T12 Interrupt generation at period-match and compare-match Supports single-shot mode Additional Features: • • • • • • • Implements block commutation for Brushless DC-drives Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage Data Sheet 78 V1.1, 2012-12 SAL-XC866 Functional Description The block diagram of the CCU6 module is shown in Figure 31. module kernel channel 1 1 channel 2 1 deadtime control compare channel 3 compare capture T13 compare start multichannel control trap control trap input clock control 1 output select T12 channel 0 Hall input address decoder output select compare compare interrupt control 1 2 3 2 2 3 1 CTRAP CCPOS2 CCPOS1 CCPOS0 CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 T13HR T12HR input / output control port control CCU6_block_diagram Figure 31 Data Sheet CCU6 Block Diagram 79 V1.1, 2012-12 SAL-XC866 Functional Description 3.18 Analog-to-Digital Converter The SAL-XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. Features: • • • • • • • • • • • • • • • • • • Successive approximation 8-bit or 10-bit resolution Eight analog channels Four independent result registers Result data protection for slow CPU access (wait-for-read mode) Single conversion mode Autoscan functionality Limit checking for conversion results Data reduction filter (accumulation of up to 2 conversion results) Two independent conversion request sources with programmable priority Selectable conversion request trigger Flexible interrupt generation with configurable service nodes Programmable sample time Programmable clock divider Cancel/restart feature for running conversions Integrated sample and hold circuitry Compensation of offset errors Low power modes Data Sheet 80 V1.1, 2012-12 SAL-XC866 Functional Description 3.18.1 ADC Clocking Scheme A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module: • fADCA is input clock for the analog part. • fADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components. • fADCD is input clock for the digital part. The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. fADCD fADC = fPCLK arbiter registers interrupts digital part fADCA CTC ÷ 32 f ADCI ÷4 MUX ÷3 ÷2 clock prescaler analog components analog part Condition: f ADCI ≤ 10 MHz, where t ADCI = Figure 32 Data Sheet 1 fADCI ADC Clocking Scheme 81 V1.1, 2012-12 SAL-XC866 Functional Description For module clock fADC = 25 MHz, the analog clock fADCI frequency can be selected as shown in Table 29. Table 29 fADCI Frequency Selection Module Clock fADC CTC Prescaling Ratio Analog Clock fADCI 25 MHz 00B ÷2 12.5 MHz (N.A) 01B ÷3 8.3 MHz 10B ÷4 6.3 MHz 11B (default) ÷ 32 781.3 kHz As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is 25 MHz. During slow-down mode where fADC may be reduced to 12.5 MHz, 6.25 MHz etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed 10 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode. 3.18.2 ADC Conversion Sequence The analog-to-digital conversion procedure consists of the following phases: • • • • Synchronization phase (tSYN) Sample phase (tS) Conversion phase Write result phase (tWR) conversion start trigger Source interrupt Sample Phase Channel interrupt Result interrupt Conversion Phase fADCI BUSY Bit SAMPLE Bit tSYN tS Write Result Phase tCONV Figure 33 Data Sheet tWR ADC Conversion Timing 82 V1.1, 2012-12 SAL-XC866 Functional Description 3.19 On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • • • • use the built-in debug functionality of the XC800 Core add a minimum of hardware overhead provide support for most of the operations by a Monitor Program use standard interfaces to communicate with the Host (a Debugger) Features: • • • • • Set breakpoints on instruction address and within a specified address range Set breakpoints on internal RAM address Support unlimited software breakpoints in Flash/RAM code region Process external breaks Step through the program code The OCDS functional blocks are shown in Figure 34. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after SALXC866 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system. Data Sheet 83 V1.1, 2012-12 SAL-XC866 Functional Description Memory Control Unit JTAG Module Primary Debug Interface TMS TCK TDI TDO JTAG TCK TDI TDO Control Reset Monitor & Bootstrap loader Control line User Program Memory Boot/ Monitor ROM User Internal RAM Monitor RAM Monitor Mode Control MBC WDT Suspend System Control Unit Reset Clock - parts of OCDS Reset Clock Debug PROG PROG Memory Interface & IRAM Data Control Addresses XC800 OCDS_XC800-Block_Diagram-UM-v0.2 Figure 34 3.19.1 OCDS Block Diagram JTAG ID Register This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the SAL-XC866 devices are given in Table 30. Table 30 Device Type Flash Data Sheet JTAG ID Summary Device Name JTAG ID SAL-XC866L-4FRA 1010 0083H SAL-XC866L-2FRA 1010 2083H 84 V1.1, 2012-12 SAL-XC866 Functional Description 3.20 Identification Register The SAL-XC866 identity register is located at Page 1 of address B3H. ID Identity Register 7 Reset Value: 0000 0010B 6 5 4 3 1 PRODID VERID r r Field Bits Type Description VERID [2:0] r Version ID 010B PRODID [7:3] r Product ID 00000B Data Sheet 2 85 0 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4 Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the SAL-XC866. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 and Section 4.3. 4.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the SALXC866 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column: • CC These parameters indicate Controller Characteristics, which are distinctive features of the SAL-XC866 and must be regarded for a system design. • SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the SAL-XC866 is designed in. Data Sheet 86 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.1.2 Absolute Maximum Rating Maximum ratings are the extreme limits to which the SAL-XC866 can be subjected to without permanent damage. Table 31 Absolute Maximum Rating Parameters Parameter Symbol TA Storage temperature TST Junction temperature TJ Voltage on power supply pin with VDDP respect to VSS Voltage on any pin with respect VIN to VSS Ambient temperature Input current on any pin during overload condition IIN Absolute sum of all input currents Σ|IIN| during overload condition 1) Limit Values Unit Notes min. max. -40 150 °C under bias -65 150 °C 1) -40 160 °C under bias1) -0.5 6 V 1) -0.5 VDDP + V Whichever is lower1) 0.5 or max. 6 -10 10 mA 1) – 50 mA 1) Not subjected to production test, verified by design/characterization. Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 87 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.1.3 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the SAL-XC866. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 32 Operating Condition Parameters Parameter Symbol Digital power supply voltage Digital power supply voltage Digital ground voltage Digital core supply voltage System Clock Frequency1) Ambient temperature 1) VDDP VDDP VSS VDDC fSYS TA min. Limit Values max. Unit Notes/ Conditions 4.5 5.5 V 5V Device 3.6 V 3.3V Device 3.0 0 2.3 V 2.7 V 69 81 MHz -40 150 °C SAL-XC866... fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 3. Please refer to Figure 24 for detailed description. Data Sheet 88 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.2 DC Parameters 4.2.1 Input/Output Characteristics Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. – 1.0 V – 0.4 V VDDP = 5V Range Output low voltage Output high voltage VOL CC VOH CC V IOL = 15 mA IOL = 5 mA IOH = -15 mA V IOH = -5 mA V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode – V CMOS Mode VDDP V CMOS Mode – V CMOS Mode 0.75 × – V CMOS Mode V CMOS Mode VDDP - – 1.0 VDDP - – 0.4 Input low voltage on VILP SR port pins (all except P0.0 & P0.1) Input low voltage on P0.0 & P0.1 VILP0 SR Input low voltage on RESET pin VILR SR Input low voltage on TMS pin VILT SR VDDP 0.3 × -0.2 VDDP 0.3 × – VDDP 0.3 × – VDDP Input high voltage on VIHP SR port pins (all except P0.0 & P0.1) Input high voltage on P0.0 & P0.1 VIHP0 SR Input high voltage on RESET pin VIHR SR Input high voltage on TMS pin VIHT SR Input Hysteresis1) on Port Pins HYS CC Input Hysteresis1) on XTAL1 HYSX CC Data Sheet 0.3 × – 0.7 × VDDP 0.7 × VDDP 0.7 × VDDP VDDP 0.08 × – VDDP 0.07 × – V VDDC 89 V1.1, 2012-12 SAL-XC866 Electrical Parameters Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values min. Input low voltage at XTAL1 VILX SR Input high voltage at XTAL1 VIHX SR Pull-up current IPU Pull-down current IPD SR VSS - 0.3 × V 0.5 0.7 × VDDC VDDC V VDDC + 0.5 – -10 µA -150 – µA VIH,min VIL,max VIL,max VIH,min 0 < VIN < VDDP, – 10 µA 150 – µA -2 2 µA -10 10 µA 5 mA 3) – 25 mA 3) SR – 0.3 V 4) SR – 15 mA Maximum current for all Σ|IM| – SR pins (excluding VDDP and VSS) 60 mA – 80 mA 3) – 80 mA 3) Input leakage current2) SR Unit Test Conditions max. IOZ1 CC IILX Overload current on any IOV Input current at XTAL1 CC TA ≤ 150°C SR -5 pin Absolute sum of overload currents Σ|IOV| Voltage on any pin during VDDP power off VPO SR Maximum current per IM pin (excluding VDDP and VSS) Maximum current into IMVDDP VDDP SR Maximum current out of IMVSS VSS Data Sheet SR 90 V1.1, 2012-12 SAL-XC866 Electrical Parameters Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. – 1.0 V – 0.4 V VDDP = 3.3V Range Output low voltage Output high voltage VOL CC VOH CC V IOL = 8 mA IOL = 2.5 mA IOH = -8 mA V IOH = -2.5 mA V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode – V CMOS Mode VDDP V CMOS Mode – V CMOS Mode 0.75 × – V CMOS Mode V CMOS Mode VDDP - – 1.0 VDDP - – 0.4 Input low voltage on VILP SR port pins (all except P0.0 & P0.1) Input low voltage on P0.0 & P0.1 VILP0 SR Input low voltage on RESET pin VILR SR Input low voltage on TMS pin VILT SR VDDP 0.3 × -0.2 VDDP 0.3 × – VDDP 0.3 × – VDDP Input high voltage on VIHP SR port pins (all except P0.0 & P0.1) Input high voltage on P0.0 & P0.1 VIHP0 SR Input high voltage on RESET pin VIHR SR Input high voltage on TMS pin VIHT SR Input Hysteresis1) on Port Pins HYS CC Input Hysteresis1) on XTAL1 HYSX CC Input low voltage at XTAL1 VILX SR Input high voltage at XTAL1 VIHX SR Data Sheet 0.3 × – 0.7 × VDDP 0.7 × VDDP 0.7 × VDDP VDDP 0.03 × – VDDP 0.07 × – VDDC VSS - 0.3 × VDDC 0.5 0.7 × VDDC VDDC + 0.5 91 V V V V1.1, 2012-12 SAL-XC866 Electrical Parameters Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter Pull-up current Symbol IPU SR Limit Values Unit Test Conditions min. max. – -5 µA -50 – µA – 5 µA Pull-down current IPD 50 – µA Input leakage current2) IOZ1 CC -2 2 µA IILX - 10 Input current at XTAL1 SR TA ≤ 150°C 10 µA 5 mA 3) – 25 mA 3) SR – 0.3 V 4) SR – 15 mA – Maximum current for all Σ|IM| SR pins (excluding VDDP and VSS) 60 mA – 80 mA – 80 mA Overload current on any IOV pin Absolute sum of overload currents Σ|IOV| Voltage on any pin during VDDP power off VPO SR -5 SR Maximum current per IM pin (excluding VDDP and VSS) Maximum current into CC VIH,min VIL,max VIL,max VIH,min 0 < VIN < VDDP, IMVDDP VDDP SR Maximum current out of IMVSS VSS SR 1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 2) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. 3) Not subjected to production test, verified by design/characterization. 4) Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Data Sheet 92 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.2.2 Supply Threshold Characteristics 5.0V VDDPPW VDDP 2.5V VDDCPW VDDCBO VDDC VDDCRDR VDDCBOPD VDDCPOR Figure 35 Supply Threshold Parameters Table 34 Supply Threshold Parameters (Operating Conditions apply) Parameters Symbol Limit Values min. typ. max. Unit VDDC prewarning voltage1) VDDCPW CC 2.2 2.3 2.4 V VDDC brownout voltage in active mode1) VDDCBO CC 2.0 2.1 2.2 V RAM data retention voltage VDDCRDR CC 0.9 1.0 1.1 V VDDC brownout voltage in power-down mode2) VDDCBOPD CC 1.3 1.5 1.7 V VDDP prewarning voltage3) VDDPPW CC 3.3 4.0 4.65 V Power-on reset voltage2)4) VDDCPOR CC 1.3 1.5 1.7 V 1) Detection is disabled in power-down mode. 2) Detection is enabled in both active and power-down mode. 3) Detection is enabled for external power supply of 5.0V Detection must be disabled for external power supply of 3.3V. 4) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage. Data Sheet 93 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.2.3 ADC Characteristics The values in the table below are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case, the analog parameters may show a reduced performance. All ground pins (VSS) must be externally connected to one single star point in the system. The voltage difference between the ground pins must not exceed 200mV. Table 35 ADC Characteristics (Operating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values min. typ . Unit max. Test Conditions/ Remarks VDDP V + 0.05 1) VAREF V -1 1) Analog reference voltage VAREF Analog reference ground VAGND VSS SR - 0.05 Analog input voltage range VAIN SR VAGND – VAREF V ADC clocks fADC – 20 40 MHz module clock1) fADCI – – 10 MHz internal analog clock1) See Figure 32 VAGND VDDP SR + 1 VSS Sample time tS CC (2 + INPCR0.STC) × tADCI µs 1) Conversion time tC CC See Section 4.2.3.1 µs 1) Total unadjusted error TUE CC – – 1 LSB 8-bit conversion.2) – – 2 LSB 10-bit conversion.2) Differential Nonlinearity |EADNL| – CC 1 – LSB 10-bit conversion1) Integral Nonlinearity |EAINL| – CC 1 – LSB 10-bit conversion1) Offset |EAOFF| – CC 1 – LSB 10-bit conversion1) Gain |EAGAIN| – CC 1 – LSB 10-bit conversion1) Overload current coupling factor for analog inputs KOVA CC – – 1.0 x 10-4 – IOV > 01)3) – – 1.5 x 10-3 – IOV < 01)3) Data Sheet 94 V1.1, 2012-12 SAL-XC866 Electrical Parameters Table 35 ADC Characteristics (Operating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarks typ . max. Overload current coupling factor for digital I/O pins KOVD CC – – 5.0 x 10-3 – IOV > 01)3) – – 1.0 x 10-2 – IOV < 01)3) Switched capacitance at the reference voltage input CAREFSW – CC 10 20 pF 1)4) Switched capacitance at the analog voltage inputs – CAINSW CC 5 7 pF 1)5) Input resistance of RAREFCC – the reference input 1 2 kΩ 1) Input resistance of RAIN CC – the selected analog channel 1 1.5 kΩ 1) min. 1) Not subject to production test, verified by design/characterization. 2) TUE is tested at VAREF = 5.0 V, VAGND = 0 V , VDDP = 5.0 V. 3) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ1| + (|IOV| × KOV). The additional error current may distort the input voltage on analog inputs. 4) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 5) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Data Sheet 95 V1.1, 2012-12 SAL-XC866 Electrical Parameters Analog Input Circuitry REXT VAIN RAIN, On ANx CEXT C AINSW VAGNDx Reference Voltage Input Circuitry R AREF, On VAREFx VAREF C AREFSW VAGNDx Figure 36 4.2.3.1 ADC Input Circuits ADC Conversion Timing Conversion time, tC = tADC × ( 1 + r × (3 + n + STC) ) , where r = CTC + 2 for CTC = 00B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC = 1 / fADC Data Sheet 96 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.2.4 Power Supply Current Table 36 Power Supply Current Parameters (Operating Conditions apply) Parameter Symbol Limit Values typ.1) Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled Unit Test Condition max.2) IDDP IDDP IDDP 22.6 25.1 mA 3) 17.2 19.7 mA 4) 7.2 9.3 mA 5) IDDP 7.1 8 mA 6) 1) The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 5.0 V. 2) The maximum IDDP values are measured under worst case conditions (TA = + 150 °C and VDDP = 5.5 V). 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 25 MHz(set by on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0001B), RESET = VDDP. 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 25 MHz, RESET = VDDP. 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 781 KHz by setting CLKREL in CMCON to 0101B, RESET = VDDP. 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 781 MHz by setting CLKREL in CMCON to 0101B, RESET = VDDP. Data Sheet 97 V1.1, 2012-12 SAL-XC866 Electrical Parameters Table 37 Power Down Current (Operating Conditions apply) Parameter Symbol Limit Values typ.1) Power-Down Mode3) IPDP Unit Test Condition max.2) 1 10 µA TA = + 25 °C.4) - 30 µA TA = + 85 °C.4)5) 1) The typical IPDP values are measured at VDDP = 5.0 V. 2) The maximum IPDP values are measured at VDDP = 5.5 V. 3) IPDP (power-down mode) has a maximum value of 500 µA at TA = + 150 °C. 4) IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 5) Not subject to production test, verified by design/characterization. Data Sheet 98 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.3 AC Parameters 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 37, Figure 38 and Figure 39. VDDP 90% 90% 10% 10% VSS tF tR Figure 37 Rise/Fall Time Parameters VDDP VDDE / 2 Test Points VDDE / 2 VSS Figure 38 Testing Waveform, Output Delay VLoad + 0.1 V VLoad - 0.1 V Figure 39 Data Sheet Timing Reference Points VOH - 0.1 V VOL - 0.1 V Testing Waveform, Output High Impedance 99 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.3.2 Output Rise/Fall Times Table 38 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. VDDP = 5V Range Rise/fall times 1) 2) tR, tF – 10 ns 20 pF. 3) tR, tF – 10 ns 20 pF. 4) VDDP = 3.3V Range Rise/fall times 1) 2) 1) Rise/Fall time measurements are taken with 10% - 90% of the pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. 4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF. VDDP 90% 90% VSS 10% 10% tF tR Figure 40 Data Sheet Rise/Fall Times Parameters 100 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.3.3 Power-on Reset and PLL Timing Table 39 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Symbol Limit Values min. typ. Unit Test Conditions max. – – V 1) – 500 ns 1) Flash initialization time tFINIT CC – 160 – µs 1) tRST SR – 500 – µs VDDP rise time tLOCK CC – – 200 µs 1) – 0.7 ns 1) Pad operating voltage On-Chip Oscillator start-up time RESET hold time PLL lock-in in time VPAD CC 2.3 – tOSCST CC PLL accumulated jitter DP (10% – 90%) ≤ 500µs1)2) – 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 2) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V). VDDP VPAD VDDC tOSCST OSC PLL unlock PLL PLL lock tLOCK Flash State Reset Initialization tFINIT tRST Ready to Read RESET Pads 3) 2) 1) 1)Pad state undefined I)until EVR is stable Figure 41 Data Sheet 2)ENPS control 3)As Programmed II)until PLL is locked III) until Flash go IV) CPU reset is released; Boot to Ready-to-Read ROM software begin execution Power-on Reset Timing 101 V1.1, 2012-12 SAL-XC866 Electrical Parameters 4.3.4 Table 40 On-Chip Oscillator Characteristics On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Nominal frequency fNOM CC 9.75 10 Long term frequency ΔfLT CC 0 deviation 10.25 MHz under nominal conditions1) – 6.0 % with respect to fNOM, over lifetime and temperature (125°C to 150°C), for one device after trimming -5.0 – 5.0 % with respect to fNOM, over lifetime and temperature (−10°C to 125°C), for one device after trimming -6.0 – 0 % with respect to fNOM, over lifetime and temperature (−40°C to -10°C), for one device after trimming Short term frequency ΔfST CC -1.0 deviation – 1.0 % within one LIN message (