XMC1302Q024X0064ABXUMA1

XMC1300 AB-Step Microcontroller Series for Industrial Applications XMC1000 Family ARM® Cortex®-M0 32-bit processor core Data Sheet V2.0 2017-10 Microcontrollers Edition 2017-10 Published by Infineon Technologies AG 81726 Munich, Germany © 2017 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. XMC1300 AB-Step Microcontroller Series for Industrial Applications XMC1000 Family ARM® Cortex®-M0 32-bit processor core Data Sheet V2.0 2017-10 Microcontrollers XMC1300 AB-Step XMC1000 Family XMC1300 Data Sheet Revision History: V2.0 2017-10 Previous Version: V1.9 2017-03 Page Subjects Page 10, Page 13 Add marking option for XMC1302-T28X0032, XMC1302-T28X0064, XMC1302-T28X0128, XMC1302-T28X0200. Trademarks C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG. ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited. Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are trademarks of ARM, Limited. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Table of Contents Table of Contents 1 1.1 1.2 1.3 1.4 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 2.1 2.2 2.2.1 2.2.2 2.2.3 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 16 16 18 22 25 27 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . . On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 34 35 37 38 38 42 46 48 49 50 55 56 56 57 59 61 62 63 63 66 68 4 4.1 4.1.1 4.2 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 70 70 72 Data Sheet 5 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Table of Contents 5 Data Sheet Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family About this Document About this Document This Data Sheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC1300 series devices. The document describes the characteristics of a superset of the XMC1300 series devices. For simplicity, the various device types are referred to by the collective term XMC1300 throughout this document. XMC1000 Family User Documentation The set of user documentation includes: • • • Reference Manual – decribes the functionality of the superset of devices. Data Sheets – list the complete ordering designations, available features and electrical characteristics of derivative devices. Errata Sheets – list deviations from the specifications given in the related Reference Manual or Data Sheets. Errata Sheets are provided for the superset of devices. Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions of those documents. Data Sheet 7 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features 1 Summary of Features The XMC1300 devices are members of the XMC1000 Family of microcontrollers based on the ARM Cortex-M0 processor core. The XMC1300 series addresses the real-time control needs of motor control, digital power conversion. It also features peripherals for LED Lighting applications. Cortex-M0 CPU Analog system EVR 2 x DCO Debug system NVIC SWD SPD ANACTRL SFRs PRNG 16-bit APB Bus Temperature sensor AHB to APB Bridge PAU AHB-Lite Bus Flash SFRs 200k + 0.5k1) Flash MATH CCU40 ACMP & ORC 16k SRAM PORTS USIC0 BCCU0 8k ROM WDT VADC CCU80 Memories SCU ERU0 POSIF0 RTC 1) 0.5kbytes of sector 0 (readable only). Figure 1 System Block Diagram CPU Subsystem • CPU Core – High-performance 32-bit ARM Cortex-M0 CPU – Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set – Single cycle 32-bit hardware multiplier – System timer (SysTick) for Operating System support Data Sheet 8 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features • • • – Ultra low power consumption Nested Vectored Interrupt Controller (NVIC) Event Request Unit (ERU) for processing of external and internal service requests MATH Co-processor (MATH) – CORDIC unit for trigonometric calculation – division unit On-Chip Memories • • • 8 kbytes on-chip ROM 16 kbytes on-chip high-speed SRAM up to 200 kbytes on-chip Flash program and data memory Communication Peripherals • Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces Analog Frontend Peripherals • • • • A/D Converters – up to 12 analog input pins – 2 sample and hold stages with 8 analog input channels each – fast 12-bit analog to digital converter with adjustable gain Up to 8 channels of out of range comparators (ORC) Up to 3 fast analog comparators (ACMP) Temperature Sensor (TSE) Industrial Control Peripherals • • • • Capture/Compare Units 4 (CCU4) as general purpose timers Capture/Compare Units 8 (CCU8) for motor control and power conversion Position Interfaces (POSIF) for hall and quadrature encoders and motor positioning Brightness and Colour Control Unit (BCCU), for LED color and dimming application System Control • • • • Window Watchdog Timer (WDT) for safety sensitive applications Real Time Clock module with alarm support (RTC) System Control Unit (SCU) for system configuration and control Pseudo random number generator (PRNG) for fast random data generation Input/Output Lines • • Tri-stated in input mode Push/pull or open drain output mode Data Sheet 9 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features • Configurable pad hysteresis On-Chip Debug Support • • Support for debug features: 4 breakpoints, 2 watchpoints Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD) 1.1 Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC1-” identifies: • • • • • the derivatives function set the package variant – T: TSSOP – Q: VQFN package pin count the temperature range: – F: -40°C to 85°C – X: -40°C to 105°C the Flash memory size. For ordering codes for the XMC1300 please contact your sales representative or local distributor. This document describes several derivatives of the XMC1300 series, some descriptions may not apply to a specific product. Please see Table 1. For simplicity the term XMC1300 is used for all derivatives throughout this document. 1.2 Device Types These device types are available and can be ordered through Infineon’s direct and/or distribution channels. Table 1 Synopsis of XMC1300 Device Types Derivative Package Flash Kbytes SRAM Kbytes XMC1301-T016F0008 PG-TSSOP-16-8 8 16 XMC1301-T016F0016 PG-TSSOP-16-8 16 16 XMC1301-T016F0032 PG-TSSOP-16-8 32 16 XMC1301-T016X0008 PG-TSSOP-16-8 8 16 XMC1301-T016X0016 PG-TSSOP-16-8 16 16 XMC1302-T016X0008 PG-TSSOP-16-8 8 16 Data Sheet 10 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features Table 1 Synopsis of XMC1300 Device Types (cont’d) Derivative Package Flash Kbytes SRAM Kbytes XMC1302-T016X0016 PG-TSSOP-16-8 16 16 XMC1302-T016X0032 PG-TSSOP-16-8 32 16 XMC1302-T028X0016 PG-TSSOP-28-8 16 16 XMC1302-T028X0032 PG-TSSOP-28-8 32 16 XMC1302-T028X0064 PG-TSSOP-28-8 64 16 XMC1302-T028X0128 PG-TSSOP-28-8 128 16 XMC1302-T028X0200 PG-TSSOP-28-8 200 16 XMC1301-T038F0008 PG-TSSOP-38-9 8 16 XMC1301-T038F0016 PG-TSSOP-38-9 16 16 XMC1301-T038F0032 PG-TSSOP-38-9 32 16 XMC1301-T038X0032 PG-TSSOP-38-9 32 16 XMC1301-T038F0064 PG-TSSOP-38-9 64 16 XMC1302-T038X0016 PG-TSSOP-38-9 16 16 XMC1302-T038X0032 PG-TSSOP-38-9 32 16 XMC1302-T038X0064 PG-TSSOP-38-9 64 16 XMC1302-T038X0128 PG-TSSOP-38-9 128 16 XMC1302-T038X0200 PG-TSSOP-38-9 200 16 XMC1301-Q024F0008 PG-VQFN-24-19 8 16 XMC1301-Q024F0016 PG-VQFN-24-19 16 16 XMC1302-Q024F0016 PG-VQFN-24-19 16 16 XMC1302-Q024F0032 PG-VQFN-24-19 32 16 XMC1302-Q024F0064 PG-VQFN-24-19 64 16 XMC1302-Q024X0016 PG-VQFN-24-19 16 16 XMC1302-Q024X0032 PG-VQFN-24-19 32 16 XMC1302-Q024X0064 PG-VQFN-24-19 64 16 XMC1301-Q040F0008 PG-VQFN-40-13 8 16 XMC1301-Q040F0016 PG-VQFN-40-13 16 16 XMC1301-Q040F0032 PG-VQFN-40-13 32 16 XMC1302-Q040X0016 PG-VQFN-40-13 16 16 XMC1302-Q040X0032 PG-VQFN-40-13 32 16 Data Sheet 11 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features Table 1 Synopsis of XMC1300 Device Types (cont’d) Derivative Package Flash Kbytes SRAM Kbytes XMC1302-Q040X0064 PG-VQFN-40-13 64 16 XMC1302-Q040X0128 PG-VQFN-40-13 128 16 XMC1302-Q040X0200 PG-VQFN-40-13 200 16 1.3 Device Type Features The following table lists the available features per device type. Table 2 Features of XMC1300 Device Types1) Derivative ADC channel ACMP BCCU MATH XMC1301-T016 11 2 - - XMC1302-T016 11 2 1 1 XMC1302-T028 14 3 1 1 XMC1301-T038 16 3 - - XMC1302-T038 16 3 1 1 XMC1301-Q024 13 3 - - XMC1302-Q024 13 3 1 1 XMC1301-Q040 16 3 - - XMC1302-Q040 16 3 1 1 1) Features that are not included in this table are available in all the derivatives Table 3 ADC Channels 1) Package VADC0 G0 VADC0 G1 PG-TSSOP-16 CH0..CH5 CH0..CH4 PG-TSSOP-28 CH0..CH7 CH0 .. CH4, CH7 PG-TSSOP-38 CH0..CH7 CH0..CH7 PG-VQFN-24 CH0..CH7 CH0..CH4 PG-VQFN-40 CH0..CH7 CH0..CH7 1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table. Data Sheet 12 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features 1.4 Chip Identification Number The Chip Identification Number allows software to identify the marking. It is a 8 words value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and most significant word of the Chip Identification Number are the value of registers DBGROMID and IDCHIP, respectively. Table 4 XMC1300 Chip Identification Number Derivative Value Marking XMC1301-T016F0008 00013032 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H AB XMC1301-T016F0016 00013032 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H AB XMC1301-T016F0032 00013032 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H AB XMC1301-T016X0008 00013033 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H AB XMC1301-T016X0016 00013033 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H AB XMC1302-T016X0008 00013033 01FF00FF 00001FF7 0000900F 00000C00 00001000 00003000 201ED083H AB XMC1302-T016X0016 00013033 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H AB XMC1302-T016X0032 00013033 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H AB XMC1302-T028X0016 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H AB XMC1302-T028X0032 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H AB XMC1302-T028X0064 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H AB XMC1302-T028X0128 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00021000 201ED083H AB XMC1302-T028X0200 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00033000 201ED083H AB XMC1301-T038F0008 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H AB Data Sheet 13 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features Table 4 XMC1300 Chip Identification Number (cont’d) Derivative Value Marking XMC1301-T038F0016 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H AB XMC1301-T038F0032 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H AB XMC1301-T038X0032 00013013 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H AB XMC1301-T038F0064 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00011000 201ED083H AB XMC1302-T038X0016 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H AB XMC1302-T038X0032 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H AB XMC1302-T038X0064 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H AB XMC1302-T038X0128 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00021000 201ED083H AB XMC1302-T038X0200 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00033000 201ED083H AB XMC1301-Q024F0008 00013062 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H AB XMC1301-Q024F0016 00013062 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H AB XMC1302-Q024F0016 00013062 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H AB XMC1302-Q024F0032 00013062 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H AB XMC1302-Q024F0064 00013062 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H AB XMC1302-Q024X0016 00013063 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H AB XMC1302-Q024X0032 00013063 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H AB XMC1302-Q024X0064 00013063 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H AB Data Sheet 14 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Summary of Features Table 4 XMC1300 Chip Identification Number (cont’d) Derivative Value Marking XMC1301-Q040F0008 00013042 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H AB XMC1301-Q040F0016 00013042 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H AB XMC1301-Q040F0032 00013042 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H AB XMC1302-Q040X0016 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H AB XMC1302-Q040X0032 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H AB XMC1302-Q040X0064 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H AB XMC1302-Q040X0128 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00021000 201ED083H AB XMC1302-Q040X0200 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00033000 201ED083H AB Data Sheet 15 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information 2 General Device Information This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping. 2.1 Logic Symbols VDDP VSSP VDDP VSSP (2) (2) (1) (1) Port 0 16 bit XMC13XX TSSOP-38 Port 0 12 bit Port 1 6 bit XMC13XX Port 2 4 bit TSSOP -28 Port 2 8 bit Port 1 4 bit Port 2 4 bit Port 2 6 bit VDDP VSSP (1) (1) Port 0 8 bit XMC13XX Port 2 3 bit TSSOP-16 Port 2 3 bit Figure 2 Data Sheet XMC1300 Logic Symbol for TSSOP-38, TSSOP-28 and TSSOP-16 16 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information V DD VSS V DDP VSSP (1) (1) (2) (1) VDDP VSSP (1) (1) Port 0 10 bit Port 0 16 bit XMC1300 VQFN-40 Port 1 7 bit XMC1300 VQFN-24 Port 2 4 bit Data Sheet Port 2 4 bit Port 2 4 bit Port 2 8 bit Figure 3 Port 1 4 bit XMC1300 Logic Symbol for VQFN-24 and VQFN-40 17 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information 2.2 Pin Configuration and Definition The following figures summarize all pins, showing their locations on the different packages. P2.4 1 38 P2.3 Top View Figure 4 Data Sheet P2.5 2 37 P2.2 P2.6 3 36 P2.1 P2.7 4 35 P2.0 P2.8 5 34 P0.15 P2.9 6 33 P0.14 P2.10 7 32 P0.13 P2.11 8 31 P0.12 VSSP /VSS 9 30 P0.11 VDDP/VDD 10 29 P0.10 P1.5 11 28 P0.9 P1.4 12 27 P0.8 P1.3 13 26 VDDP P1.2 14 25 VSSP P1.1 15 24 P0.7 P1.0 16 23 P0.6 P0.0 17 22 P0.5 P0.1 18 21 P0.4 P0.2 19 20 P0.3 XMC1300 PG-TSSOP-38 Pin Configuration (top view) 18 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information P2.6 1 28 P2.5 Top View Figure 5 P2.7 2 27 P2.2 P2.8 3 26 P2.1 P2.9 4 25 P2.0 P2.10 5 24 P0.15 P2.11 6 23 P0.14 VSSP /VSS 7 22 P0.13 VDDP/VDD 8 21 P0.12 P1.3 9 20 P0.10 P1.2 10 19 P0.9 P1.1 11 18 P0.8 P1.0 12 17 P0.7 P0.0 13 16 P0.6 P0.4 14 15 P0.5 XMC1300 PG-TSSOP-28 Pin Configuration (top view) P2.7/P2.8 1 16 P2.6 Top View Figure 6 Data Sheet P2.9 2 15 P2.0 P2.10 3 14 P0.15 P2.11 4 13 P0.14 VSSP/VSS 5 12 P0.9 VDDP/VDD 6 11 P0.8 P0.0 7 10 P0.7 P0.5 8 9 P0.6 XMC1300 PG-TSSOP-16 Pin Configuration (top view) 19 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family P1.1 P1.0 P0.0 P0.5 P0.6 P0.7 General Device Information 18 17 16 15 14 13 12 P1.2 P0.9 20 11 P1.3 P0.12 21 10 VDDP /V DD P0.13 22 9 VSSP /V SS P0.14 23 8 P2.11 P0.15 24 7 P2.10 P2.2 4 5 6 P2.9 3 P2.7/P2.8 2 P2.6 1 P2.1 Data Sheet 19 P2.0 Figure 7 P0.8 XMC1300 PG-VQFN-24 Pin Configuration (top view) 20 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family P1.1 P1.0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 General Device Information 30 29 28 27 26 25 24 23 22 21 V SSP 31 20 P1.2 VDDP 32 19 P1.3 P0.8 33 18 P1.4 P0.9 34 17 P1.5 P0.10 35 16 P1.6 P0.11 36 15 VDDP P0.12 37 14 V DD P0.13 38 13 V SS P0.14 39 12 P2.11 P0.15 40 11 P2.10 6 7 8 9 10 P2.5 P2.6 P2.7 P2.8 P2.9 P2.4 P2.2 4 5 P2.3 3 P2.1 Data Sheet 2 P2.0 Figure 8 1 XMC1300 PG-VQFN-40 Pin Configuration (top view) 21 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information 2.2.1 Package Pin Summary The following general building block is used to describe each pin: Table 5 Package Pin Mapping Description Function Package A Package B Px.y N N ... Pad Type Pad Class The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the supply pins. The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package. The “Pad Type” indicates the employed pad type: • • • • • STD_INOUT(standard bi-directional pads) STD_INOUT/AN (standard bi-directional pads with analog input) High Current (high current bi-directional pads) STD_IN/AN (standard input pads with analog input) Power (power supply) Details about the pad properties are defined in the Electrical Parameters. Table 6 Package Pin Mapping Function VQFN 40 TSSOP TSSOP VQFN 38 28 24 TSSOP Pad 16 Type P0.0 23 17 13 15 7 STD_IN OUT P0.1 24 18 - - - STD_IN OUT P0.2 25 19 - - - STD_IN OUT P0.3 26 20 - - - STD_IN OUT P0.4 27 21 14 - - STD_IN OUT P0.5 28 22 15 16 8 STD_IN OUT P0.6 29 23 16 17 9 STD_IN OUT Data Sheet 22 Notes V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information Table 6 Package Pin Mapping (cont’d) Function VQFN 40 TSSOP TSSOP VQFN 38 28 24 TSSOP Pad 16 Type P0.7 30 24 17 18 10 STD_IN OUT P0.8 33 27 18 19 11 STD_IN OUT P0.9 34 28 19 20 12 STD_IN OUT P0.10 35 29 20 - - STD_IN OUT P0.11 36 30 - - - STD_IN OUT P0.12 37 31 21 21 - STD_IN OUT P0.13 38 32 22 22 - STD_IN OUT P0.14 39 33 23 23 13 STD_IN OUT P0.15 40 34 24 24 14 STD_IN OUT P1.0 22 16 12 14 - High Current P1.1 21 15 11 13 - High Current P1.2 20 14 10 12 - High Current P1.3 19 13 9 11 - High Current P1.4 18 12 - - - High Current P1.5 17 11 - - - High Current P1.6 16 - - - - STD_IN OUT P2.0 1 35 25 1 15 STD_IN OUT/AN Data Sheet 23 Notes V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information Table 6 Package Pin Mapping (cont’d) Function VQFN 40 TSSOP TSSOP VQFN 38 28 24 TSSOP Pad 16 Type P2.1 2 36 26 2 - STD_IN OUT/AN P2.2 3 37 27 3 - STD_IN/ AN P2.3 4 38 - - - STD_IN/ AN P2.4 5 1 - - - STD_IN/ AN P2.5 6 2 28 - - STD_IN/ AN P2.6 7 3 1 4 16 STD_IN/ AN P2.7 8 4 2 5 1 STD_IN/ AN P2.8 9 5 3 5 1 STD_IN/ AN P2.9 10 6 4 6 2 STD_IN/ AN P2.10 11 7 5 7 3 STD_IN OUT/AN P2.11 12 8 6 8 4 STD_IN OUT/AN VSS 13 9 7 9 5 Power Supply GND, ADC reference GND VDD 14 10 8 10 6 Power Supply VDD, ADC reference voltage/ ORC reference voltage VDDP 15 10 8 10 6 Power When VDD is supplied, VDDP has to be supplied with the same voltage. Data Sheet 24 Notes V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information Table 6 Package Pin Mapping (cont’d) Function VQFN 40 TSSOP TSSOP VQFN 38 28 24 TSSOP Pad 16 Type Notes VSSP 31 25 - - - Power I/O port ground VDDP 32 26 - - - Power I/O port supply VSSP Exp. Pad - - Exp. Pad - Power Exposed Die Pad The exposed die pad is connected internally to VSSP. For proper operation, it is mandatory to connect the exposed pad to the board ground. For thermal aspects, please refer to the Package and Reliability chapter. 2.2.2 Port I/O Function Description The following general building block is used to describe the I/O functions of each PORT pin: Table 7 Function Port I/O Function Description Outputs ALT1 P0.0 Pn.y Data Sheet Inputs ALTn Input MODA.OUT MODC.INA MODA.OUT MODA.INA 25 Input MODC.INB V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information Pn.y XMC1000 Control Logic PAD Input 0 MODA.INA MODA MODB MODB.OUT Input n HWI0 HWI1 SW Pn.y ALT1 ... ALTn HWO0 HWO1 Figure 9 VDDP ... GND Simplified Port Structure Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value. Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad). The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources. The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin. Please refer to the Port I/O Functions table for the complete Port I/O function mapping. Data Sheet 26 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family General Device Information 2.2.3 Hardware Controlled I/O Function Description The following general building block is used to describe the hardware I/O and pull control functions of each PORT pin: Table 8 Hardware Controlled I/O Function Description Function Outputs Inputs Pull Control P0.0 HWO0 HWI0 HW0_PD HW0_PU MODB.OUT MODB.INA MODC.OUT MODC.OUT Pn.y By Pn_HWSEL, it is possible to select between different hardware “masters” (HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers. Additional hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the peripherals can be used to control the pull devices of the pin. Please refer to the Hardware Controlled I/O Functions table for the complete hardware I/O and pull control function mapping. Data Sheet 27 V2.0, 2017-10 Data Sheet Ports, V2.3 ERU0. PDOUT0 ERU0. PDOUT1 ERU0. PDOUT2 ERU0. PDOUT3 BCCU0. OUT0 BCCU0. OUT1 BCCU0. OUT2 BCCU0. OUT3 BCCU0. OUT4 BCCU0. OUT5 BCCU0. OUT6 BCCU0. OUT7 BCCU0. OUT6 WWDT. SERVICE _OUT P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 ALT1 ALT2 ERU0. GOUT3 ERU0. GOUT2 ERU0. GOUT1 ERU0. GOUT0 ALT3 2-28 CCU80. OUT22 CCU80. OUT21 CCU80. OUT20 CCU80. OUT10 CCU80. OUT11 CCU80. OUT12 CCU80. OUT13 CCU80. OUT03 CCU80. OUT02 CCU80. OUT01 CCU80. OUT00 ALT5 CCU80. OUT32 CCU80. OUT33 USIC0_C CCU80. H0.MCLK OUT23 OUT ACMP0. OUT CCU40. OUT3 CCU40. OUT2 CCU40. OUT1 CCU40. OUT0 CCU40. OUT0 CCU40. OUT1 CCU40. OUT3 CCU40. OUT2 CCU40. OUT1 CCU40. OUT0 ALT4 Outputs Port I/O Functions P0.0 Function Table 2-1 ALT7 Input Input CCU80. OUT01 WWDT. SERVICE _OUT CCU80. OUT11 CCU80. OUT10 SCU. VDROP CCU40. IN2A USIC0_C USIC0_C H0.DX2C H1.DX2C USIC0_C USIC0_C H0.DX2B H1.DX2B USIC0_C USIC0_C H0.DX1B H1.DX1B USIC0_C CCU80. H0.SELO OUT21 4 CCU80. IN3B POSIF0. IN0B USIC0_C H0.DX2F CCU80. IN0A CCU40. IN3A CCU40. IN1A Input CCU80. IN1A USIC0_C USIC0_C USIC0_C H0.DX1C H1.DX0D H1.DX1C USIC0_C H1.DX0C USIC0_C USIC0_C H0.DX2A H1.DX2A Input Inputs Input USIC0_C CCU80. H0.SELO OUT20 3 BCCU0. CCU40. TRAPINA IN0A Input USIC0_C USIC0_C H0.DX2D H1.DX2D CCU80. IN2B CCU40. IN3B CCU40. IN2B CCU40. IN1B CCU40. IN0B CCU80. IN1B CCU80. IN0B CCU40. IN3C CCU40. IN2C CCU40. IN1C Input USIC0_C USIC0_C H0.SELO H1.SELO 2 2 USIC0_C USIC0_C H0.SELO H1.SELO 1 1 USIC0_C USIC0_C H0.SELO H1.SELO 0 0 USIC0_C USIC0_C H0.SCLK H1.SCLK OUT OUT USIC0_C USIC0_C H0.SCLK H1.DOUT OUT 0 USIC0_C USIC0_C H1.MCLK H1.DOUT 0 OUT ACMP2. OUT VADC0. EMUX00 VADC0. EMUX01 VADC0. EMUX02 BCCU0. OUT8 USIC0_C USIC0_C BCCU0. CCU40. H0.SELO H1.SELO TRAPINB IN0C 0 0 ALT6 CCU80. IN2A Input CCU80. IN3A Input USIC0_C H0.DX2E Input XMC1300 AB-Step XMC1000 Family V2.0, 2017-10 Data Sheet Ports, V2.3 2-29 ERU0. PDOUT3 ERU0. PDOUT2 P2.0 P2.1 ALT7 USIC0_C H0.DOUT 0 ACMP2.I NN USIC0_C USIC0_C ACMP2.I H0.DOUT H1.SCLK NP 0 OUT VADC0. G0CH7 VADC0. G0CH6 VADC0. G0CH5 VADC0. G1CH6 CCU80. OUT21 USIC0_C USIC0_C H0.DOUT H0.SCLK 0 OUT USIC0_C USIC0_C H0.SELO H1.SELO 2 3 Input P2.4 ERU0. GOUT2 CCU80. OUT20 USIC0_C BCCU0. H0.SCLK OUT2 OUT Input VADC0. G1CH5 CCU40. OUT1 CCU40. OUT0 USIC0_C H1.DOUT 0 USIC0_C USIC0_C H0.SELO H1.SELO 1 2 CCU80. OUT21 USIC0_C H0.DOUT 0 USIC0_C H1.DOUT 0 USIC0_C USIC0_C H0.SELO H1.SELO 1 0 ACMP2. OUT USIC0_C USIC0_C H0.DOUT H1.SELO 0 0 ACMP1. OUT USIC0_C USIC0_C H0.DOUT H1.MCLK 0 OUT USIC0_C USIC0_C H0.DOUT H0.SCLK 0 OUT ALT6 CCU80. OUT20 CCU80. OUT10 CCU80. OUT01 CCU80. OUT00 CCU80. OUT30 CCU80. OUT31 ALT5 USIC0_C H1.SCLK OUT BCCU0. OUT1 ALT4 Outputs USIC0_C USIC0_C H1.SCLK H1.DOUT 0 OUT ERU0. GOUT3 ALT3 CCU80. OUT11 CCU40. OUT3 CCU40. OUT2 CCU40. OUT1 CCU40. OUT0 ALT2 P2.3 P2.2 VADC0. EMUX12 VADC0. EMUX02 P1.3 P1.6 VADC0. EMUX01 P1.2 VADC0. EMUX11 VADC0. EMUX00 P1.1 P1.5 BCCU0. OUT0 P1.0 VADC0. EMUX10 BCCU0. OUT8 P0.15 P1.4 BCCU0. OUT7 ALT1 Port I/O Functions (cont’d) P0.14 Function Table 2-1 USIC0_C H0.DX5F POSIF0. IN0A POSIF0. IN1A POSIF0. IN2A POSIF0. IN2B POSIF0. IN1B Input Input USIC0_C H1.DX5F USIC0_C USIC0_C H0.DX5E H1.DX5E USIC0_C USIC0_C H1.DX0A H1.DX1A USIC0_C H1.DX0B USIC0_C USIC0_C USIC0_C H0.DX0D H0.DX1D H1.DX2E USIC0_C H0.DX0C USIC0_C H0.DX0B USIC0_C USIC0_C H0.DX0A H0.DX1A Input Inputs Input Input ERU0.0A USIC0_C USIC0_C USIC0_C ORC2.AI 1 H0.DX3B H0.DX4B H1.DX5B N ERU0.1B USIC0_C USIC0_C USIC0_C ORC1.AI 1 H0.DX5B H1.DX3C H1.DX4C N ERU0.0B USIC0_C USIC0_C USIC0_C ORC0.AI 1 H0.DX3A H0.DX4A H1.DX5A N ERU0.1B USIC0_C USIC0_C USIC0_C 0 H0.DX0F H1.DX3A H1.DX4A ERU0.0B USIC0_C USIC0_C USIC0_C 0 H0.DX0E H0.DX1E H1.DX2F Input Input Input XMC1300 AB-Step XMC1000 Family V2.0, 2017-10 Data Sheet Ports, V2.3 ERU0. PDOUT1 ERU0. PDOUT0 P2.10 P2.11 CCU40. OUT3 CCU40. OUT2 ERU0. GOUT0 ERU0. GOUT1 CCU80. OUT31 CCU80. OUT30 USIC0_C H1.DOUT 0 VADC0. G0CH3 VADC0. G0CH2 USIC0_C USIC0_C ACMP.RE VADC0. H1.SCLK H1.DOUT F G0CH4 OUT 0 ACMP0. OUT ACMP0.I NP VADC0. G0CH1 VADC0. G1CH1 P2.9 Input ACMP0.I NN Input P2.8 ALT7 ACMP1.I NP ALT6 P2.7 ALT5 VADC0. G0CH0 ALT4 Outputs ACMP1.I NN ALT3 P2.6 ALT2 VADC0. G1CH7 ALT1 Port I/O Functions (cont’d) P2.5 Function Table 2-1 VADC0. G1CH3 VADC0. G1CH2 VADC0. G1CH4 VADC0. G1CH0 Input Input Inputs Input Input Input ERU0.2B USIC0_C USIC0_C 1 H1.DX0E H1.DX1E ERU0.2B USIC0_C USIC0_C USIC0_C 0 H0.DX3C H0.DX4C H1.DX0F ERU0.3B USIC0_C USIC0_C USIC0_C ORC7.AI 0 H0.DX5A H1.DX3B H1.DX4B N ERU0.3B USIC0_C USIC0_C USIC0_C ORC6.AI 1 H0.DX3D H0.DX4D H1.DX5C N ERU0.3A USIC0_C USIC0_C USIC0_C ORC5.AI 1 H0.DX5C H1.DX3D H1.DX4D N ERU0.2A USIC0_C USIC0_C USIC0_C ORC4.AI 1 H0.DX3E H0.DX4E H1.DX5D N ERU0.1A USIC0_C USIC0_C USIC0_C ORC3.AI 1 H0.DX5D H1.DX3E H1.DX4E N Input Input Input XMC1300 AB-Step XMC1000 Family 2-30 V2.0, 2017-10 Data Sheet Ports, V3.1 2-31 BCCU0.OUT6 BCCU0.OUT0 ACMP2.OUT BCCU0.OUT8 P2.2 P2.3 P2.4 BCCU0.OUT1 P2.0 P2.1 BCCU0.OUT8 P1.6 BCCU0.OUT5 BCCU0.OUT7 USIC0_CH0.HWIN3 BCCU0.OUT4 BCCU0.OUT3 BCCU0.OUT2 HW0_PD P1.5 USIC0_CH0.DOUT3 P1.3 USIC0_CH0.HWIN2 USIC0_CH0.HWIN1 USIC0_CH0.HWIN0 HWI1 Inputs BCCU0.OUT6 USIC0_CH0.DOUT2 P1.2 HWI0 P1.4 USIC0_CH0.DOUT0 USIC0_CH0.DOUT1 HWO1 Outputs P1.0 HWO0 Hardware Controlled I/O Functions P1.1 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.9 P0.8 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Function Table 2-2 BCCU0.OUT8 ACMP2.OUT BCCU0.OUT0 BCCU0.OUT6 BCCU0.OUT1 BCCU0.OUT8 BCCU0.OUT7 BCCU0.OUT6 BCCU0.OUT5 BCCU0.OUT4 BCCU0.OUT3 BCCU0.OUT2 HW0_PU CCU40.OUT3 HW1_PD Pull Control CCU40.OUT3 HW1_PU XMC1300 AB-Step XMC1000 Family V2.0, 2017-10 HWO1 Outputs HWI0 HWI1 Inputs HW0_PD Data Sheet Ports, V3.1 BCCU0.OUT2 BCCU0.OUT8 BCCU0.OUT1 BCCU0.OUT7 BCCU0.OUT4 BCCU0.OUT5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 ACMP1.OUT HWO0 Hardware Controlled I/O Functions (cont’d) P2.5 Function Table 2-2 BCCU0.OUT5 BCCU0.OUT4 BCCU0.OUT7 BCCU0.OUT1 BCCU0.OUT8 BCCU0.OUT2 ACMP1.OUT HW0_PU CCU40.OUT2 CCU40.OUT2 CCU40.OUT3 CCU40.OUT3 HW1_PD Pull Control CCU40.OUT2 CCU40.OUT2 CCU40.OUT3 CCU40.OUT3 HW1_PU XMC1300 AB-Step XMC1000 Family 2-32 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3 Electrical Parameters This section provides the electrical parameters which are implementation-specific for the XMC1300. 3.1 General Parameters 3.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the XMC1300 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column: • • CC Such parameters indicate Controller Characteristics, which are distinctive feature of the XMC1300 and must be regarded for a system design. SR Such parameters indicate System Requirements, which must be provided by the application system in which the XMC1300 is designed in. Data Sheet 33 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.1.2 Absolute Maximum Ratings Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 9 Absolute Maximum Rating Parameters Parameter Symbol Values Min Typ. Max. . Unit Note / Test Cond ition TJ SR -40 – TST SR -40 – VDDP SR -0.3 – 115 °C – 125 °C – 6 V – Voltage on digital pins with respect to VSSP1) VIN VDDP + 0.5 V Voltage on P2 pins with respect to VSSP2) Voltage on analog input pins with respect to VSSP Junction temperature Storage temperature Voltage on power supply pin with respect to VSSP Input current on any pin during overload condition or max. 6 whichever is lower VINP2 SR -0.3 – VDDP + 0.3 V – VAIN -0.5 – VAREF SR IIN SR -10 – VDDP + 0.5 V whichever is lower Absolute maximum sum of all ΣIIN input currents during overload condition SR -0.5 – SR -50 – or max. 6 10 mA – +50 mA – 1) Excluding port pins P2.[1,2,6,7,8,9,11]. 2) Applicable to port pins P2.[1,2,6,7,8,9,11]. Data Sheet 34 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.1.3 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 10 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: • • full operation life-time is not exceeded Operating Conditions are met for – pad supply levels (VDDP) – temperature If a pin current is outside of the Operating Conditions but within the overload conditions, then the parameters of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery. Table 10 Overload Parameters Parameter Symbol Values Min. Input current on any port pin during overload condition IOV Absolute sum of all input circuit currents during overload condition IOVS SR – SR -5 Typ. Unit Note / Test Condition Max. – 5 mA – 25 mA Figure 10 shows the path of the input currents during overload via the ESD protection structures. The diodes against VDDP and ground are a simplified representation of these ESD protection structures. Data Sheet 35 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters VDDP VDDP Pn.y IOVx GND ESD Figure 10 GND Pad Input Overload Current via ESD structures Table 11 and Table 12 list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the Absolute Maximum Ratings must not be exceeded during overload. Table 11 PN-Junction Characterisitics for positive Overload Pad Type Standard, High-current, AN/DIG_IN P2.[1,2,6:9,11] Table 12 PN-Junction Characterisitics for negative Overload Pad Type Standard, High-current, AN/DIG_IN P2.[1,2,6:9,11] Data Sheet IOV = 5 mA VIN = VDDP + 0.5 V VAIN = VDDP + 0.5 V VAREF = VDDP + 0.5 V VINP2 = VDDP + 0.3 V IOV = 5 mA VIN = VSS - 0.5 V VAIN = VSS - 0.5 V VAREF = VSS - 0.5 V VINP2 = VSS - 0.3 V 36 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.1.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC1300. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise. Table 13 Operating Conditions Parameters Parameter Symbol Values Min. Unit Note / Test Condition 85 °C Temp. Range F Temp. Range X Typ. Max. SR -40 − Ambient Temperature TA -40 − 105 °C Digital supply voltage1) VDDP SR 1.8 fMCLK CC − fPCLK CC − − 5.5 V − 33.2 MHz CPU clock − 66.4 MHz Peripherals clock Short circuit current of digital outputs ISC − 5 mA Absolute sum of short circuit currents of the device ΣISC_D SR − − 25 mA MCLK Frequency PCLK Frequency SR -5 1) See also the Supply Monitoring thresholds, Chapter 3.3.2. Data Sheet 37 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2 DC Parameters 3.2.1 Input/Output Characteristics Table 14 provides the characteristics of the input/output pins of the XMC1300. Note: These parameters are not subject to production test, but verified by design and/or characterization. Note: Unless otherwise stated, input DC and AC characteristics, including peripheral timings, assume that the input pads operate with the standard hysteresis. Table 14 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Output low voltage on port pins (with standard pads) VOLP Output low voltage on high current pads VOLP1 Output high voltage on port pins (with standard pads) VOHP Unit Test Conditions V IOL = 11 mA (5 V) IOL = 7 mA (3.3 V) IOL = 5 mA (5 V) IOL = 3.5 mA (3.3 V) IOL = 50 mA (5 V) IOL = 25 mA (3.3 V) IOL = 10 mA (5 V) IOL = 5 mA (3.3 V) IOH = -10 mA (5 V) IOH = -7 mA (3.3 V) IOH = -4.5 mA (5 V) IOH = -2.5 mA (3.3 V) IOH = -6 mA (5 V) V IOH = -8 mA (3.3 V) V IOH = -4 mA (3.3 V) 0.19 × V CMOS Mode (5 V, 3.3 V & 2.2 V) Max. CC – 1.0 V – 0.4 V CC – 1.0 V – 0.32 V – 0.4 V – V VDDP - – V CC VDDP 1.0 0.4 Output high voltage on high current pads VOHP1 CC VDDP - – 0.32 VDDP - – 1.0 VDDP - – 0.4 Input low voltage on port VILPS pins (Standard Hysteresis) Data Sheet SR – VDDP 38 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 14 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Input high voltage on port pins (Standard Hysteresis) Symbol VIHPS SR SR Input high voltage on port pins (Large Hysteresis) VIHPL SR Rise time on High Current Pad1) tHCPR Rise time on Standard Pad1) Fall time on Standard Pad1) Data Sheet Max. 0.7 × – Unit Test Conditions V CMOS Mode (5 V, 3.3 V & 2.2 V) VDDP Input low voltage on port VILPL pins (Large Hysteresis) Fall time on High Current Pad1) Limit Values Min. 0.08 × V – VDDP 0.85 × – V CMOS Mode (5 V, 3.3 V & 2.2 V)18) 9 ns 50 pF @ 5 V2) – 12 ns 50 pF @ 3.3 V3) – 25 ns 50 pF @ 1.8 V4) 9 ns 50 pF @ 5 V2) – 12 ns 50 pF @ 3.3 V3) – 25 ns 50 pF @ 1.8 V4) CC – 12 ns 50 pF @ 5 V5) – 15 ns 50 pF @ 3.3 V6) – 31 ns 50 pF @ 1.8 V7) CC – 12 ns 50 pF @ 5 V5) – 15 ns 50 pF @ 3.3 V6) – 31 ns 50 pF @ 1.8 V7) VDDP tHCPF tR tF CMOS Mode (5 V, 3.3 V & 2.2 V)18) CC – CC – 39 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 14 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol Limit Values Min. Input Hysteresis8) HYS Unit Test Conditions V CMOS Mode (5 V), Standard Hysteresis V CMOS Mode (3.3 V), Standard Hysteresis V CMOS Mode (2.2 V), Standard Hysteresis Max. CC 0.08 × – VDDP 0.03 × – VDDP 0.02 × – VDDP 0.5 × 0.75 × V VDDP VDDP 0.4 × 0.75 × V VDDP VDDP 0.2 × 0.65 × V VDDP VDDP CMOS Mode(5 V), Large Hysteresis CMOS Mode(3.3 V), Large Hysteresis CMOS Mode(2.2 V), Large Hysteresis Pin capacitance (digital inputs/outputs) CIO CC – 10 pF Pull-up resistor on port pins RPUP CC 20 50 kohm VIN = VSSP Pull-down resistor on port pins RPDP CC 20 50 kohm VIN = VDDP Input leakage current9) IOZP CC -1 1 μA 0 < VIN < VDDP, TA ≤ 105 °C Voltage on any pin during VDDP power off VPO SR – 0.3 V 10) Maximum current per pin (excluding P1, VDDP and VSS) IMP SR -10 11 mA – Maximum current per high currrent pins IMP1A SR -10 50 mA – Maximum current into VDDP (TSSOP16, VQFN24) IMVDD1 SR – 130 mA 18) Maximum current into VDDP (TSSOP38, VQFN40) IMVDD2 SR – 260 mA 18) Data Sheet 40 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 14 Parameter Input/Output Characteristics (Operating Conditions apply) (cont’d) Symbol Limit Values Unit Test Conditions 130 mA 18) 260 mA 18) Min. Max. Maximum current out of IMVSS1 SR VSS (TSSOP16, VQFN24) – Maximum current out of IMVSS2 SR VSS (TSSOP38, VQFN40) – 1) Rise/Fall time parameters are taken with 10% - 90% of supply. 2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage. 3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage. 4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage. 5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage. 6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage. 7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage. 8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. 10) However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Data Sheet 41 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2.2 Analog to Digital Converters (ADC) Table 15 shows the Analog to Digital Converter (ADC) characteristics. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 15 ADC Characteristics (Operating Conditions apply)1) Parameter Symbol Values Min. Supply voltage range (internal reference) Unit Note / Test Condition Typ. Max. VDD_int SR 2.0 – 3.0 V SHSCFG.AREF = 11B CALCTR.CALGNSTC = 0CH 3.0 – 5.5 V SHSCFG.AREF = 10B 3.0 – 5.5 V SHSCFG.AREF = 00B VSSP – VDDP V Supply voltage range (external reference) VDD_ext Analog input voltage range VAIN SR Auxiliary analog reference ground VREFGND VSSP SR - 0.05 SR - 0.05 VSSP + 0.05 – 1.0 V G0CH0 – 0.2 V G1CH0 - 0.05 Internal reference voltage (full scale value) VREFINT 5 V CC Switched capacitance CAINS CC of an analog input – 1.2 2 pF GNCTRxz.GAINy = 00B (unity gain) – 1.2 2 pF GNCTRxz.GAINy = 01B (gain g1) – 4.5 6 pF GNCTRxz.GAINy = 10B (gain g2) – 4.5 6 pF GNCTRxz.GAINy = 11B (gain g3) Total capacitance of an analog input CAINT CC – – 10 pF Total capacitance of the reference input CAREFT – 10 pF Data Sheet – CC 42 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 15 ADC Characteristics (Operating Conditions apply)1) (cont’d) Parameter Symbol Values Min. Gain settings Sample Time GIN CC Unit Note / Test Condition Typ. Max. 1 – GNCTRxz.GAINy = 00B (unity gain) 3 – GNCTRxz.GAINy = 01B (gain g1) 6 – GNCTRxz.GAINy = 10B (gain g2) 12 – GNCTRxz.GAINy = 11B (gain g3) 1/ VDD = 5.0 V tsample CC 3 – – fADC 3 – – 1/ VDD = 3.3 V fADC 30 – – 1/ VDD = 2.0 V fADC Sigma delta loop hold time tSD_hold Conversion time in fast compare mode tCF CC Conversion time in 12-bit mode tC12 CC 20 – – μs Residual charge stored in an active sigma delta loop remains available 1/ 2) CC 9 fADC Maximum sample rate fC12 CC in 12-bit mode 3) 20 – – 1/ – – fADC fADC / – 1 sample 42.5 pending fADC / – 2 samples pending 62.5 Conversion time in 10-bit mode tC10 CC Maximum sample rate fC10 CC in 10-bit mode 3) 18 – – 1/ – – Data Sheet tC8 CC 16 2) fADC fADC / – 1 sample 40.5 pending fADC / – 2 samples pending 58.5 Conversion time in 8-bit mode 2) 1/ 2) fADC 43 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 15 ADC Characteristics (Operating Conditions apply)1) (cont’d) Parameter Symbol Maximum sample rate fC8 CC in 8-bit mode 3) Values Unit Note / Test Condition Min. Typ. Max. – – fADC / – 38.5 – – fADC / – 54.5 RMS noise 4) ENRMS – 1.5 – CC 1 sample pending 2 samples pending LSB DC input, 12 VDD = 5.0 V, VAIN = 2.5 V, 25°C DNL error EADNL CC – ±2.0 – LSB 12 INL error EAINL CC – ±4.0 – LSB 12 Gain error with external reference EAGAIN – ±0.5 – % CC SHSCFG.AREF = 00B (calibrated) – ±3.6 – % SHSCFG.AREF = 1XB (calibrated), -40°C - 105°C – ±2.0 – % SHSCFG.AREF = 1XB (calibrated), 0°C - 85°C EAOFF CC – ±8.0 – mV Calibrated, VDD = 5.0 V Gain error with internal EAGAIN reference 5) CC Offset error 1) The parameters are defined for ADC clock frequency fSH = 32MHz, SHSCFG.DIVS = 0000B. Usage of any other frequencies may affect the ADC performance. 2) No pending samples assumed, excluding sampling time and calibration. 3) Includes synchronization and calibration (average of gain and offset calibration). 4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS). With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12]. NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB. 5) Includes error from the reference voltage. Data Sheet 44 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters VAIN SAR Converter : 0 VSS 1X VCAL 00 1 VREFGND VDD VREF VAGND CH7 . . CH0 VREFINT VAREF Internal Reference VDDint/ VDD VDDext CHNR REFSEL AREF MC_VADC_AREFPATHS Figure 11 Data Sheet ADC Voltage Supply 45 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2.3 Out of Range Comparator (ORC) Characteristics The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the VDDP on selected input pins (ORCx.AIN) and generates a service request trigger (ORCx.OUT). Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 16 Out of Range Comparator (ORC) Characteristics (Operating Conditions apply; VDDP = 3.0 V - 5.5 V; CL = 0.25 pF) Parameter Symbol Values Min. Typ. DC Switching Level VODC CC 54 Hysteresis Always detected Overvoltage Pulse Never detected Overvoltage Pulse VOHYS CC 15 tOPDD CC 103 Unit Note / Test Condition Max. − 183 mV − 54 mV − - ns − - ns tOPDN CC − − 21 ns − − 11 ns 88 VAIN ≥ VDDP + VODC VAIN ≥ VDDP + 150 mV VAIN ≥ VDDP + 350 mV VAIN ≥ VDDP + 150 mV VAIN ≥ VDDP + 350 mV VAIN ≥ VDDP + 150 mV VAIN ≥ VDDP + 350 mV CC 39 − 132 ns 31 − 121 ns Release Delay tORD CC 44 − 240 ns 57 − 340 ns VAIN ≤ VDDP; VDDP = 5 V VAIN ≤ VDDP; VDDP = 3.3 V Enable Delay tOED CC − − 300 ns ORCCTRL.ENORCx = 1 VODC VOH YS Detection Delay of a tODD persistent Overvoltage VD D P VSS ORCx.AIN ORCx.OUT tOD D Figure 12 Data Sheet tOR D ORCx.OUT Trigger Generation 46 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters V AIN (V) T < tOPDN VDDP + 350 mV T < tOPDN VDDP + 150 mV tOPDN < T < tOPDD t OPDN < T < tOPDD T > tOPDD T > tOPDD T > tOPDD V DDP + 60 mV VDDP VSSA Figure 13 Data Sheet Never detected Overvoltage Pulse (Too low) Overvoltage may be detected (long enough, level uncertain ) Never detected Overvoltage Pulse (Too short) Overvoltage may be detected Always detected Overvoltage Pulse Never detected Overvoltage Pulse (Too short) Overvoltage may be detected Always detected Overvoltage Pulse ORC Detection Ranges 47 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2.4 Analog Comparator Characteristics Table 17 below shows the Analog Comparator characteristics. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 17 Analog Comparator Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Typ. Max. Unit Notes/ Test Conditions Input Voltage VCMP SR -0.05 – VDDP + V 0.05 Input Offset VCMPOFF CC – – mV High power mode Δ VCMP < 200 mV +/-20 – mV Low power mode Δ VCMP < 200 mV CC – 25 – ns High power mode, Δ VCMP = 100 mV – 80 – ns High power mode, Δ VCMP = 25 mV – 250 – ns Low power mode, Δ VCMP = 100 mV – 700 – ns Low power mode, Δ VCMP = 25 mV CC – 100 – μA First active ACMP in high power mode, ΔVCMP > 30 mV – 66 – μA Each additional ACMP in high power mode, ΔVCMP > 30 mV – 10 – μA First active ACMP in low power mode – 6 – μA Each additional ACMP in low power mode – Propagation Delay1) Current Consumption Input Hysteresis Filter Delay 1) tPDELAY IACMP VHYS tFDELAY +/-3 CC – +/-15 – mV CC – 5 ns – 1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay. Data Sheet 48 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2.5 Temperature Sensor Characteristics Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 18 Temperature Sensor Characteristics Parameter Symbol Values Min. Typ. Measurement time Temperature sensor range Sensor Accuracy1) Start-up time after enabling Unit Note / Test Condition 10 ms tM CC − TSR SR -40 TTSAL CC -6 − 115 °C – 6 °C -10 – 10 °C − -/+8 – °C − 15 μs tTSSTE SR − − Max. TJ > 20°C 0°C ≤ TJ ≤ 20°C TJ < 0°C 1) The temperature sensor accuracy is independent of the supply voltage. Data Sheet 49 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2.6 Power Supply Current The total power supply current defined below consists of a leakage and a switching component. Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 19 Power Supply Parameters; VDDP = 5V Parameter Symbol Values Unit Note / Test Condition Min Typ.1) Max. . Active mode current Peripherals enabled fMCLK / fPCLK in MHz2) Active mode current Peripherals disabled fMCLK / fPCLK in MHz3) Active mode current Code execution from RAM Flash is powered down fMCLK / fPCLK in MHz Sleep mode current Peripherals clock enabled fMCLK / fPCLK in MHz4) Data Sheet IDDPAE CC − 9.2 12 mA 32 / 64 − 8.1 - mA 24 / 48 − 6.6 - mA 16 / 32 − 5.5 - mA 8 / 16 − 4 - mA 1/1 IDDPAD CC − 4.8 - mA 32 / 64 − 4.1 - mA 24 / 48 − 3.3 - mA 16 / 32 − 2.7 - mA 8 / 16 − 1.5 - mA 1/1 IDDPAR CC − 7.3 - mA 32 / 64 − 6.3 - mA 24 / 48 − 5.2 - mA 16 / 32 − 4.2 - mA 8 / 16 − 3.3 - mA 1/1 IDDPSE CC − 6.6 - mA 32 / 64 5.8 - mA 24 / 48 5.1 - mA 16 / 32 4.4 - mA 8 / 16 3.7 - mA 1/1 50 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 19 Power Supply Parameters; VDDP = 5V Parameter Symbol Values Unit Note / Test Condition Min Typ.1) Max. . Sleep mode current Peripherals clock disabled Flash active fMCLK / fPCLK in MHz5) Sleep mode current Peripherals clock disabled Flash powered down fMCLK / fPCLK in MHz6) Deep Sleep mode current 7) IDDPSD CC − IDDPSR CC − IDDPDS CC − 1.8 - mA 32 / 64 1.7 - mA 24 / 48 1.6 - mA 16 / 32 1.5 - mA 8 / 16 1.4 - mA 1/1 1.2 - mA 32 / 64 1.1 - mA 24 / 48 1.0 - mA 16 / 32 0.8 - mA 8 / 16 0.7 - mA 1/1 0.24 - mA Wake-up time from Sleep to tSSA CC Active mode8) − 6 - cycles tDSA CC − 280 - μsec Wake-up time from Deep Sleep to Active mode9) 1) The typical values are measured at TA = + 25 °C and VDDP = 5 V. 2) CPU and all peripherals clock enabled, Flash is in active mode. 3) CPU enabled, all peripherals clock disabled, Flash is in active mode. 4) CPU in sleep, all peripherals clock enabled and Flash is in active mode. 5) CPU in sleep, Flash is in active mode. 6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up. 7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up. 8) CPU in sleep, Flash is in active mode during sleep mode. 9) CPU in sleep, Flash is in powered down mode during deep sleep mode. Data Sheet 51 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Figure 14 shows typical graphs for active mode supply current for VDDP = 5V, VDDP = 3.3V, VDDP = 1.8V across different clock frequencies. 10 9 8 7 6 I (m A) 5 4 3 2 1 0 IDDPA E 5V/3.3V IDDPA E 1.8V IDDPA D 5V/3.3V/1.8V 1/1 8/16 16/32 24/48 32/64 M CLK / PCLK (M Hz) Condition: 1. TA = +25° C Figure 14 Active mode, a) peripherals clocks enabled, b) peripherals clocks disabled: Supply current IDDPA over supply voltage VDDP for different clock frequencies Data Sheet 52 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Figure 15 shows typical graphs for sleep mode current for VDDP = 5V, VDDP = 3.3V, VDDP = 1.8V across different clock frequencies. 1 .4 1 .2 1 I (m A ) 0 .8 0 .6 ID D P S R 5 V /3 .3 V /1 .8 V 0 .4 0 .2 0 1 /1 8 /1 6 1 6 / 3 2 2 4 / 4 8 3 2 / 64 M C L K / P C L K (M H z ) C o n d itio n : 1. TA = +25° C Figure 15 Data Sheet Sleep mode, peripherals clocks disabled, Flash powered down: Supply current IDDPSR over supply voltage VDDP for different clock frequencies 53 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 20 provides the active current consumption of some modules operating at 5 V power supply at 25° C. The typical values shown are used as a reference guide on the current consumption when these modules are enabled. Table 20 Typical Active Current Consumption Active Current Consumption Symbol Limit Values Unit Test Condition Typ. Baseload current ICPUDDC 5.04 mA Modules including Core, SCU, PORT, memories, ANATOP1) VADC and SHS IADCDDC IUSIC0DDC ICCU40DDC ICCU80DDC IPIF0DDC IBCCU0DDC IMATHDDC IWDTDDC IRTCDDC 3.4 mA Set CGATCLR0.VADC to 12) 0.87 mA Set CGATCLR0.USIC0 to 13) 0.94 mA Set CGATCLR0.CCU40 to 14) 0.42 mA Set CGATCLR0.CCU80 to 15) 0.26 mA Set CGATCLR0.POSIF0 to 16) 0.24 mA Set CGATCLR0.BCCU0 to 17) 0.35 mA Set CGATCLR0.MATH to 18) 0.03 mA Set CGATCLR0.WDT to 19) 0.01 mA Set CGATCLR0.RTC to 110) USIC0 CCU40 CCU80 POSIF0 BCCU0 MATH WDT RTC 1) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop in the flash memory. The clock to the modules stated in CGATSTAT0 are gated. 2) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode 3) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms 4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching from 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle 5) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU8 slice with PWM frequency at 1500Hz and a period match interrupt used to toggle duty cycle between 10% and 90% 6) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, hall sensor mode 7) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, FCLK=0.8MHz, Normal mode (BCCU Clk = FCLK/4), 3 BCCU Channels and 1 Dimming Engine, change color or dim every 1s 8) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, tangent calculation in while loop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11 9) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB = 0x00008000; WDT serviced every 1s 10) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled Data Sheet 54 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.2.7 Flash Memory Parameters Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 21 Flash Memory Parameters Parameter Symbol Values Unit Min. Typ. Max. Erase Time per page / sector tERASE CC 6.8 7.1 7.6 ms Program time per block tPSER CC 102 152 204 μs Wake-Up time − 32.2 − μs − 50 − ns Data Retention Time tWU CC ta CC tRET CC 10 − − years Flash Wait States 1) NWSFLASH CC 0 0 0 0 1 1 Read time per word Note / Test Condition Max. 100 erase / program cycles fMCLK = 8 MHz fMCLK = 16 MHz fMCLK = 32 MHz 1 1.3 2 Fixed Flash Wait NFWSFLASH States configured in SR bit NVM_NVMCONF.WS 0 0 1 NVM_CONFIG1.FI XWS = 1B, fMCLK ≤ 16 MHz 1 1 1 NVM_CONFIG1.FI XWS = 1B, 16 MHz < fMCLK ≤ 32 MHz Erase Cycles NECYC CC − − 5*104 cycles Sum of page and sector erase cycles Total Erase Cycles NTECYC CC − − 2*106 cycles 1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical values are calculated from the execution of the Dhrystone benchmark program. Data Sheet 55 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3 AC Parameters 3.3.1 Testing Waveforms VD D P VSS 90% 90% 10% 10% tR Figure 16 tF Rise/Fall Time Parameters VD D P VD D P / 2 Test Points VD D P / 2 VSS Figure 17 Testing Waveform, Output Delay VL OAD + 0.1V VL OAD - 0.1V Figure 18 Data Sheet Timing Reference Points VOH - 0.1V VOL + 0.1V Testing Waveform, Output High Impedance 56 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3.2 Power-Up and Supply Monitoring Characteristics Table 22 provides the characteristics of the power-up and supply monitoring in XMC1300. The guard band between the lowest valid operating voltage and the brownout reset threshold provides a margin for noise immunity and hysteresis. The electrical parameters may be violated while VDDP is outside its operating range. The brownout detection triggers a reset within the defined range. The prewarning detection can be used to trigger an early warning and issue corrective and/or fail-safe actions in case of a critical supply voltage drop. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 22 Power-Up and Supply Monitoring Parameters (Operating Conditions apply) Parameter Symbol Values Min. Unit Typ. Max. Note / Test Condition VDDP ramp-up time tRAMPUP SR VDDP/ − SVDDPrise 107 μs VDDP slew rate SVDDPOP SR 0 − 0.1 V/μs Slope during normal operation SVDDP10 SR 0 − 10 V/μs Slope during fast transient within +/10% of VDDP SVDDPrise SR 0 − 10 V/μs Slope during power-on or restart after brownout event SVDDPfall1) SR 0 − 0.25 V/μs Slope during supply falling out of the +/-10% limits2) VDDPPW CC 2.1 2.25 2.4 V ANAVDEL.VDEL_ SELECT = 00B 2.85 3 3.15 V ANAVDEL.VDEL_ SELECT = 01B 4.2 4.4 4.6 V ANAVDEL.VDEL_ SELECT = 10B VDDP prewarning voltage Data Sheet 57 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 22 Power-Up and Supply Monitoring Parameters (Operating Conditions apply) (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition calibrated, before user code starts running VDDP brownout reset voltage VDDPBO CC 1.55 1.62 1.75 V VDDP voltage to ensure defined pad states VDDPPA CC − 1.0 − V Start-up time from power-on reset tSSW SR − 320 – μs Time to the first user code instruction3) BMI program time tBMI SR − 8.25 – ms Time taken from a user-triggered system reset after BMI installation is is requested 1) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for this parameter. 2) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to the chip. A larger capacitor value has to be chosen if the power source sink a current. 3) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz and the clocks to peripheral as specified in register CGATSTAT0 are gated. 5.0V } VDDP VDDPPW V DDPBO Figure 19 Data Sheet Supply Threshold Parameters 58 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3.3 On-Chip Oscillator Characteristics Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 23 provides the characteristics of the 64 MHz clock output from the digital controlled oscillator, DCO1 in XMC1300. Table 23 64 MHz DCO1 Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Unit Test Conditions Typ. Max. Nominal frequency fNOM CC – 64 – MHz under nominal conditions1) after trimming Accuracy2) ΔfLT -1.7 – 3.4 % with respect to fNOM(typ), over temperature (TA = 0 °C to 85 °C) -3.9 – 4.0 % with respect to fNOM(typ), over temperature (TA = -40 °C to 105 °C) CC 1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C. 2) The accuracy can be further improved through alternative methods, refer to XMC1000 Oscillator Handling Application Note. Data Sheet 59 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Figure 20 shows the typical curves for the accuracy of DCO1, with and without calibration based on temperature sensor, respectively. 4.00 3.00 Accuracy [%] 2.00 Without calibration based on temperature sensor 1.00 With calibration based on temperature sensor 0.00 - 1.00 - 2.00 - 3.00 - 4.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [ °C] Figure 20 Typical DCO1 accuracy over temperature Table 24 provides the characteristics of the 32 kHz clock output from digital controlled oscillators, DCO2 in XMC1300. Table 24 32 kHz DCO2 Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Nominal frequency fNOM CC – 32.75 – kHz under nominal conditions1) after trimming Accuracy ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ), over temperature (0 °C to 85 °C) -3.9 – 4.0 % with respect to fNOM(typ), over temperature (-40 °C to 105 °C) Min. Typ. Unit Test Conditions Max. 1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C. Data Sheet 60 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3.4 Serial Wire Debug Port (SW-DP) Timing The following parameters are applicable for communication through the SW-DP interface. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 25 SWD Interface Timing Parameters(Operating Conditions apply) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t1 SR t2 SR t3 SR 50 – 500000 ns – 50 – 500000 ns – 10 – – ns – SWDIO input hold t4 SR after SWDCLK rising edge 10 – – ns – SWDCLK high time SWDCLK low time SWDIO input setup to SWDCLK rising edge SWDIO output valid time t5 after SWDCLK rising edge CC – – 68 ns CL = 50 pF – – 62 ns CL = 30 pF t6 SWDIO output hold time from SWDCLK rising edge CC 4 – – ns t1 t2 SWDCLK t6 SWDIO (Output ) t5 t3 t4 SWDIO (Input ) Figure 21 Data Sheet SWD Timing 61 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3.5 SPD Timing Requirements The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the system has maximum robustness against frequency deviations of the sampling clock on tool and on device side. However it is not always possible to exactly match this value with the given constraints for the sample clock. For instance for a oversampling rate of 4, the sample clock will be 8 MHz and in this case the closest possible effective decision time is 5.5 clock cycles (0.69 µs). Table 26 Optimum Number of Sample Clocks for SPD Sample Effective Remark Sample Sampling Sample Freq. Factor Clocks 0B Clocks 1B Decision Time1) 8 MHz 4 1 to 5 6 to 12 0.69 µs The other closest option (0.81 µs) for the effective decision time is less robust. 1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks) For a balanced distribution of the timing robustness of SPD between tool and device, the timing requirements for the tool are: • • Frequency deviation of the sample clock is +/- 5% Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal sample frequency) Data Sheet 62 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3.6 Peripheral Timings Note: These parameters are not subject to production test, but verified by design and/or characterization. 3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: Operating Conditions apply. Table 27 USIC SSC Master Mode Timing Parameter Symbol Values Min. SCLKOUT master clock period Unit Typ. Max. tCLK CC 62.5 − − ns Slave select output SELO t1 active to first SCLKOUT transmit edge CC 80 − − ns Slave select output SELO t2 inactive after last SCLKOUT receive edge CC 0 − − ns CC -10 − 10 ns Receive data input t4 DX0/DX[5:3] setup time to SCLKOUT receive edge SR 80 − − ns Data input DX0/DX[5:3] t5 hold time from SCLKOUT receive edge SR 0 − − ns Data output DOUT[3:0] valid time Data Sheet t3 63 Note / Test Condition V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 28 USIC SSC Slave Mode Timing Parameter Symbol Values Min. Unit Typ. Max. − − ns Select input DX2 setup to t10 first clock input DX1 transmit edge1) SR 10 − − ns Select input DX2 hold after last clock input DX1 receive edge1) t11 SR 10 − − ns Receive data input DX0/DX[5:3] setup time to shift clock receive edge1) t12 SR 10 − − ns Data input DX0/DX[5:3] hold t13 time from clock input DX1 receive edge1) SR 10 − − ns Data output DOUT[3:0] valid t14 time CC - − 80 ns DX1 slave clock period tCLK SR 125 Note / Test Condition 1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 64 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Master Mode Timing t1 Select Output SELOx t2 Inactive Inactive Active Clock Output SCLKOUT Receive Edge First Transmit Edge t3 Last Receive Edge Transmit Edge t3 Data Output DOUT[3:0] t4 Data Input DX0/DX[5:3] t4 t5 Data valid t5 Data valid Slave Mode Timing t1 0 Select Input DX2 Clock Input DX1 t1 1 Active Inactive Receive Edge First Transmit Edge t1 2 Data Input DX0/DX[5:3] Inactive t1 2 t1 3 Data valid t14 Last Receive Edge Transmit Edge t13 Data valid t1 4 Data Output DOUT[3:0] Transmit Edge: with this clock edge, transmit data is shifted to transmit data output. Receive Edge: with this clock edge, receive data at receive data input is latched . Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal. USIC_SSC_TMGX.VSD Figure 22 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted. Data Sheet 65 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters 3.3.6.2 Inter-IC (IIC) Interface Timing The following parameters are applicable for a USIC channel operated in IIC mode. Note: Operating Conditions apply. Table 29 USIC IIC Standard Mode Timing1) Parameter Symbol Values Unit Min. Typ. Max. Fall time of both SDA and t1 SCL CC/SR - - 300 ns Rise time of both SDA and t2 SCL CC/SR - - 1000 ns 0 - - µs 250 - - ns 4.7 - - µs 4.0 - - µs 4.0 - - µs 4.7 - - µs 4.0 - - µs 4.7 - - µs - - 400 pF Data hold time t3 Note / Test Condition CC/SR Data set-up time t4 CC/SR LOW period of SCL clock t5 CC/SR HIGH period of SCL clock t6 CC/SR Hold time for (repeated) START condition t7 Set-up time for repeated START condition t8 Set-up time for STOP condition t9 Bus free time between a STOP and START condition t10 Capacitive load for each bus line Cb SR CC/SR CC/SR CC/SR CC/SR 1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s. Data Sheet 66 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters Table 30 USIC IIC Fast Mode Timing1) Parameter Symbol Values Min. Fall time of both SDA and t1 SCL CC/SR Typ. Unit Max. 20 + 0.1*Cb 300 ns 20 + 0.1*Cb 300 ns 0 - - µs 100 - - ns 1.3 - - µs 0.6 - - µs 0.6 - - µs 0.6 - - µs 0.6 - - µs 1.3 - - µs - - 400 pF Note / Test Condition 2) Rise time of both SDA and t2 SCL CC/SR Data hold time t3 CC/SR Data set-up time t4 CC/SR LOW period of SCL clock t5 CC/SR HIGH period of SCL clock t6 CC/SR Hold time for (repeated) START condition t7 Set-up time for repeated START condition t8 Set-up time for STOP condition t9 Bus free time between a STOP and START condition t10 Capacitive load for each bus line Cb SR CC/SR CC/SR CC/SR CC/SR 1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s. 2) Cb refers to the total capacitance of one bus line in pF. Data Sheet 67 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters t1 SDA t2 t4 70% 30% t1 t3 t2 t6 SCL th t7 9 clock t5 t10 S SDA t8 t7 t9 SCL th 9 clock Sr Figure 23 3.3.6.3 P S USIC IIC Stand and Fast Mode Timing Inter-IC Sound (IIS) Interface Timing The following parameters are applicable for a USIC channel operated in IIS mode. Note: Operating Conditions apply. Table 31 USIC IIS Master Transmitter Timing Parameter Clock period Clock HIGH Symbol t1 CC t2 CC Values Unit Note / Test Condition VDDP ≥ 3 V VDDP < 3 V Min. Typ. Max. 2/fMCLK - - ns 4/fMCLK - - ns 0.35 x - - ns - - ns 0 - - ns - - 0.15 x ns t1min Clock Low t3 CC 0.35 x t1min Hold time Clock rise time t4 CC t5 CC t1min Data Sheet 68 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Electrical Parameters t1 t2 t5 t3 SCK t4 WA/ DOUT Figure 24 USIC IIS Master Transmitter Timing Table 32 USIC IIS Slave Receiver Timing Parameter Symbol t6 SR t7 SR Clock period Clock HIGH Values Unit Min. Typ. Max. 4/fMCLK - - ns 0.35 x - - ns Note / Test Condition t6min Clock Low t8 SR 0.35 x t6min - - ns Set-up time t9 SR 0.2 x t6min - - ns Hold time t10 SR 10 - - ns t6 t7 t8 SCK t9 t10 WA/ DIN Figure 25 Data Sheet USIC IIS Slave Receiver Timing 69 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability 4 Package and Reliability The XMC1300 is a member of the XMC1000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies. Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the exposed die pad may vary. If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration. 4.1 Package Parameters Table 33 provides the thermal characteristics of the packages used in XMC1300. Table 33 Thermal Characteristics of the Packages Parameter Symbol Limit Values Exposed Die Pad Dimensions Ex × Ey CC Thermal resistance Junction-Ambient RΘJA CC - Unit Package Types Min. Max. - 2.7 × 2.7 mm PG-VQFN-24-19 - 3.7 × 3.7 mm PG-VQFN-40-13 104.6 K/W PG-TSSOP-16-81) - 83.2 K/W PG-TSSOP-28-161) - 70.3 K/W PG-TSSOP-38-91) - 46.0 K/W PG-VQFN-24-191) - 38.4 K/W PG-VQFN-40-131) 1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered. Note: For electrical reasons, it is required to connect the exposed pad to the board ground VSSP, independent of EMC and thermal requirements. 4.1.1 Thermal Considerations When operating the XMC1300 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 115 °C. Data Sheet 70 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability The difference between junction temperature and ambient temperature is determined by ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA The internal power consumption is defined as PINT = VDDP × IDDP (switching current and leakage current). The static external power consumption caused by the output drivers is defined as PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL) The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies. If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation: • • • • Reduce VDDP, if possible in the system Reduce the system frequency Reduce the number of output pins Reduce the load on active output drivers Data Sheet 71 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability 4.2 Figure 26 Data Sheet Package Outlines PG-TSSOP-38-9 72 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability Figure 27 Data Sheet PG-TSSOP-28-16 73 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability Figure 28 Data Sheet PG-TSSOP-16-8 74 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability Figure 29 Data Sheet PG-VQFN-24-19 75 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Package and Reliability Figure 30 PG-VQFN-40-13 All dimensions in mm. Data Sheet 76 V2.0, 2017-10 XMC1300 AB-Step XMC1000 Family Quality Declaration 5 Quality Declaration Table 34 shows the characteristics of the quality parameters in the XMC1300. Table 34 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. VHBM ESD susceptibility according to Human Body SR Model (HBM) - 2000 V Conforming to EIA/JESD22A114-B VCDM ESD susceptibility SR according to Charged Device Model (CDM) pins - 500 V Conforming to JESD22-C101-C MSL - 3 - JEDEC J-STD-020D - 260 °C Profile according to JEDEC J-STD-020D Moisture sensitivity level CC Soldering temperature TSDR SR Data Sheet 77 V2.0, 2017-10 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG