74ACT323

74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins June 1988 Revised October 1998 74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins General Description The ACT323 is an 8-bit universal shift/storage register with 3-STATE outputs. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load. Features s ICC and IOZ reduced by 50% s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes: shift left, shift right, load and store s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number 74ACT323PC Package Number N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for DIP Pin Descriptions Pin Name CP DS0 DS7 S0, S1 SR OE1, OE2 I/O0–I/O7 Description Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input 3-STATE Output Enable Inputs Multiplexed Parallel Data Inputs or 3-STATE Parallel Data Outputs Q0, Q7 FACT™ is a trademark of Fairchild Semiconductor Corporation. Serial Outputs © 1999 Fairchild Semiconductor Corporation DS009787.prf www.fairchildsemi.com 74ACT323 Functional Description The ACT323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Mode Select Table Inputs SR L H H H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Response CP S1 X H L H L S0 X H H L L     X Synchronous Reset; Q0–Q7 = LOW Parallel Load; I/On→Qn Shift Right; DS0→Q0, Q0→Q1, etc. Shift Left; DS7→Q7, Q7→Q6, etc. Hold  www.fairchildsemi.com 2 74ACT323 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ACT323 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) ±50 mA −65°C to +150°C ±50 mA −20 mA +20 mA −0.5V to V CC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V Junction Temperature (TJ) PDIP 140°C Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT™ circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C DC Electrical Characteristics Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZT ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum I/O Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 ±0.1 ±0.3 0.6 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 Units Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH V V V 3.76 4.76 0.1 0.1 V V IOH = −24 mA IOH = −24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH 0.44 0.44 ±1.0 ±3.0 1.5 75 −75 V µA µA mA mA mA µA IOL = −24 mA IOL = −24 mA (Note 2) VI = VCC, GND VI/O = VCC or GND VIN = VIH, VIL VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND 5.5 5.5 5.5 5.5 5.5 5.5 4.0 40.0 www.fairchildsemi.com 4 74ACT323 AC Electrical Characteristics VCC Symbol fmax tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Propagation Delay CP to I/On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 3.5 3.5 4.0 3.0 7.5 7.5 8.5 8.0 11.0 11.5 12.5 11.5 3.0 3.0 3.0 2.5 12.5 13.0 13.5 12.5 ns ns ns ns 5.0 6.0 10.0 14.5 5.0 16.0 ns 5.0 5.0 8.5 12.5 4.5 14.5 ns 5.0 5.0 9.0 13.5 4.5 15.0 ns (V) (Note 4) 5.0 5.0 Min 120 5.0 T A = 2 5 °C CL = 50 pF Typ 125 9.0 12.5 Max TA = −40°C to +85°C CL = 50 pF Min 110 4.0 14.0 Max MHz ns Units Note 4: Voltage Range 5.0 is 5.0V ±0.5V AC Operating Requirements T A = 2 5 °C Symbol Parameter VCC (V) (Note 5) tS Setup Time, HIGH or LOW S0 or S1 to CP tH Hold Time, HIGH or LOW S0 or S1 to CP tS Setup Time, HIGH or LOW I/On, DS0, DS7 to CP tH Hold Time, HIGH or LOW I/On, DS0, DS 7 to CP tS Setup Time, HIGH or LOW SR to CP tH Hold Time, HIGH or LOW SR to CP tW CP Pulse Width HIGH or LOW Note 5: Voltage Range 5.0 is 5.0V ±0.5V TA = −40°C to +85°C CL = 50 pF VCC = +5.0V Guaranteed Minimum 5.0 5.0 ns Units CL = 50 pF VCC = +5.0V Typ 2.0 5.0 5.0 0 1.5 1.5 ns 5.0 1.0 4.0 4.5 ns 5.0 0 1.0 1.0 ns 5.0 1.0 2.5 2.5 ns 5.0 0 1.0 1.0 ns 5.0 2.0 4.0 4.5 ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 170 Units pF pF VCC = OPEN VCC = 5.0V Conditions 5 www.fairchildsemi.com 74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.