74ALVCH2245

74ALVCH2245 Low Voltage Bidirectional Transceiver with Bushold January 2002 Revised January 2002 74ALVCH2245 Low Voltage Bidirectional Transceiver with Bushold and 26Ω Series Resistors in B Outputs General Description The ALVCH2245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The T/R input determines the direction of data flow. The OE input disables both the A and B Ports by placing them in a high impedance state. The ALVCH2245 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH2245 is designed for low voltage (1.65V to 3.6V) VCC applications. The ALVCH2245 is also designed with 26Ω series resistance in the B Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers transmitters The 74ALVCH2245 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s 26Ω series resistors in B Port outputs s tPD (A to B) 4.9 ns max for 3.0V to 3.6V VCC 6.1 ns max for 2.3V to 2.7V VCC 9.8 ns max for 1.65V to 1.95V VCC s Uses patented Quiet Series noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74ALVCH2245WM 74ALVCH2245MTC Package Number M20B MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Quiet Series is a trademark of Fairchild Semiconductor Corporation. © 2002 Fairchild Semiconductor Corporation ds500716 www.fairchildsemi.com 74ALVCH2245 Pin Descriptions Pin Names OE T/R A0–A7 B0–B7 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Bushold Inputs or 3-STATE Outputs Side B Bushold Inputs or 3-STATE Outputs Truth Table Inputs Outputs OE L L H T/R L H X Bus B0–B7 Data to Bus A0–A7 Bus A0–A7 Data to Bus B0–B7 HIGH Z State on A0–A7, B0–B7 H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram www.fairchildsemi.com 2 74ALVCH2245 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG) −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions (Note 3) Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Floating or unused control inputs must be held HIGH or LOW. 1.65V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage A Outputs IOH = −100 µA IOH = −4 mA IOH = −6 mA IOH = −12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = −24 mA HIGH Level Output Voltage B Outputs IOH = −100 µA IOH = −2 mA IOH = −4 mA IOH = −6 mA IOH = −8 mA IOH = −12 mA VOL LOW Level Output Voltage A Outputs IOL = 100 µA IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA LOW Level Output Voltage B Outputs IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II Input Leakage Current 0 ≤ VI ≤ 3.6V 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 - 3.6 VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 VCC - 0.2 1.2 1.9 1.7 2.4 2 2 0.2 0.45 0.4 0.7 0.4 0.55 0.2 0.45 0.4 0.55 0.55 0.6 0.8 ±5.0 µA V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units 3 www.fairchildsemi.com 74ALVCH2245 DC Electrical Characteristics Symbol II(HOLD) Parameter Bushold Input Maximum Drive Hold Current (Continued) VCC (V) 1.65 1.65 2.3 2.3 3.0 3.0 3.6 1.65 - 3.6 3.6 2.7 - 3.6 Conditions VIN = 0.58V VIN = 1.07V VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V 0 < VO ≤ 3.6V Min 25 −25 45 −45 75 −75 Max Units µA ±500 ±10 40 750 µA µA µA IOZ ICC ∆ICC 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 ≤ VO ≤ 3.6V, VI = VIH or VIL VI = VCC or GND, IO = 0 VIH = VCC − 0.6V AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter CL = 50 pF VCC = 3.3V ± 0.3V Min tPHL, tPLH Propagation Delay 1.1 A to B ns Propagation Delay 1.1 B to A tPZL, tPZH Output Enable Time 1.1 A to B ns Output Enable Time 1.1 B to A tPLZ, tPHZ Output Disable Time 1.1 A to B ns Output Disable Time 1.1 B to A 4.1 1.3 4.5 0.8 4.0 1.5 7.2 4.7 1.3 5.2 0.8 4.7 1.5 8.5 5.0 1.3 6.1 0.8 5.6 1.5 9.8 5.5 1.3 7.1 0.8 6.6 1.5 9.8 4.0 1.3 4.7 0.8 4.2 1.5 8.4 4.9 1.3 6.1 0.8 5.6 1.5 9.8 Max VCC = 2.7V Min Max CL = 30 pF VCC = 2.5 ± 0.2V Min Max VCC = 1.8V ± 0.15V Min Max Units Capacitance Symbol CIN CIO CPD Input Capacitance Input, Output Capacitance Power Dissipation Capacitance Parameter Conditions VI = 0V or VCC VO = 0V or VCC Outputs Enabled f = 10 MHz, CL = 50 pF TA = +25°C VCC 3.3 3.3 3.3 2.5 Typical 6 7 20 20 Units pF pF pF www.fairchildsemi.com 4 74ALVCH2245 AC Loading and Waveforms TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; ZO = 50Ω) Symbol Vmi Vmo VX VY VL VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V 2.5 ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC*2 1.8V ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC*2 FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic 5 www.fairchildsemi.com 74ALVCH2245 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74ALVCH2245 Low Voltage Bidirectional Transceiver with Bushold Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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