FST3245MTCX

FST3245 — 8-Bit Bus Switch March 2008 FST3245 — 8-Bit Bus Switch Features 4Ω Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low ICC Zero Bounce in Flow-through Mode Control Inputs Compatible with TTL Level Description The FST3245 switch provides eight-bits of high-speed CMOS TTL-compatible bus switching in a standard ’245 pin-out. The low on resistance allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The device is organized as an eight-bit switch. When /OE is LOW, the switch is ON and port A is connected to port B. When /OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. Ordering Information Part Number FST3245WMX FST3245QSC FST3245QSCX FST3245MTC FST3245MTCX Operating Temperature Range -40 to +85°C -40 to +85°C -40 to +85°C -40 to +85°C -40 to +85°C Package 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150-inch Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150-inch Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Packing Method Tape and Reel Tube Tape and Reel Tube Tape and Reel All packages are lead free per JEDEC: J-STD-020B standard. The Fairchild switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product. Logic Diagram A0 2 1 8 B0 A7 9 11 B 7 /OE 19 Figure 1. Logic Diagram ©1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com FST3245 — 8-Bit Bus Switch Pin Configuration NC A0 A1 1 2 3 4 5 6 20 19 18 17 16 15 VCC /OE B0 B1 B2 B3 B4 B5 B6 B7 A2 A3 A4 A5 A6 A7 GND 7 8 9 10 14 13 12 11 Figure 2. Pin Configuration Pin Descriptions Pin # 1 19 2,3,4,5,6,7,8,9 10 11,12,13,14,15,16,17,18 20 Pin Names NC /OE A0,A1,A2,A3,A4,A5,A6,A7 GND B7,B6,B5,B4,B3,B2,B1,B0 VCC Description No Connnect Bus Switch Enable Bus A Ground Bus B Supply Voltage Truth Table Input /OE LOW HIGH Function Connect Disconnect © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 2 FST3245 — 8-Bit Bus Switch Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VS VIN IIK IOUT ICC / IGND TSTG Supply Voltage DC Switch Voltage DC Input Voltage (1) Parameter Min. -0.5 -0.5 -0.5 Max. 7.0 7.0 7.0 -50 128 ±100 Unit V V V mA mA mA °C DC Input Diode Current, VIN < 0V DC Output Sink Current DC VCC / GND Current Storage Temperature Range -65 +150 Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VOUT tr , tf TA Input Voltage Output Voltage Parameter Power Supply Operating Min. 4.0 0 0 Max. 5.5 5.5 5.5 5 DC +85 Unit V V V ns/V °C Input Rise and Fall Time Switch Control Input Switch I/O (2) 0 0 -40 Operating Temperature, Free Air Note: 2. Unused control inputs must be held HIGH or LOW. They may not float. © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 3 FST3245 — 8-Bit Bus Switch DC Electrical Characteristics Typical values are at VCC = 5.0V and TA = 25°C. Symbol VIK VIH VIL IIN IOZ Parameter Clamp Diode Voltage High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Off-state Leakage Current Conditions IIN = -18mA VCC (V) 4.5 4.0 to 5.5 4.0 to 5.5 TA=-40 to +85°C Min. 2.0 0.8 ±1.0 ±1.0 4 4 8 11 7 7 15 20 3 2.5 Units V V V µA µA Typ. Max. -1.2 0 ≤ VIN ≤ 5.5V 0 ≤ A, B ≤ VCC VIN = 0V, IIN = 64mA 5.5 5.5 4.5 4.5 4.5 4.0 5.5 5.5 RON Switch On Resistance (3) VIN = 0V, IIN = 30mA VIN = 2.4V, IIN = 15mA VIN = 2.4V, IIN = 15mA VIN = VCC or GND, IOUT = 0 One Input at 3.4V, Other Inputs at VCC or GND Ω ICC ΔICC Quiescent Supply Current Increase in ICC per Input µA mA Note: 3. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the A or B pins. AC Electrical Characteristics TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω. Symbol tPHL, tPLH Parameter Propagation Delay (4) Bus-to-Bus Output Enable Time Conditions VIN = Open VIN = 7V for tPZL VIN = Open for tPZH VIN = 7V for tPLZ VIN = Open for tPHZ VCC = 4.5 – 5.5V Min. Max. 0.25 VCC = 4.0V Min. Max. 0.25 Units ns Figure Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 tPZH ,tPZL 1.5 5.9 6.4 ns tPHZ, tPLZ Output Disable Time 1.5 6.0 5.7 ns Note: 4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by an ideal voltage source (zero output impedance). Capacitance TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested. Symbol CIN CI/O Parameter Control Pin Input Capacitance Input/Output Capacitance Conditions VCC = 5.0V VCC, /OE = 5.0V Typ. 3 5 Units pF pF © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 4 FST3245 — 8-Bit Bus Switch AC Loadings and Waveforms Notes: Input driven by 50Ω source terminated in 50Ω. CL includes load and stray capacitance. Input PRR = 1.0MHz, tw = 500ns. Figure 3. AC Test Circuit Figure 4. AC Waveforms © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 5 FST3245 — 8-Bit Bus Switch Physical Dimensions 13.00 12.60 11.43 20 B 11 A 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 0.51 0.35 0.25 M 10 1.27 CBA 1.27 0.65 LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A C 0.33 0.20 0.10 C SEATING PLANE 0.75 0.25 (R0.10) (R0.10) 8° 0° X 45° 0.30 0.10 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE 0.25 1.27 0.40 (1.40) A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3 SEATING PLANE DETAIL A SCALE: 2:1 Figure 5. 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 6 FST3245 — 8-Bit Bus Switch Physical Dimensions TOP VIEW LAND PATTERN RECOMMENDATION SIDE VIEW END VIEW DETAIL A Figure 6. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150-inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 7 FST3245 — 8-Bit Bus Switch Physical Dimensions Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 8 FST3245 — 8-Bit Bus Switch © 1997 Fairchild Semiconductor Corporation FST3245 • Rev. 1.0.2 www.fairchildsemi.com 9