SCAN18245T

SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs October 1991 Revised May 2000 SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs General Description The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundaryscan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Features s IEEE 1149.1 (JTAG) Compliant s Dual output enable control signals s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP (Shrink Small Outline Package) s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products Ordering Code: Order Number SCAN18245TSSC Package Number MS56A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names A1(0–8) B1(0–8) A2(0–8) B2(0–8) G1, G2 DIR1, DIR2 Description Side A1 Inputs or 3-STATE Outputs Side B1 Inputs or 3-STATE Outputs Side A2 Inputs or 3-STATE Outputs Side B2 Inputs or 3-STATE Outputs Output Enable Pins Direction of Data Flow Pins © 2000 Fairchild Semiconductor Corporation DS010961 www.fairchildsemi.com SCAN18245T Truth Table Inputs A1 (0–8) G1 L L L L H H= HIGH Voltage Level L= LOW Voltage Level Inputs B1 (0–8) G2 H L H L Z DIR2 L L H H X H L H L Z A2 (0–8) L L L L H X= Immaterial Z= High Impedance B2 (0–8) DIR1 L L H H X ← ← → → H L H L Z ← ← → → H L H L Z Functional Description The SCAN18245 consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B Ports to A Ports, when HIGH enables data from A Ports to B Ports. The Output Enable pins (G1 and G2) when HIGH disables both A and B Ports by placing them in a high impedance condition. Block Diagrams A1, B1, G1 and DIR1 A2, B2, G2 and DIR2 Note: BSR stands for Boundary Scan Register. Note: BSR stands for Boundary Scan Register. Tap Controller www.fairchildsemi.com 2 SCAN18245T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10–11 for a further description of scan cell TYPE1 and Figure 10–12 for a further description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18245T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition MSB → LSB Instruction Code 00000000 10000001 10000010 00000011 All Others Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGHZ BYPASS The INSTRUCTION register is an eight-bit register which captures the value 00111101. Scan Cell TYPE1 Scan Cell TYPE2 3 www.fairchildsemi.com SCAN18245T Boundary-Scan Register Scan Chain Definition (80 Bits in Length) www.fairchildsemi.com 4 SCAN18245T Boundary-Scan Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 DIR1 G1 AOE1 BOE1 DIR2 G2 AOE2 BOE2 A10 A11 A12 A13 A14 A15 A16 A17 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 B10 B11 B12 B13 B14 B15 B16 B17 B18 B20 B21 B22 B23 B24 B25 B26 B27 B28 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 26 31 3 54 Input Input Internal Internal Input Input Internal Internal Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output TYPE1 TYPE1 TYPE2 TYPE2 Control TYPE1 Signals TYPE1 TYPE2 TYPE2 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B1–out TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B2–out TYPE2 TYPE2 TYPE2 TYPE2 A2–in A1–in Bit No. Pin Name Pin No. Pin Type Scan Cell Type 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B10 B11 B12 B13 B14 B15 B16 B17 B18 B20 B21 B22 B23 B24 B25 B26 B27 B28 A10 A11 A12 A13 A14 A15 A16 A17 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 A1–out TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 A2–out TYPE2 TYPE2 TYPE2 TYPE2 B2–in B1–in 5 www.fairchildsemi.com SCAN18245T Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Junction Temperature SSOP Storage Temperature ESD (Min) −0.5V to +7.0V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC +0.5V ±70 mA ±70 mA +140 °C −65°C to +150 °C 2000V Recommended Operating Conditions Supply Voltage (VCC) SCAN Products Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage (Note 2) VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage (Note 2) 4.5 5.5 4.5 5.5 4.5 5.5 IIN IIN TDI, TMS Minimum Input Leakage IOLD IOHD IOZT Minimum Dynamic Output Current (Note 3) Maximum I/O Leakage Current IOS ICC Output Short Circuit Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 ±0.6 −100 16.0 750 ±6.0 −100 88 820 µA 5.5 5.5 Maximum Input Leakage Current Maximum Input Leakage 5.5 5.5 TA = +25°C Typ 1.5 1.5 1.5 1.5 2.0 2.0 0.8 0.8 3.15 4.15 2.4 2.4 2.4 2.4 0.1 0.1 0.55 0.55 0.55 0.55 ±0.1 2.8 −385 −160 94 −40 ±1.0 3.6 −385 −160 94 −40 0.1 0.1 0.55 0.55 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 3.15 4.15 2.4 2.4 Units V V V V V V V V µA µA µA µA mA mA Conditions VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH IOH = −32 mA VIN = VIL or VIH IOH = −24 mA IOUT = 50 µA VIN = VIL or VIH IOL = 64 mA VIN = VIL or VIH IOL = 48 mA VI = VCC, GND VI = VCC VI = GND VI = GND VOLD = 0.8V Max VOHD = 2.0V Min VI (OE) = VIL, VIHVI = VCC, GND VO = VCC, GND mA (min) VO = 0V µA µA VO = HIGH TDI, TMS = VCC VO = HIGH TDI, TMS = GND www.fairchildsemi.com 6 SCAN18245T DC Electrical Characteristics Symbol ICCt Parameter Maximum ICC Per Input VCC (V) 5.5 5.5 (Continued) TA = +25°C Typ 2.0 2.15 TA = −40°C to +85°C Guaranteed Limits 2.0 2.15 mA mA VI = VCC–2.1V VI = VCC–2.1V TDI/TMS Pin, test one with the other floating Units Conditions Note 2: All outputs loaded; thresholds associated with output under test. Note 3: M aximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Symbol VOLP VOLV VOHP VOHV VIHD VILD Parameter Maximum HIGH Output Noise (Note 5)(Note 6) Minimum LOW Output Noise (Note 5)(Note 6) Maximum Overshoot (Note 4)(Note 6) Minimum VCC Droop (Note 4)(Note 6) Minimum HIGH Dynamic Input Voltage Level (Note 4)(Note 7) Maximum LOW Dynamic Input Voltage Level (Note 4)(Note 7) Note 4: Worst case package. Note 5: M aximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 6: M aximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. Note 7: M aximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). VCC (V) 5.0 5.0 5.0 5.0 5.5 5.5 Typ 1.0 −0.6 VOH+1.0 VOH−1.0 1.6 1.4 TA = +25°C TA = −40°C to +85°C Guaranteed Limits 1.5 −1.2 VOH+1.5 VOH−1.8 2.0 0.8 2.0 0.8 Units V V V V V V AC Electrical Characteristics Normal Operation VCC Symbol Parameter (V) (Note 8) tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. TA = +25°C CL = 50 pF Min 1.6 1.6 1.2 1.2 1.6 1.6 Typ Max 7.9 7.9 8.6 8.5 11.0 8.5 TA=−40°C to +85°C CL = 50 pF Min 1.6 1.6 1.2 1.2 1.6 1.6 Max 8.5 8.8 9.5 9.0 12.0 9.5 ns ns ns Units Propagation Delay A to B, B to A Disable Time Enable Time 5.0 5.0 5.0 7 www.fairchildsemi.com SCAN18245T AC Electrical Characteristics Scan Test Operation VCC Symbol Parameter (V) (Note 9) tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tPLH, tPHL tPLH, tPHL tPLH, tPHL Propagation Delay TCK to TDO Disable Time TCK to TDO Enable Time TCK to TDO Propagation Delay TCK to Data Out During Update-DR State Propagation Delay TCK to Data Out During Update-IR State Propagation Delay TCK to Data Out During Test Logic Reset State tPLZ, tPHZ tPLZ, tPHZ tPLZ, tPHZ Propagation Delay TCK to Data Out During Update-DR State Propagation Delay TCK to Data Out During Update-IR State Propagation Delay TCK to Data Out During Test Logic Reset State tPZL, tPZH tPZL, tPZH tPZL, tPZH Propagation Delay TCK to Data Out During Update-DR State Propagation Delay TCK to Data Out During Update-IR State Propagation Delay TCK to Data Out During Test Logic Reset State Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note: All Propagation Delays involving TCK are measured from the falling edge of TCK. TA = +25°C CL = 50 pF Min 2.8 2.8 2.0 2.0 2.4 2.4 4.0 4.0 4.0 Typ Max 13.2 13.2 11.5 11.5 14.5 14.5 18.0 18.0 18.6 18.6 19.9 19.9 TA=−40°C to +85°C CL = 50 pF Min 2.8 2.8 2.0 2.0 2.4 2.4 4.0 4.0 4.0 4.0 4.4 4.4 Max 14.5 14.5 11.9 11.9 15.8 15.8 19.8 19.8 20.2 20.2 21.5 21.5 ns ns ns ns Units 5.0 5.0 5.0 5.0 5.0 5.0 4.0 4.4 4.4 ns ns 5.0 3.2 3.2 16.4 16.4 18.0 18.0 18.4 18.4 3.2 3.2 2.8 2.8 2.8 2.8 18.2 18.2 19.3 19.3 20.0 20.0 ns 5.0 2.8 2.8 ns 5.0 2.8 2.8 ns 5.0 4.0 4.0 18.9 18.9 19.9 19.9 21.3 21.3 4.0 4.0 3.2 3.2 3.6 3.6 20.9 20.9 21.7 21.7 23.3 23.3 ns 5.0 3.2 3.2 ns 5.0 3.6 3.6 ns www.fairchildsemi.com 8 SCAN18245T AC Operating Requirements Scan Test Operation VCC Symbol Parameter (V) (Note 10) tS tH tS tH tS tH tS Setup Time, H or L Data to TCK (Note 11) Hold Time, H or L TCK to Data (Note 11) Setup Time, H or L G1, G2 to TCK (Note 12) Hold Time, H or L TCK to G1, G2 (Note 12) Setup Time, H or L DIR1, DIR2 to TCK (Note 13) Hold Time, H or L TCK to DIR1, DIR2 (Note 13) Setup Time, H or L Internal AOEn, BOEn to TCK (Note 14) tH Hold Time, H or L TCK to Internal AOEn, BOEn (Note 14) tS tH tS tH tW Setup Time, H or L TMS to TCK Hold Time, H or L TCK to TMS Setup Time, H or L TDI to TCK Hold Time, H or L TCK to TDI Pulse Width H L fMAX TPU TDN Maximum TCK Clock Frequency Wait Time, Power Up to TCK Power Down Delay Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. Note 11: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71). Note 12: Timing pertains to BSR 74 and 78 only. Note 13: Timing pertains to BSR 75 and 79 only. Note 14: Timing pertains to BSR 72, 73, 76 and 77 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units Guaranteed Minimum 0.0 6.5 0.0 4.0 0.0 4.0 0.0 6.5 0.0 4.0 0.0 4.0 ns ns ns ns ns ns 5.0 5.0 5.0 5.0 5.0 5.0 5.0 1.0 1.0 ns 5.0 4.0 4.0 ns 5.0 5.0 5.0 5.0 5.0 7.0 2.0 1.0 3.5 7.0 2.0 1.0 3.5 ns ns ns ns 15.0 5.0 5.0 5.0 0.0 25 100 100 15.0 5.0 25 100 100 ns MHz ns ms 9 www.fairchildsemi.com SCAN18245T Extended AC Electrical Characteristics TA = +25°C, VCC = 5.0V CL = 50 pF Symbol Parameter 18 Outputs Switching (Note 15) Min tPLH, tPHL tPZH, tPZL tPHZ, tPLZ tOSHL (Note 19) tOSLH (Note 19) Pin to Pin Skew HL Data to Output Pin to Pin Skew LH data to Output Output Disable Time Propagation Delay Data to Output Output Enable Time 2.5 2.5 2.5 2.5 2.0 2.0 0.5 0.5 Typ Max 10.5 10.5 10.5 13.5 9.5 10.0 1.0 1.0 3.5 3.5 TA = −40°C to +85°C VCC = 5.0V ± 0.5V CL = 250 pF (Note 16) Min Max 12.0 13.5 (Note 17) (Note 18) 1.0 1.0 ns ns ns ns ns Units Note 15: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) Note 16: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 17: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 18: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 19: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW. Capacitance Symbol CIN CI/O CPD Parameter Input Pin Capacitance Input/Output Capacitance Power Dissipation Capacitance Typ 4 20 41 Units pF pF pF VCC = 5.0V VCC = 5.0V VCC = 5.0V Conditions www.fairchildsemi.com 10 SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com