68HC705SB7

HC05SB7GRS/H REV 2.1 68HC05SB7 68HC705SB7 SPECIFICATION (General Release) August 27, 1998 Consumer Systems Group Semiconductor Products Sector Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. © Motorola, Inc., 1998 August 27, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS Section SECTION 1 GENERAL DESCRIPTION 1.1 FEATURES ...................................................................................................... 1-1 1.2 MASK OPTION ................................................................................................ 1-2 1.3 PEPROM FACTORY PREPROGRAMMED OPTIONS ................................... 1-2 1.4 MCU STRUCTURE.......................................................................................... 1-2 1.5 PIN ASSIGNMENTS ........................................................................................ 1-4 1.6 FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4 1.6.1 VDD, VSS .................................................................................................... 1-4 1.6.2 OSC1, OSC2 ............................................................................................... 1-4 1.6.3 IRQ/VPP ...................................................................................................... 1-5 1.6.4 RESET ......................................................................................................... 1-6 1.6.5 CSA ............................................................................................................. 1-6 1.6.6 TM................................................................................................................ 1-6 1.6.7 VM ............................................................................................................... 1-6 1.6.8 CAP (ADC) .................................................................................................. 1-6 1.6.9 ESV.............................................................................................................. 1-7 1.6.10 PA0-PA7 / PWM0-PWM3, SCL0-SCL1, SDA0-SDA1 ................................. 1-7 1.6.11 PB1-PB7 / TCAP, CS0-CS1, AN0-AN3 ....................................................... 1-7 1.6.12 PC4-PC7...................................................................................................... 1-7 SECTION 2 MEMORY 2.1 2.2 2.3 2.4 2.5 MEMORY MAP ................................................................................................ 2-1 INPUT/OUTPUT SECTION.............................................................................. 2-2 INTERRUPT VECTOR MAPPING ................................................................... 2-6 ROM................................................................................................................. 2-6 RAM ................................................................................................................. 2-6 SECTION 3 CENTRAL PROCESSING UNIT 3.1 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 REGISTERS .................................................................................................... 3-1 ACCUMULATOR (A)........................................................................................ 3-2 INDEX REGISTER (X) ..................................................................................... 3-2 STACK POINTER (SP) .................................................................................... 3-2 PROGRAM COUNTER (PC) ........................................................................... 3-2 CONDITION CODE REGISTER (CCR) ........................................................... 3-3 Half Carry Bit (H-Bit) .................................................................................... 3-3 Interrupt Mask (I-Bit) .................................................................................... 3-3 Negative Bit (N-Bit) ...................................................................................... 3-3 Zero Bit (Z-Bit) ............................................................................................. 3-3 Carry/Borrow Bit (C-Bit) ............................................................................... 3-4 MOTOROLA i Page MC68HC05SB7 REV 2.1 GENERAL RELEASE SPECIFICATION August 27, 1998 TABLE OF CONTENTS Section SECTION 4 INTERRUPTS 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.6.3 4.7 4.8 4.8.1 4.8.2 4.9 INTERRUPT VECTORS .................................................................................. 4-1 INTERRUPT PROCESSING............................................................................ 4-2 SOFTWARE INTERRUPT ............................................................................... 4-4 EXTERNAL INTERRUPT................................................................................. 4-4 IRQ/VPP Pin ................................................................................................ 4-4 IRQ Status and Control Register (ISCR) ..................................................... 4-5 CORE TIMER INTERRUPTS........................................................................... 4-6 Core Timer Overflow Interrupt ..................................................................... 4-7 Real-Time Interrupt...................................................................................... 4-7 PROGRAMMABLE TIMER INTERRUPTS ...................................................... 4-7 Input Capture Interrupt................................................................................. 4-7 Output Compare Interrupt............................................................................ 4-7 Timer Overflow Interrupt .............................................................................. 4-7 SM-BUS INTERRUPT...................................................................................... 4-8 ANALOG INTERRUPTS .................................................................................. 4-8 Comparator Input Match Interrupt................................................................ 4-8 Input Capture Interrupt................................................................................. 4-8 CURRENT DETECT INTERRUPT................................................................... 4-8 SECTION 5 RESETS 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 POWER-ON RESET ........................................................................................ 5-2 EXTERNAL RESET ......................................................................................... 5-2 INTERNAL RESETS ........................................................................................ 5-2 Power-On Reset (POR) ............................................................................... 5-2 Computer Operating Properly (COP) Reset ................................................ 5-3 Low Voltage Reset (LVR) ............................................................................ 5-4 Illegal Address Reset................................................................................... 5-4 RESET STATES .............................................................................................. 5-4 CPU ............................................................................................................. 5-4 I/O Registers................................................................................................ 5-4 Core Timer................................................................................................... 5-5 COP Watchdog............................................................................................ 5-5 16-Bit Programmable Timer......................................................................... 5-5 SM-Bus Serial Interface............................................................................... 5-5 Analog Subsystem....................................................................................... 5-6 SECTION 6 LOW POWER MODES 6.1 6.2 STOP MODE.................................................................................................... 6-3 WAIT MODE .................................................................................................... 6-4 MC68HC05SB7 REV 2.1 Page MOTOROLA ii August 27, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS Section 6.3 6.4 Page DATA-RETENTION MODE.............................................................................. 6-4 SLOW MODE................................................................................................... 6-5 SECTION 7 INPUT/OUTPUT PORTS 7.1 7.1.1 7.1.2 7.2 7.3 7.4 PARALLEL PORTS.......................................................................................... 7-1 Port Data Registers ..................................................................................... 7-2 Port Data Direction Registers ...................................................................... 7-2 PORT A............................................................................................................ 7-2 PORT B............................................................................................................ 7-2 PORT C............................................................................................................ 7-2 SECTION 8 SYSTEM CLOCK 8.1 CLOCK SOURCES .......................................................................................... 8-1 8.2 VCO CLOCK SPEED....................................................................................... 8-2 8.2.1 VCO Slow Mode .......................................................................................... 8-2 8.2.2 Setting the VCO Speed ............................................................................... 8-3 SECTION 9 CORE TIMER 9.1 9.2 9.3 9.4 9.5 CORE TIMER STATUS AND CONTROL REGISTER..................................... 9-2 CORE TIMER COUNTER REGISTER (CTCR) ............................................... 9-3 COP WATCHDOG ........................................................................................... 9-4 CORE TIMER DURING WAIT MODE.............................................................. 9-5 CORE TIMER DURING STOP MODE............................................................. 9-5 SECTION 10 16-BIT TIMER 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 TIMER REGISTERS (TMRH, TMRL)............................................................. 10-2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) ................................ 10-4 INPUT CAPTURE REGISTERS .................................................................... 10-5 OUTPUT COMPARE REGISTERS ............................................................... 10-7 TIMER CONTROL REGISTER (TCR) ........................................................... 10-9 TIMER STATUS REGISTER (TSR)............................................................. 10-10 TIMER OPERATION DURING WAIT MODE............................................... 10-11 TIMER OPERATION DURING STOP MODE .............................................. 10-11 SECTION 11 PULSE WIDTH MODULATOR 11.1 11.2 11.3 11.4 D/A DATA REGISTERS (DAC0-DAC3) ......................................................... 11-2 MUX CHANNEL ENABLE REGISTER (MCER) ............................................ 11-3 PWM DURING WAIT MODE ......................................................................... 11-4 PWM DURING STOP MODE......................................................................... 11-4 MOTOROLA iii MC68HC05SB7 REV 2.1 GENERAL RELEASE SPECIFICATION August 27, 1998 TABLE OF CONTENTS Section SECTION 12 SM-BUS 12.1 SM-BUS INTRODUCTION............................................................................. 12-1 12.2 SM-BUS INTERFACE FEATURES................................................................ 12-1 12.3 SM-BUS SYSTEM CONFIGURATION .......................................................... 12-2 12.4 SM-BUS PROTOCOL .................................................................................... 12-2 12.4.1 START Signal ............................................................................................ 12-3 12.4.2 Slave Address Transmission ..................................................................... 12-3 12.4.3 Data Transfer............................................................................................. 12-3 12.4.4 Repeated START Signal ........................................................................... 12-4 12.4.5 STOP Signal .............................................................................................. 12-4 12.4.6 Arbitration Procedure................................................................................. 12-4 12.4.7 Clock Synchronization ............................................................................... 12-5 12.4.8 Handshaking.............................................................................................. 12-5 12.5 SM-BUS REGISTERS ................................................................................... 12-5 12.5.1 SM-Bus Address Register (SMADR) ......................................................... 12-6 12.5.2 SM-Bus Frequency Divider Register (SMFDR) ......................................... 12-6 12.5.3 SM-Bus Control Register (SMCR) ............................................................. 12-7 12.5.4 SM-Bus Status Register (SMSR)............................................................... 12-8 12.5.5 SM-Bus Data I/O Register (SMDR) ......................................................... 12-10 12.5.6 SM-Bus logic Level .................................................................................. 12-10 12.5.7 SCL as16-bit Timer Input Capture ........................................................... 12-10 12.6 PROGRAMMING CONSIDERATIONS........................................................ 12-11 12.6.1 Initialization .............................................................................................. 12-11 12.6.2 Generation of a START Signal and the First Byte of Data Transfer ........ 12-11 12.6.3 Software Responses after Transmission or Reception of a Byte ............ 12-11 12.6.4 Generation of the STOP Signal ............................................................... 12-13 12.6.5 Generation of a Repeated START Signal................................................ 12-14 12.6.6 Slave Mode.............................................................................................. 12-14 12.6.7 Arbitration Lost......................................................................................... 12-14 12.7 OPERATION DURING WAIT MODE ........................................................... 12-14 12.8 OPERATION DURING STOP MODE .......................................................... 12-14 SECTION 13 CURRENT SENSE AMPLIFIER 13.1 13.2 13.3 13.4 13.5 CURRENT SENSE AMPLIFIER APPLICATION............................................ 13-1 CURRENT SENSE INTERRUPT................................................................... 13-2 CSA STATUS AND CONTROL REGISTER (CSSCR) .................................. 13-2 CSA OPERATION DURING WAIT MODE..................................................... 13-4 CSA OPERATION DURING STOP MODE.................................................... 13-4 Page MOTOROLA iv MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS Section SECTION 14 TEMPERATURE SENSOR 14.1 14.2 14.3 14.4 INTERNAL TEMPERATURE SENSOR ......................................................... 14-1 EXTERNAL TEMPERATURE SENSOR........................................................ 14-2 TEMPERATURE SENSOR OPERATION DURING WAIT MODE................. 14-2 TEMPERATURE SENSOR OPERATION DURING STOP MODE................ 14-2 SECTION 15 ANALOG SUBSYSTEM 15.1 ANALOG MULTIPLEX REGISTERS ............................................................. 15-3 15.2 ANALOG CONTROL REGISTER ................................................................ 15-14 15.3 ANALOG STATUS REGISTER.................................................................... 15-17 15.4 A/D CONVERSION METHODS ................................................................... 15-19 15.5 VOLTAGE MEASUREMENT METHODS .................................................... 15-27 15.5.1 Absolute Voltage Readings ..................................................................... 15-27 15.5.2 Ratiometric Voltage Readings ................................................................. 15-28 15.6 VOLTAGE COMPARATOR FEATURES ..................................................... 15-29 15.7 CURRENT SOURCE FEATURES ............................................................... 15-30 15.8 SAMPLE AND HOLD ................................................................................... 15-30 15.9 PORT B INTERACTION WITH ANALOG INPUTS ...................................... 15-30 15.9.1 Port B Pins As Inputs............................................................................... 15-31 15.10 NOISE SENSITIVITY ............................................................................................................ 15-31 SECTION 16 PERSONALITY EPROM 16.1 PEPROM REGISTERS.................................................................................. 16-2 16.1.1 PEPROM Bit Select Register (PEBSR) ..................................................... 16-2 16.1.2 PEPROM Status and Control Register (PESCR) ...................................... 16-2 16.2 PEPROM PROGRAMMING........................................................................... 16-3 16.3 PEPROM READING ...................................................................................... 16-4 16.4 PEPROM ERASING ...................................................................................... 16-4 16.5 PEPROM PREPROGRAMMED OPTIONS ................................................... 16-5 16.5.1 Data Format in Preprogrammed PEPROM ............................................... 16-5 SECTION 17 INSTRUCTION SET 17.1 ADDRESSING MODES ................................................................................. 17-1 17.1.1 Inherent...................................................................................................... 17-1 17.1.2 Immediate .................................................................................................. 17-1 17.1.3 Direct ......................................................................................................... 17-2 17.1.4 Extended.................................................................................................... 17-2 17.1.5 Indexed, No Offset..................................................................................... 17-2 17.1.6 Indexed, 8-Bit Offset .................................................................................. 17-2 MC68HC05SB7 REV 2.1 MOTOROLA v Page GENERAL RELEASE SPECIFICATION August 27, 1998 TABLE OF CONTENTS Section 17.1.7 17.1.8 17.1.9 17.1.10 17.1.11 17.1.12 17.1.13 17.1.14 17.1.15 Page Indexed, 16-Bit Offset ................................................................................ 17-3 Relative...................................................................................................... 17-3 Instruction Types ....................................................................................... 17-3 Register/Memory Instructions .................................................................... 17-4 Read-Modify-Write Instructions ................................................................. 17-5 Jump/Branch Instructions .......................................................................... 17-5 Bit Manipulation Instructions...................................................................... 17-7 Control Instructions.................................................................................... 17-7 Instruction Set Summary ........................................................................... 17-8 SECTION 18 ELECTRICAL SPECIFICATIONS 18.1 MAXIMUM RATINGS..................................................................................... 18-1 18.2 OPERATING TEMPERATURE RANGE ........................................................ 18-1 18.3 THERMAL CHARACTERISTICS ................................................................... 18-1 18.4 SUPPLY CURRENT CHARACTERISTICS ................................................... 18-2 18.5 PEPROM PROGRAMMING CHARACTERISTICS........................................ 18-2 18.6 DC ELECTRICAL CHARACTERISTICS........................................................ 18-3 18.7 ANALOG SUBSYSTEM CHARACTERISTICS .............................................. 18-4 18.8 CONTROL TIMING ........................................................................................ 18-5 18.9 RESET CHARACTERISTICS ........................................................................ 18-6 18.10 SM-BUS DC ELECTRICAL CHARACTERISTICS......................................... 18-8 18.11 SM-BUS CONTROL TIMING ......................................................................... 18-8 18.11.1 SM-Bus Interface Input Signal Timing ....................................................... 18-8 18.11.2 SM-Bus Interface Output Signal Timing .................................................... 18-8 SECTION 19 MECHANICAL SPECIFICATIONS 19.1 19.2 28-PIN SOIC (CASE 751F)............................................................................ 19-1 28-PIN SSOP ................................................................................................. 19-2 APPENDIX A MC68HC705SB7 A.1 A.2 A.3 A.4 A.5 A.6 A.6.1 A.6.2 A.7 A.8 INTRODUCTION..............................................................................................A-1 MEMORY .........................................................................................................A-1 PERSONALITY EPROM (PEPROM)...............................................................A-2 MASK OPTION REGISTER.............................................................................A-2 BOOTLOADER MODE ....................................................................................A-3 EPROM PROGRAMMING ...............................................................................A-3 EPROM Programming Register (EPROG) ..................................................A-3 Programming Sequence ..............................................................................A-4 EPROM ERASING...........................................................................................A-5 EPROM PROGRAMMING SPECIFICATIONS ................................................A-6 MC68HC05SB7 REV 2.1 MOTOROLA vi August 27, 1998 GENERAL RELEASE SPECIFICATION LIST OF FIGURES Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 4-1 4-2 4-3 4-4 5-1 5-2 5-3 6-1 6-2 7-1 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Title Page MC68HC05SB7 Block Diagram ....................................................................... 1-3 MC68HC05SB7 Pin Assignments.................................................................... 1-4 EPO Oscillator Connections............................................................................. 1-5 MC68HC05SB7 Memory Map.......................................................................... 2-1 MC68HC05SB7 I/O Registers.......................................................................... 2-2 MC68HC05SB7 I/O Registers $0000-$000F ................................................... 2-3 MC68HC05SB7 I/O Registers $0010-$001F ................................................... 2-4 MC68HC05SB7 I/O Registers $0020-$002F ................................................... 2-5 COP Register (COPR) ..................................................................................... 2-5 MC68HC05SB7 Interrupt Vector Mapping ....................................................... 2-6 MC68HC05 Programming Model ..................................................................... 3-1 Interrupt Stacking Order................................................................................... 4-2 Interrupt Flow Chart ......................................................................................... 4-3 External Interrupt Logic .................................................................................... 4-5 IRQ Status and Control Register (ISCR).......................................................... 4-5 Reset Sources.................................................................................................. 5-1 COP Watchdog Register (COPR) .................................................................... 5-3 Miscellaneous Control Register (MCR)............................................................ 5-3 STOP and WAIT Flowchart.............................................................................. 6-2 Miscellaneous Control Register (MCR)............................................................ 6-5 Port I/O Circuitry............................................................................................... 7-1 MC68HC05SB7 Input Clock Source ................................................................ 8-1 IRQ Status and Control Register (ISCR).......................................................... 8-2 Miscellaneous Control Register (MCR)............................................................ 8-3 VCO Adjust Register (VAR) ............................................................................. 8-3 Core Timer Block Diagram............................................................................... 9-1 Core Timer Status and Control Register (CTSCR) .......................................... 9-2 Core Timer Counter Register (CTCR).............................................................. 9-3 COP Watchdog Register (COPR) .................................................................... 9-4 Miscellaneous Control Register (MCR)............................................................ 9-4 Programmable Timer Block Diagram ............................................................. 10-1 Programmable Timer Block Diagram ............................................................. 10-2 Programmable Timer Registers (TMRH, TMRL)............................................ 10-3 Alternate Counter Block Diagram................................................................... 10-4 Alternate Counter Registers (ACRH, ACRL).................................................. 10-4 Timer Input Capture Block Diagram............................................................... 10-5 Miscellaneous Control Register (MCR).......................................................... 10-5 Analog Control Register (ACR) ...................................................................... 10-6 Input Capture Registers (ICRH, ICRL)........................................................... 10-6 Timer Output Compare Block Diagram .......................................................... 10-7 Output Compare Registers (OCRH, OCRL) .................................................. 10-8 Timer Control Register (TCR) ........................................................................ 10-9 Timer Status Registers (TSR) ...................................................................... 10-10 MOTOROLA vii MC68HC05SB7 REV 2.1 GENERAL RELEASE SPECIFICATION August 27, 1998 LIST OF FIGURES Figure 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-10 11-8 11-9 11-11 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 14-1 14-2 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 16-1 16-2 16-3 18-1 18-2 18-3 18-4 A-1 A-2 A-3 A-4 Title Page PWM Block Diagram ...................................................................................... 11-1 D/A Data Register 0 (DAC0) (MSB) ............................................................... 11-2 D/A Data Register 0 (DAC0) (LSB) ................................................................ 11-2 D/A Data Register 1 (DAC1) (MSB) ............................................................... 11-2 D/A Data Register 1 (DAC1) (LSB) ................................................................ 11-2 D/A Data Register 2 (DAC2) (MSB) ............................................................... 11-2 D/A Data Register 2 (DAC2) (LSB) ................................................................ 11-2 PWM Output Waveform Examples ................................................................ 11-3 D/A Data Register 3 (DAC3) (MSB) ............................................................... 11-3 D/A Data Register 3 (DAC3) (LSB) ................................................................ 11-3 MUX Channel Enable Register (MCER) ........................................................ 11-4 SM-Bus Interface Block Diagram ................................................................... 12-2 SM-Bus Transmission Signal Diagram .......................................................... 12-3 Clock Synchronization.................................................................................... 12-5 Miscellaneous Control Register (MCR)........................................................ 12-10 Flow-chart of SM-Bus Interrupt Routine....................................................... 12-12 Current Sense Amplifier Block ....................................................................... 13-2 CSA Status and Control Register (CSSCR)................................................... 13-3 Miscellaneous Control Register (MCR).......................................................... 13-4 Miscellaneous Control Register (MCR).......................................................... 14-1 External Temperature Sensor Connection..................................................... 14-2 Analog Subsystem Block Diagram................................................................. 15-2 Analog Multiplex Register 1 (AMUX1)............................................................ 15-3 Analog Multiplex Register 2 (AMUX2)............................................................ 15-3 INV Bit Action ................................................................................................. 15-4 Analog Control Register (ACR) .................................................................... 15-14 Analog Status Register ................................................................................ 15-17 Single-Slope A/D Conversion Method.......................................................... 15-19 A/D Conversion - Full Manual Control (Mode 0) .......................................... 15-23 A/D Conversion - Manual/Auto Discharge Control (Mode 1) ....................... 15-24 A/D Conversion - TOF/ICF Control (Mode 2)............................................... 15-25 A/D Conversion - OCF/ICF Control (Mode 3) .............................................. 15-26 Personality EPROM ....................................................................................... 16-1 PEPROM Bit Select Register (PEBSR) ......................................................... 16-2 PEPROM Status and Control Register (PESCR)........................................... 16-2 Stop Recovery Timing Diagram ..................................................................... 18-6 Internal Reset Timing Diagram ...................................................................... 18-7 Low Voltage Reset Timing Diagram............................................................... 18-7 SM-Bus Timing Diagram ................................................................................ 18-9 MC68HC705SB7 Memory Map........................................................................A-1 MC68HC705SB7 Mask Option Register (MOR ...............................................A-2 EPROM Programming Register (EPROG).......................................................A-3 EPROM Programming Sequence ....................................................................A-5 MC68HC05SB7 REV 2.1 MOTOROLA viii August 27, 1998 GENERAL RELEASE SPECIFICATION LIST OF TABLES Table 4-1 7-1 8-1 9-1 10-1 12-1 13-1 13-2 13-3 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 Title Page Reset/Interrupt Vector Addresses .................................................................... 4-1 I/O Pin Functions.............................................................................................. 7-1 Clock Source Selection .................................................................................... 8-2 Core Timer Interrupt Rates and COP Timeout Selection................................. 9-3 16-bit Timer Input Capture Source................................................................. 10-6 SM-Bus Clock Prescaler ................................................................................ 12-6 Voltage Across the Sense Resistor against Current ...................................... 13-1 Current Sense Amplifier Gain Select ............................................................. 13-3 Current Detect Output Select ......................................................................... 13-4 Comparator Input Sources ............................................................................. 15-3 Channel Select Bus Combinations................................................................. 15-6 A/D Conversion Options............................................................................... 15-15 A/D Conversion Signals and Definitions ...................................................... 15-21 Sample Conversion Timing .......................................................................... 15-22 Absolute Voltage Reading Errors................................................................. 15-27 Ratiometric Voltage Reading Errors............................................................. 15-29 Voltage Comparator Setup Conditions......................................................... 15-30 PEPROM Bit Selection................................................................................... 16-3 PEPROM Preprogrammed Option ................................................................. 16-5 Register/Memory Instructions ........................................................................ 17-4 Read-Modify-Write Instructions ..................................................................... 17-5 Jump and Branch Instructions........................................................................ 17-6 Bit Manipulation Instructions .......................................................................... 17-7 Control Instructions ........................................................................................ 17-7 Instruction Set Summary .............................................................................. 17-8 Opcode Map................................................................................................. 17-14 MC68HC05SB7 REV 2.1 MOTOROLA ix GENERAL RELEASE SPECIFICATION August 27, 1998 LIST OF TABLES Table Title Page MOTOROLA x MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 1 GENERAL DESCRIPTION The MC68HC05SB7 HCMOS microcontroller is a member of the M68HC05 family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU), which contains an internal oscillator, CPU, RAM, ROM, personality EPROM, I/O, 16-bit timer, core timer, watchdog system, LVR, SM-Bus, PWM, current sense amplifier, internal temperature sensor and A/D, is designed specifically for smart battery applications. 1.1 FEATURES • • • • • • • Industry standard 8-bit M68HC05 CPU core Power saving STOP, WAIT, DATA-RETENTION and SLOW modes 2.1MHz maximum bus frequency from internal VCO or external pin oscillator 6144 bytes of user ROM with the security feature 224 bytes of user RAM (64 bytes for stack) System calibration characteristics by 64-bit Personality EPROM 19 bidirectional I/O lines – 4 shared with SM-Bus – 4 shared with PWM – 4 shared with A/D analog channels input – 2 shared with current detect output – 1 shared with Timer Input Capture (TCAP) • • • • • 16-bit Programmable Timer with Input Capture/Output Compare (driven by interrupt) 15-stage multi-function Core Timer including 8-bit free-running counter and 4-stage selectable real-time interrupt generator Built-in current sensing amplifiers with selectable gain of 10 and 30 Two voltage comparators which can be combined with the 16-bit Timer to create an 8-channel, single-slope Analog to Digital Converter Built-in internal temperature sensor from 0°C to 70°C MC68HC05SB7 REV 2.1 GENERAL DESCRIPTION MOTOROLA 1-1 GENERAL RELEASE SPECIFICATION August 27, 1998 • • • • • • • • • • 4 channels 10-bit PWM running at a fixed clock rate SM-Bus† serial interface compatible with I2C†† Bus Slow ramp up power supply reset capability via LVR Selectable sensitivity on IRQ interrupt (Edge- and Level-Sensitive or Edge-Only) SM-Bus, current detect, 16-bit timer, analog subsystem and core timer interrupts Internal 100kΩ pull-up resistor on RESET Low Voltage Reset (LVR) Illegal Address Reset Computer Operating Properly (COP) Watchdog system Available in 28-pin SSOP NOTE A bar over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. The exact values and their tolerance or limits are specified in the Electrical Specifications section. 1.2 MASK OPTION A single mask option is available on the MC68HC05SB7. • 1.3 External oscillator on pins OSC1 and OSC2 (EPO): [enabled or disabled] PEPROM FACTORY PREPROGRAMMED OPTIONS The MC68HC05SB7 is available with a factory preprogrammed PEPROM containing any of the following measured parameters: • • • • The internal VCO minimum frequency: programmed or left blank The internal VCO maximum frequency: programmed or left blank The internal bandgap reference voltage: programmed or left blank The internal temperature sensor voltage at 80°C: programmed or left blank 1.4 †SM-Bus MCU STRUCTURE The block diagram of the MC68HC05SB7 is shown in Figure 1-1. is an Intel bus standard. ††I2C Bus is a Philips bus standard. MOTOROLA 1-2 GENERAL DESCRIPTION MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION RESET ILLEGAL ADDR RESET LOW VOLTAGE RESET OSCILLATOR AND DIVIDE BY 2 CPU CONTROL 68HC05 CPU OSC1* (PB2/CS0) CPU REGISOSC2* (PB3/CS1) IRQ/VPP PROGRAM COUNTER PA7/SDA1 PA6/SCL1 DATA DIR REG PORT A REG PA5/SDA0 PA4/SCL0 PA3/PWM3 PA2/PWM2 PA1/PWM1 PA0/PWM0 4 SM-BUS SERIAL INTERFACE 16-BIT TIMER 4 10-BIT PWM SCL TCAP PB7/AN0 DATA DIR REG PB6/AN1 PB5/AN2 PB4/AN3 PB3/CS1* PB2/CS0* PB1/TCAP * Selected by Mask Option CS1:0 4 PORT B REG STATIC RAM - 224 BYTES TCSEL CORE TIMER WATCHDOG SYSTEM VDD VSS ALU ESVEN VDD ACCUM INDEX REG DATA DIR REG 0 0 0 0 0 0 0 0 1 1 STK PTR ESV PORT C REG PC7 PC6 PC5 PC4 COND CODE REG 1 1 1 H I N Z C MUX USER ROM - 6656 BYTES TCAP PERSONALITY EPROM - 64 BITS TCMP ICF OCF AN3:0 TCAP CSA 2 CURRENT SENSE AMPLIFIER COMPARATOR CONTROL AND MULTIPLEXER TOF INTERNAL TEMPERATURE SENSOR AND BANDGAP REFERENCE TM VM CAP COMP + – VDD Figure 1-1. MC68HC05SB7 Block Diagram MC68HC05SB7 REV 2.1 GENERAL DESCRIPTION MOTOROLA 1-3 GENERAL RELEASE SPECIFICATION August 27, 1998 1.5 PIN ASSIGNMENTS The MC68HC05SB7 is available in 28-pin SSOP package. The pin assignments are shown in Figure 1-2. PA7/SDA1 PA6/SCL1 PC7 PC6 PC5 PC4 IRQ/VPP PB1/TCAP PB2/CS0 (OSC1) PB3/CS1 (OSC2) PB4/AN3 PB5/AN2 PB6/AN1 PB7/AN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RESET PA5/SDA0 PA4/SCL0 PA3/PWM3 PA2/PWM2 PA1/PWM1 PA0/PWM0 ESV VM CSA TM CAP(ADC) VSS VDD Figure 1-2. MC68HC05SB7 Pin Assignments 1.6 FUNCTIONAL PIN DESCRIPTION The following paragraphs give a description of the general function of each pin. 1.6.1 VDD, VSS Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. 1.6.2 OSC1, OSC2 When selected by a mask option, the OSC1 and OSC2 pins are the connections for the external pin oscillator (EPO). The OSC1 and OSC2 pins can accept the following sets of components: 1. A crystal as shown in Figure 1-3(a). 2. A ceramic resonator as shown in Figure 1-3(a). 3. An external clock signal as shown in Figure 1-3(b). MOTOROLA 1-4 GENERAL DESCRIPTION MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION The frequency, fOSC of the EPO or external clock source is divided by two to produce the internal operating frequency, fOP. or fBUS. Crystal Oscillator The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. MCU MCU OSC1 2MΩ OSC2 OSC1 OSC2 Unconnected External Clock (a) Crystal or Ceramic Resonator Connections (b) External Clock Source Connection Figure 1-3. EPO Oscillator Connections Ceramic Resonator Oscillator In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The resonator manufacturer’s recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b). This configuration is possible regardless of whether the crystal/ceramic resonator or internal VCO is enabled. 1.6.3 IRQ/VPP The IRQ/VPP input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a bit to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the MC68HC05SB7 REV 2.1 GENERAL DESCRIPTION MOTOROLA 1-5 GENERAL RELEASE SPECIFICATION August 27, 1998 option is selected to include level-sensitive triggering, the IRQ/VPP input requires an external resistor to VDD for “wired-OR” operation, if desired. If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin may affect the mode of operation and should not exceed VDD. The IRQ/VPP pin is also used for programming voltage when programming the Personality EPROM. See section on Interrupts for more details. 1.6.4 RESET The RESET pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. It also functions as an output to indicate that an internal COP watchdog, illegal address, or low voltage reset has occurred. The RESET pin contains a pullup device to allow the pin to be left disconnected without an external pullup resistor. The RESET pin also contains a steering diode that, when the power is removed, will discharge to VDD any charge left on an external capacitor connected between the RESET pin and VSS. The RESET pin also contains an internal Schmitt trigger to improve its noise immunity as an input. See section on Resets for more details. 1.6.5 CSA This pin is the input to the current sense amplifier. Usually one terminal of the current path shunt sensing resistor of 0.01Ω is connected to this input pin. The other terminal is connected to VSS. See section on Current Sense Amplifier for more details. 1.6.6 TM This pin is fed from the output of an external temperature sensor. Usually a thermistor with a resistor forms a voltage divider with the voltage value applied to this input. See section on Temperature Sensor for more details. 1.6.7 VM This pin is the battery voltage input of the voltage measurement circuit. See section on Temperature Sensor for more details. 1.6.8 CAP (ADC) This pin is connected to an external ramp capacitor to form the slope voltage converter. See section on Analog Subsystem for more details. MOTOROLA 1-6 GENERAL DESCRIPTION MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 1.6.9 ESV This pin provides a switchable 5mA at VOH (at worst case) to an external EEPROM. The ESVEN bit in the Miscellaneous Control Register enables/disables the ESV pin. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 U = UNAFFECTED BY RESET ESVEN — ESV Enable This read/write bit selects whether ESV is enable or not. Reset clears the ESVEN bit. 1 = ESV enabled. 0 = ESV disabled. 1.6.10 PA0-PA7 / PWM0-PWM3, SCL0-SCL1, SDA0-SDA1 These eight I/O lines comprise the Port A. The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset. PA0-PA3 are multiplexed with PWM outputs PWM0-PWM3. PA4-PA7 are multiplexed with the two SM-Bus channels - SCL0, SDA0 and SCL1, SDA1. 1.6.11 PB1-PB7 / TCAP, CS0-CS1, AN0-AN3 Pins PB2/CS0 and PB3/CS1 are only available when selected by a mask option. These seven I/O lines comprise the Port B. The state of any pin is software programmable and all Port B lines are configured as input during power-on or at reset. PB1 is configured as the TCAP input pin for the 16-bit timer after a reset, and is disabled by setting the ICEN bit in the Analog Control Register ($1D). PB2 and PB3 (when selected) are multiplexed with CS0 and CS1 respectively, from the current sense interrupt circuit. See section on Current Sense Amplifier for more details. PB4-PB7 are multiplexed with the analog input pins of the A/D converter. See section on Analog Subsystem for more details. 1.6.12 PC4-PC7 These four I/O lines comprise the port C. The state of any pin is software programmable and all port C lines are configured as input during power-on or at reset. MC68HC05SB7 REV 2.1 GENERAL DESCRIPTION MOTOROLA 1-7 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 1-8 GENERAL DESCRIPTION MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 2 MEMORY This section describes the organization of the MC68HC05SB7 on-chip memory. 2.1 MEMORY MAP In Normal operating mode, the 48 bytes of I/O, 224 bytes of user RAM and 6144 bytes of user ROM are all active as shown in Figure 2-1. The ROM portion of memory holds the program instructions, fixed data, user defined vectors, and interrupt service routines. The RAM portion of memory holds variable data. I/O registers are memory mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. $0000 $002F $0030 $003F $0040 USER RAM 224 BYTES $011F $0120 $05FF $0600 USER ROM 6144 BYTES $1DFF $1E00 $1FEF $1FF0 $1FFF INTERNAL TEST ROM 496 BYTES USER VECTORS 16 BYTES STACK RAM 64 BYTES UNIMPLEMENTED 1248 BYTES $00C0 $00FF I/O REGISTERS 48 BYTES UNIMPLEMENTED 16 BYTES Figure 2-1. MC68HC05SB7 Memory Map MC68HC05SB7 REV 2.1 MEMORY MOTOROLA 2-1 GENERAL RELEASE SPECIFICATION August 27, 1998 2.2 INPUT/OUTPUT SECTION The first 48 addresses of the memory space, $0000 – $002F, are the I/O section as summarized in Figure 2-2. These are the addresses of the I/O control registers, status registers, and data registers. Reading from unimplemented locations will return unknown states, and writing to unimplemented locations will be ignored. One I/O register is located outside the 48-byte I/O section which is the computer operating properly (COP) register, mapped at $1FF0. The assignment of each control, status, and data bit in the I/O register space from $0000 through $002F are given in Figure 2-3, Figure 2-4, and Figure 2-5. Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 Register Name Port A Data Register Port B Data Register Port C Data Register Analog MUX Register 1 Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Analog MUX Register 2 Core Timer Status & Control Register Core Timer Counter CSA Status/Control Register Miscellaneous Control Register VCO Adjust Register IRQ Status & Control Register Personality EPROM Bit Select Register Personality EPROM Status & Control Reg. Reserved Reserved Timer Control Register Timer Status Register Input Capture Register MSB Input Capture Register LSB Output Compare Register MSB Output Compare Register LSB Addr. $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F Register Name Timer Counter Register MSB Timer Counter Register LSB Alternate Counter Register MSB Alternate Counter Register LSB Reserved Analog Control Register Analog Status Register Reserved SM-Bus Address Register SM-Bus Frequency Select Register SM-Bus Control Register SM-Bus Status Register SM-Bus Data Register D/A Register 0 H D/A Register 0 L D/A Register 1 H D/A Register 1 L D/A Register 2 H D/A Register 2 L D/A Register 3 H D/A Register 3 L MUX Channel Enable Register Reserved Reserved Figure 2-2. MC68HC05SB7 I/O Registers MOTOROLA 2-2 MEMORY MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION ADDR $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F REGISTER Port A Data PORTA Port B Data PORTB Port C Data PORTC Analog MUX 1 AMUX1 Port A Data Direction DDRA Port B Data Direction DDRB Port C Data Direction DDRC Analog MUX 2 AMUX2 CTimer Status/Ctrl CTSCR CTimer Counter CTCR CSA Status/Control CSASCR Misc Control MCR VCO Adjust VAR IRQ Status/Ctrl ISCR PEPROM Bit Select PEBSR PEPROM Status/Ctrl PESCR R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIT 7 PA7 PB7 PC7 HOLD BIT 6 PA6 PB6 PC6 DHOLD BIT 5 PA5 PB5 PC5 INV BIT 4 PA4 PB4 PC4 VREF BIT 3 PA3 PB3 BIT 2 PA2 PB2 BIT 1 PA1 PB1 BIT 0 PA0 MUX3 MUX2 DDRA2 DDRB2 0 MUX1 DDRA1 DDRB1 0 MUX0 DDRA0 0 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRC7 DDRC6 DDRC5 DDRC4 0 0 IREF RTIE TMR4 0 MUX7 0 CTOFR TMR3 MUX6 0 RTIFR TMR2 MUX5 RT1 TMR1 0 CSIFR MUX4 RT0 TMR0 CSIF CTOF TMR7 RTIF TMR6 CTOFE TMR5 CSEN TSEN X30 LVRON X10 0 COPON CSCAL SCLK VA4 CDEN CSSEL VA3 IRQF CDIE TCSEL VA2 0 ESVEN SMINLEV VA1 0 IRQR VA0 0 IRQE PEB7 PEDATA VCOEN PEB7 0 LEVEL PEB7 PEPGM 0 PEB4 0 PEB3 0 PEB2 0 PEB1 0 PEB0 PEPZRF unimplemented bits reserved bits Figure 2-3. MC68HC05SB7 I/O Registers $0000-$000F MC68HC05SB7 REV 2.1 MEMORY MOTOROLA 2-3 GENERAL RELEASE SPECIFICATION August 27, 1998 ADDR $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F REGISTER Reserved Reserved Timer Control TCR Timer Status TSR Input Capture MSB ICRH Input Capture LSB ICRL Output Compare MSB OCRH Output Compare LSB OCRL Timer Counter MSB TMRH Timer Counter LSB TMRL Alter. Counter MSB ACRH Alter. Counter LSB ACRL Reserved Analog Control ACR Analog Status ASR Reserved R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ICIE ICF ICRH7 ICRL7 OCIE OCF ICRH6 ICRL6 TOIE TOF ICRH5 ICRL5 0 0 ICRH4 ICRL4 0 0 ICRH3 ICRL3 0 0 ICRH2 ICRL2 IEDG 0 ICRH1 ICRL1 OLVL 0 ICRH0 ICRL0 OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0 OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0 TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0 TMRL7 ACRH7 ACRL7 TMRL6 ACRH6 ACRL6 TMRL5 ACRH5 ACRL5 TMRL4 ACRH4 ACRL4 TMRL3 ACRH3 ACRL3 TMRL2 ACRH2 ACRL2 TMRL1 ACRH1 ACRL1 TMRL0 ACRH0 ACRL0 CHG CPF ATD2 ATD1 0 CPFR ICEN 0 CPIE 0 CPEN 0 0 ISEN 0 unimplemented bits reserved bits Figure 2-4. MC68HC05SB7 I/O Registers $0010-$001F MOTOROLA 2-4 MEMORY MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION ADDR $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F REGISTER SM-Bus Address SMADR SM-Bus Freq. Sel. SMFDR SM-Bus Control SMCR SM-Bus Status SMSR SM-Bus Data SMDR D/A Register 0 DAC0 D/A Register 0 DAC0 D/A Register 1 DAC1 D/A Register 1 DAC1 D/A Register 2 DAC2 D/A Register 2 DAC2 D/A Register 3 DAC3 D/A Register 3 DAC3 MUX Channel Enable MCER Reserved Reserved R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SMAD7 SMAD6 SMAD5 SMAD4 SMAD3 SMAD2 SMAD1 FD4 SMEN SMCF SMIEN SMAAS SMSTA SMBB SMTX SMAL SMAL clr SMD7 SMD6 SMD5 SMD4 SMD3 SMD2 FD3 TXAK FD2 SMUX SRW SMIF SMIF clr SMD1 SMD0 RXAK FD1 FD0 D9 D8 D7 D6 D5 D4 D3 D1 D2 D0 D2 D0 D2 D0 D2 D0 DA0-E D9 D8 D7 D6 D5 D4 D3 D1 D9 D8 D7 D6 D5 D4 D3 D1 D9 D8 D7 D6 D5 D4 D3 D1 PWM_I DA3-E DA2-E DA1-E unimplemented bits reserved bits Figure 2-5. MC68HC05SB7 I/O Registers $0020-$002F ADDR $1FF0 REGISTER COP Register COPR R/W R W BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 COPC Figure 2-6. COP Register (COPR) MC68HC05SB7 REV 2.1 MEMORY MOTOROLA 2-5 GENERAL RELEASE SPECIFICATION August 27, 1998 2.3 INTERRUPT VECTOR MAPPING The interrupt vectors are contained in the upper memory addresses above $1FF0 as shown in Figure 2-2. Addr. $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF Register Name CDET INTERRUPT VECTOR (MSB) CDET INTERRUPT VECTOR (LSB) ANALOG INTERRUPT VECTOR (MSB) ANALOG INTERRUPT VECTOR (LSB) SM-BUS INTERRUPT VECTOR (MSB) SM-BUS INTERRUPT VECTOR (LSB) TIMER INTERRUPT VECTOR (MSB) TIMER INTERRUPT VECTOR (LSB) CTIMER INTERRUPT VECTOR (MSB) CTIMER INTERRUPT VECTOR (LSB) EXTERNAL IRQ VECTOR (MSB) EXTERNAL IRQ VECTOR (LSB) SWI VECTOR (MSB) SWI VECTOR (LSB) RESET VECTOR (MSB) RESET VECTOR(LSB) Figure 2-7. MC68HC05SB7 Interrupt Vector Mapping 2.4 ROM There are a total of 6160 bytes of ROM on chip. This includes 6144 bytes of user ROM with locations $0600 through $1DFF for the user program storage and another 16 bytes for user vectors at locations $1FF0 through $1FFF. 2.5 RAM The 224 addresses from $0040 to $011F serve as both the user RAM and the stack RAM. The stack begins at address $00C0 and proceeds down to $00FF. The stack pointer can access 64 locations from $00C0 to $00FF. Using the stack area for data storage or temporary work locations requires care to prevent it from being over written due to stacking from an interrupt or subroutine call. The CPU uses five RAM bytes to save all CPU register contents before processing an interrupt. During a subroutine call, the CPU uses two bytes to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MOTOROLA 2-6 MEMORY MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 3 CENTRAL PROCESSING UNIT The MC68HC05SB7 has an 8k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter. 3.1 REGISTERS The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1 and are described in the following paragraphs. 7 6 5 4 3 2 1 0 A ACCUMULATOR 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 1 1 INDEX REGISTER X STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER 1 1 1 H I N Z C CC HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT Figure 3-1. MC68HC05 Programming Model MC68HC05SB7 REV 2.1 CENTRAL PROCESSING UNIT MOTOROLA 3-1 GENERAL RELEASE SPECIFICATION August 27, 1998 3.2 ACCUMULATOR (A) The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device. 3.3 INDEX REGISTER (X) The index register shown in Figure 3-1 is an 8-bit register that can perform two functions: • • Indexed addressing Temporary storage In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register content to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand address by adding the index register content to a 16-bit immediate value. The index register can also serve as an auxiliary accumulator for temporary storage. The index register is not affected by a reset of the device. 3.4 STACK POINTER (SP) The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. The six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses five locations. 3.5 PROGRAM COUNTER (PC) The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched. MOTOROLA 3-2 CENTRAL PROCESSING UNIT MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 CONDITION CODE REGISTER (CCR) The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a program, and specific actions can be taken as a result of their states. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register. 3.6.1 Half Carry Bit (H-Bit) When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations. 3.6.2 Interrupt Mask (I-Bit) When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions. 3.6.3 Negative Bit (N-Bit) The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.) The negative bit can also be used to check an often tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag. 3.6.4 Zero Bit (Z-Bit) The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. MC68HC05SB7 REV 2.1 CENTRAL PROCESSING UNIT MOTOROLA 3-3 GENERAL RELEASE SPECIFICATION August 27, 1998 3.6.5 Carry/Borrow Bit (C-Bit) The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction. MOTOROLA 3-4 CENTRAL PROCESSING UNIT MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 4 INTERRUPTS An interrupt temporarily stops normal program execution to process a particular event. An interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the CPU registers on the stack and loads the program counter with a user-defined vector address. 4.1 INTERRUPT VECTORS Table 4-1. Reset/Interrupt Vector Addresses Function Source Power-On Logic RESET Pin Low Voltage Reset Illegal Address Reset COP Watchdog Software Interrupt (SWI) External Interrupt (IRQ) Core Timer Interrupts Programmable Timer Interrupts SM-Bus Interrupt Analog Interrupt Current Detect Interrupt 1. User Code IRQ/VPP Pin TOF Bit RTIF Bit ICF Bit OCF Bit TOF Bit SMIF Bit CPF1 Bit CPF2 Bit CIF Bit Control Bit Global Hardware Mask Local Software Mask Priority (1 = Highest) Vector Address — — COPON1 — — — — I Bit I Bit — IRQE Bit TOFE Bit RTIE Bit ICIE Bit OCIE Bit TOIE Bit SMIE Bit CPIE Bit CIE Bit Same Priority As Instruction 2 3 $1FFC–$1FFD $1FFA–$1FFB $1FF8–$1FF9 — 1 $1FFE–$1FFF Reset — I Bit 4 $1FF6–$1FF7 — — — I Bit I Bit I Bit 5 6 7 $1FF4–$1FF5 $1FF2–$1FF3 $1FF0–$1FF1 COPON enables the COP watchdog timer Table 4-1 summarizes the reset and interrupt sources and vector assignments. MC68HC05SB7 REV 2.1 INTERRUPTS MOTOROLA 4-1 GENERAL RELEASE SPECIFICATION August 27, 1998 NOTE If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit. 4.2 INTERRUPT PROCESSING The CPU does the following actions to begin servicing an interrupt: • • • Stores the CPU registers on the stack in the order shown in Figure 4-1. Sets the I bit in the condition code register to prevent further interrupts. Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1. The return from interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt are shown in the flow chart in Figure 4-2. $0020 $0021 (BOTTOM OF RAM) $00BE $00BF $00C0 $00C1 $00C2 UNSTACKING ORDER (BOTTOM OF STACK) ⇓ n n+1 n+2 n+3 n+4 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE) 5 4 3 2 1 1 2 3 4 5 ⇑ STACKING $00FD $00FE $00FF TOP OF STACK (RAM) ORDER Figure 4-1. Interrupt Stacking Order MOTOROLA 4-2 INTERRUPTS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? NO YES CLEAR IRQ LATCH. CORE TIMER INTERRUPT? NO YES TIMER INTERRUPT? NO YES SM-BUS INTERRUPT? NO YES ANALOG INTERRUPT? NO YES CDET INTERRUPT? NO YES STACK PCL, PCH, X, A, CCR. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI INSTRUCTION? NO YES RTI INSTRUCTION? NO YES UNSTACK CCR, A, X, PCH, PCL. EXECUTE INSTRUCTION. Figure 4-2. Interrupt Flow Chart MC68HC05SB7 REV 2.1 INTERRUPTS MOTOROLA 4-3 GENERAL RELEASE SPECIFICATION August 27, 1998 4.3 SOFTWARE INTERRUPT The software interrupt (SWI) instruction causes a nonmaskable interrupt. 4.4 EXTERNAL INTERRUPT The IRQ/VPP pin is the source that generates external interrupt. Setting the I bit in the condition code register or clearing the IRQE bit in the interrupt status and control register disables this external interrupt. 4.4.1 IRQ/VPP Pin An interrupt signal on the IRQ/VPP pin latches an external interrupt request. To help clean up slow edges, the input from the IRQ/VPP pin is processed by a Schmitt trigger gate. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit is clear and the IRQE bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. Figure 4-3 shows the logic for external interrupts. NOTE If the IRQ/VPP pin is not in use, it should be connected to the VDD pin. The IRQ/VPP pin can be negative edge-triggered only or negative edge- and lowlevel-triggered. External interrupt sensitivity is programmed with the LEVEL bit. With the edge- and level-sensitive trigger option, a falling edge or a low level on the IRQ/VPP pin latches an external interrupt request. The edge- and level-sensitive trigger option allows connection to the IRQ/VPP pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ/VPP low, an external interrupt request is present, and the CPU continues to execute the interrupt service routine. With the edge-sensitive-only trigger option, a falling edge on the IRQ/VPP pin latches an external interrupt request. A subsequent interrupt request can be latched only after the voltage level on the IRQ/VPP pin returns to a logic one and then falls again to logic zero. MOTOROLA 4-4 INTERRUPTS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION VPP TO USER EPROM AND PEPROM TO BIH & BIL INSTRUCTION PROCESSING IRQ/VPP VDD IRQ LATCH R EXTERNAL INTERRUPT REQUEST LEVEL RST IRQ VECTOR FETCH IRQE IRQ STATUS/CONTROL REGISTER INTERNAL DATA BUS Figure 4-3. External Interrupt Logic 4.4.2 IRQ Status and Control Register (ISCR) The IRQ status and control register (ISCR), shown in Figure 4-4, contains an external interrupt mask (IRQE), an external interrupt flag (IRQF), and a flag reset bit (IRQR). Unused bits will read as logic zeros. Reset sets the IRQE bit and clears all the other bits. BIT 7 ISCR $000D reset: R W IRQE 1 BIT 6 VCOEN 1 BIT 5 LEVEL 0 BIT 4 0 0 BIT 3 IRQF 0 BIT 2 0 0 BIT 1 0 IRQR 0 0 BIT 0 0 Figure 4-4. IRQ Status and Control Register (ISCR) MC68HC05SB7 REV 2.1 INTERRUPTS IRQR IRQF MOTOROLA 4-5 GENERAL RELEASE SPECIFICATION August 27, 1998 IRQE — External Interrupt Request Enable This read/write bit enables external interrupts. Reset sets the IRQE bit. 1 = External interrupt processing enabled. 0 = External interrupt processing disabled. VCOEN — VCO Enable Please refer to section on System Clock. LEVEL — External Interrupt Sensitivity This bit makes the external interrupt inputs level-triggered as well as edge-triggered. 1 = IRQ/VPP pin negative edge-triggered and low level-triggered. 0 = IRQ/VPP pin negative edge-triggered only. IRQF — External Interrupt Request Flag The IRQ flag is a clearable, read-only bit that is set when an external interrupt request is pending. Reset clears the IRQF bit. 1 = Interrupt request pending. 0 = No interrupt request pending. The following condition set the IRQ flag: • An external interrupt signal on the IRQ/VPP pin. The following conditions clear the IRQ flag: • • When the CPU fetches the interrupt vector. When a logic “1” is written to the IRQR bit. IRQR — Interrupt Request Reset This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Writing a logic one to IRQR clears the IRQF. Writing a logic zero to IRQR has no effect. IRQR always reads as a logic zero. Reset has no affect on IRQR. 1 = Clear IRQF flag bit. 0 = No effect. 4.5 CORE TIMER INTERRUPTS The Core Timer can generate the following interrupts: • • Timer overflow interrupt. Real-time interrupt. Setting the I bit in the condition code register disables Core Timer interrupts. The controls and flags for these interrupts are in the Core Timer status and control register (CTSCR) located at $0008. MOTOROLA 4-6 INTERRUPTS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 4.5.1 Core Timer Overflow Interrupt An overflow interrupt request occurs if the Core Timer overflow flag (TOF) becomes set while the Core Timer overflow interrupt enable bit (TOFE) is also set. The TOF flag bit can be reset by writing a logical one to the CTOFR bit in the CTSCR or by a reset of the device. 4.5.2 Real-Time Interrupt A real-time interrupt request occurs if the real-time interrupt flag (RTIF) becomes set while the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical one to the RTIFR bit in the CTSCR or by a reset of the device. 4.6 PROGRAMMABLE TIMER INTERRUPTS The 16-bit programmable Timer can generate an interrupt whenever the following events occur: • • • Input capture. Output compare. Timer counter overflow. Setting the I bit in the condition code register disables Timer interrupts. The controls for these interrupts are in the Timer control register (TCR) located at $0012 and in the status bits are in the Timer status register (TSR) located at $0013. 4.6.1 Input Capture Interrupt An input capture interrupt occurs if the input capture flag (ICF) becomes set while the input capture interrupt enable bit (ICIE) is also set. The ICF flag bit is in the TSR; and the ICIE enable bit is located in the TCR. The ICF flag bit is cleared by a read of the TSR with the ICF flag bit is set; and then followed by a read of the LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected by reset. 4.6.2 Output Compare Interrupt An output compare interrupt occurs if the output compare flag (OCF) becomes set while the output compare interrupt enable bit (OCIE) is also set. The OCF flag bit is in the TSR and the OCIE enable bit is in the TCR. The OCF flag bit is cleared by a read of the TSR with the OCF flag bit set; and then followed by an access to the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is unaffected by reset. 4.6.3 Timer Overflow Interrupt A Timer overflow interrupt occurs if the Timer overflow flag (TOF) becomes set while the Timer overflow interrupt enable bit (TOIE) is also set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR. The TOF flag bit is cleared by a MC68HC05SB7 REV 2.1 INTERRUPTS MOTOROLA 4-7 GENERAL RELEASE SPECIFICATION August 27, 1998 read of the TSR with the TOF flag bit set; and then followed by an access to the LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected by reset. 4.7 SM-BUS INTERRUPT There is one SM-Bus interrupt flag that causes SM-Bus interrupt whenever it is set and enabled. The interrupt flags is in the SM-Bus Status Register (SMSR) and the enable bit is in SM-Bus Control Register (SMCR). SM-Bus interrupt can wake up MCU from WAIT mode. 4.8 ANALOG INTERRUPTS The analog subsystem can generate the following interrupts: • • Voltage on positive input of comparator is greater than the voltage on the negative input of comparator. Trigger of the input capture interrupt from the programmable Timer as described in Section 4.6 above. Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these interrupts are in the analog subsystem control register (ACR) located at $001D and the status bits are in the analog subsystem status register (ASR) located at $001E. 4.8.1 Comparator Input Match Interrupt A comparator input match interrupt occurs if the compare flag bit (CPF) in the ASR becomes set while the comparator interrupt enable bit (CPIE) in the ACR is also set. Reset clears these bits. 4.8.2 Input Capture Interrupt The analog subsystem can also generate an input capture interrupt through the programmable Timer. The input capture can be triggered when there is a match in the input conditions for the voltage comparator. If comparator sets the CPF flag bit in the ASR and the input capture enable (ICEN) in the ACR is set then an input capture will be performed by the programmable Timer. If the ICIE enable bit in the TCR is also set then an input compare interrupt will occur. Reset clears these bits. NOTE In order for the analog subsystem to generate an interrupt using the input capture function of the programmable Timer the ICEN enable bit in the ACR and the ICIE enable bit in the TCR must both be set. 4.9 CURRENT DETECT INTERRUPT The Current Sense Amplifier circuit can be configured to generate an interrupt once it detects a current passing through the current sensing resistor. MOTOROLA 4-8 INTERRUPTS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 5 RESETS This section describes the five reset sources and how they initialize the MCU. A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user defined reset vector address. The following conditions produce a reset: • • • • • Initial power up of device (power on reset). A logic zero applied to the RESET pin (external reset). Timeout of the COP watchdog (COP reset). Low voltage applied to the device (LVR reset). Fetch of an opcode from an address not in the memory map (illegal address reset). Figure 5-1 shows a block diagram of the reset sources and their interaction. MCU INTERNAL REGISTER COPON LVREN COP WATCHDOG LOW VOLTAGE RESET VDD POWER-ON RESET ILLEGAL ADDRESS RESET VDD 100KΩ RESET INTERNAL ADDRESS BUS S RST D RESET LATCH 3-CYCLE CLOCKED ONE-SHOT R INTERNAL CLOCK TO CPU AND SUBSYSTEMS Figure 5-1. Reset Sources MC68HC05SB7 REV 2.1 RESETS MOTOROLA 5-1 GENERAL RELEASE SPECIFICATION August 27, 1998 5.1 POWER-ON RESET A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic zero at the end of the multiple tCYC time, the MCU remains in the reset condition until the signal on the RESET pin goes to a logic one. 5.2 EXTERNAL RESET A logic zero applied to the RESET pin for 1.5tCYC generates an external reset. This pin is connected to a Schmitt trigger input gate to provide and upper and lower threshold voltage separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals. The RESET pin can also act as an open drain output. It will be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. This RESET pulldown device will only be asserted for 3 - 4 cycles of the internal clock, fOP, or as long as the internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will not be turned on. NOTE Do not connect the RESET pin directly to VDD, as this may overload some power supply designs when the internal pulldown on the RESET pin activates. 5.3 INTERNAL RESETS The four internally generated resets are the initial power-on reset function, the COP Watchdog timer reset, the low voltage reset, and the illegal address detector. Only the COP Watchdog timer reset, low voltage reset and illegal address detector will also assert the pulldown device on the RESET pin for the duration of the reset function or 3 - 4 internal clock cycles, whichever is longer. 5.3.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active. MOTOROLA 5-2 RESETS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 4064 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR in order for the internal POR circuit to detect the next rise of VDD. 5.3.2 Computer Operating Properly (COP) Reset A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic zero to the COPC bit of the COP register at location $1FF0. BIT 7 COPR $1FF0 reset: R W U U U U U U U 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 COPC 0 U = UNAFFECTED BY RESET Figure 5-2. COP Watchdog Register (COPR) COPC — COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = No effect on system. 0 = Reset COP watchdog timer. The COP Watchdog reset will assert the pulldown device to pull the RESET pin low for three to four clock cycles of the internal bus clock. After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic “1” to the COPON bit in the Miscellaneous Control Register (see Figure 5-2). Once enabled, the COP watchdog can only be disabled by a POR or reset. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 U = UNAFFECTED BY RESET Figure 5-3. Miscellaneous Control Register (MCR) COPON — COP ON COPON is a write-once bit. 1 = Enables COP watchdog system. 0 = No effect on system. See section on Core Timer for detail on COP watchdog timeout periods. MC68HC05SB7 REV 2.1 RESETS MOTOROLA 5-3 GENERAL RELEASE SPECIFICATION August 27, 1998 5.3.3 Low Voltage Reset (LVR) The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four clock cycles of the internal bus clock. The Low Voltage Reset circuit is enabled/disabled by the LVRON bit in the Miscellaneous Control Register (see Figure 5-2). LVRON — LVR ON This is a read/write bit to disable/enable the LVR circuit. 0 = Low Voltage Reset circuit disabled. 1 = Low Voltage Reset circuit enabled. This is the default setting at POR or reset. 5.3.4 Illegal Address Reset An opcode fetch from an address that is not in the EPROM (locations $0600 – $1DFF and $1FF0 - $1FFF) or the RAM (locations $0030 – $010F) generates an illegal address reset. The illegal address reset will assert the pulldown device to pull the RESET pin low for 3 - 4 cycles of the internal bus clock. 5.4 RESET STATES The following paragraphs describe how the various resets initialize the MCU. 5.4.1 CPU A reset has the following effects on the CPU: • • • • • Loads the stack pointer with $FF. Sets the I bit in the condition code register, inhibiting interrupts. Loads the program counter with the user defined reset vector from locations $1FFE and $1FFF. Clears the stop latch, enabling the CPU clock. Clears the wait latch, bringing the CPU out of the wait mode. 5.4.2 I/O Registers A reset has the following effects on I/O registers: • Clears bits in data direction registers configuring pins as inputs: – DDRA7 – DDRA0 in DDRA for port A. – DDRB7 – DDRB1 in DDRA for port B. – DDRC3–DDRC0 in DDRA for port C. • • MOTOROLA 5-4 Has no effect on port A, B or C data registers. Sets the IRQE bit in the interrupt status and control register. RESETS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 5.4.3 Core Timer A reset has the following effects on the Core Timer: • • • Clears the Core Timer counter register (CTCR). Clears the Core Timer interrupt flag and enable bits in the Core Timer status and control register (CTSCR). Sets the real-time interrupt rate selection bits (RT0, RT1) such that the device will start with the longest real-time interrupt and COP timeout delays. 5.4.4 COP Watchdog A reset clears the COP watchdog timeout counter. 5.4.5 16-Bit Programmable Timer A reset has the following effects on the 16-bit programmable Timer: • • • • • • • Initializes the timer counter registers (TMRH, TMRL) to a value of $FFFC. Initializes the alternate timer counter registers (ACRH, ACRL) to a value of $FFFC. Clears all the interrupt enables and the output level bit (OLVL) in the timer control register (TCR). Does not affect the input capture edge bit (IEDG) in the TCR. Does not affect the interrupt flags in the timer status register (TSR). Does not affect the input capture registers (ICRH, ICRL). Does not affect the output compare registers (OCRH, OCRL). 5.4.6 SM-Bus Serial Interface A reset has the following effects on the SM-Bus serial interface: • • • • • Clears all bits in the address register (SMADR) and those unimplemented bit locations are not affected. Clears all bits in the frequency divider register (SMFDR) and those unimplemented bit locations are not affected. Clears all bits in control register (SMCR) and those unimplemented bit locations are not affected. Sets SMCF & RXAK bits and clears other bits and those unimplemented bit locations are not affected. Does not affect the contents of the data I/O register (SMDR). MC68HC05SB7 REV 2.1 RESETS MOTOROLA 5-5 GENERAL RELEASE SPECIFICATION August 27, 1998 A reset therefore disables the SM-Bus and leaves the shared port A pins as general I/O. Any pending interrupt flag is cleared and the SM-Bus interrupt is disabled. Also the clock rate defaults to the fastest rate. 5.4.7 Analog Subsystem A reset has the following effects on the analog subsystem: • • • Clears all the bits in the multiplex registers (AMUX1, AMUX2) bits except the hold switch bit (HOLD) which is set. Clears all the bits in the analog control register (ACR). Clears all the bits in the analog status register (ASR). A reset therefore connects the negative input of comparator to the channel selection bus, which is switched to VSS. The comparator is set up as non-inverting (a higher positive voltage on the positive input results in a positive output) and both are powered down. The current source and discharge device on the CAP pin is also disabled and powered down. Any analog subsystem interrupt flags are cleared and the interrupts are disabled. MOTOROLA 5-6 RESETS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 6 LOW POWER MODES There are four modes of operation that reduce power consumption: • • • • Stop mode Wait mode Data retention mode Slow mode Figure 6-1 shows the sequence of events in stop and wait modes. MC68HC05SB7 REV 2.1 LOW POWER MODES MOTOROLA 6-1 GENERAL RELEASE SPECIFICATION August 27, 1998 STOP WAIT CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. TURN OFF CPU CLOCK. KEEP OTHER MODULE CLOCKS ACTIVE. CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. CLEAR CTOF, RTIF, CTOFE, AND RTIE BITS IN TSCR. CLEAR ICF, OCF AND TOF BITS IN TSR. CLEAR ICIE, OCIE and TOIE BITS IN TCR. DISABLE OSCILLATOR YES EXTERNAL RESET? NO EXTERNAL RESET? NO YES YES EXTERNAL INTERRUPT? NO EXTERNAL INTERRUPT? NO YES YES CORE TIMER INTERRUPT? NO YES PROG. TIMER INTERRUPT? NO TURN ON OSCILLATOR. RESET STABILIZATION DELAY TIMER. YES SM-BUS INTERRUPT? NO YES END OF STABILIZATION DELAY? NO YES ANALOG INTERRUPT? NO YES TURN ON CPU CLOCK. CDET INTERRUPT? NO YES COP RESET? NO 1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON STACK. b. SET I BIT IN CCR. c. LOAD PC WITH INTERRUPT VECTOR. Figure 6-1. STOP and WAIT Flowchart MOTOROLA 6-2 LOW POWER MODES MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 6.1 STOP MODE The STOP instruction puts the MCU in a mode with the lowest power consumption and has the following affect on the MCU: • Turns off the CPU clock and all internal clocks by stopping the internal oscillator. The stopped clocks turn off the COP watchdog, the Core Timer, the programmable Timer, the analog subsystem and the SM-Bus Interface. Removes any pending Core Timer interrupts by clearing the Core Timer interrupt flags (CTOF, RTIF) in the Core Timer status and control register (CTSCR). Disables any further Core Timer interrupts by clearing the Core Timer interrupt enable bits (CTOFE, RTIE) in the CTSCR. Removes any pending programmable Timer interrupts by clearing the timer interrupt flags (ICF, OCF and TOF) in the timer status register (TSR). Disables any further programmable Timer interrupts by clearing the timer interrupt enable bits (ICIE, OCIE and TOIE) in the timer control register (TCR). Enables external interrupts via the IRQ/VPP pin by setting the IRQE bit in the IRQ status and control register (ISCR). Enables interrupts in general by clearing the I bit in the condition code register. • • • • • The STOP instruction does not affect any other bits, registers or I/O lines. The following conditions bring the MCU out of stop mode: • An external interrupt signal on the IRQ/VPP pin — A high to low transition on the IRQ/VPP pin loads the program counter with the contents of locations $1FFA and $1FFB. External reset — A logic zero on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. • When the MCU exits stop mode, processing resumes after a stabilization delay of 4064 oscillator cycles. If an external interrupt brings the MCU out of stop mode after an active edge occurred on the PC3/TCAP during the stop mode, the ICF flag becomes set. An external interrupt also latches the value of the timer registers into the input capture registers. If an external reset brings the MCU out of the stop mode after an active edge occurred on the PC3/TCAP pin during the stop mode, the ICF flag does not become set. An external reset has no effect on the input capture registers. MC68HC05SB7 REV 2.1 LOW POWER MODES MOTOROLA 6-3 GENERAL RELEASE SPECIFICATION August 27, 1998 6.2 WAIT MODE The WAIT instruction puts the MCU in a low power wait mode which consumes more power than the stop mode. The wait mode and has the following affects on the MCU: • • • Enables interrupts by clearing the I bit in the condition code register. Enables external interrupts by setting the IRQE bit in the IRQ status and control register. Stops the CPU clock which drives the address and data buses, but allows the internal oscillator and its clock to continue to run and drive the Core Timer, programmable Timer, analog subsystem and SM-Bus. The WAIT instruction does not affect any other bits, registers or I/O lines. The following conditions restart the CPU clock and bring the MCU out of the wait mode: • An external interrupt signal on the IRQ/VPP pin — A high to low transition on the IRQ/VPP pin loads the program counter with the contents of locations $1FFA and $1FFB. A programmable Timer interrupt — A programmable Timer interrupt driven by an input capture, output compare or timer overflow loads the program counter with the contents of locations $1FF6 and $1FF7. An SM-Bus interrupt — An SM-Bus interrupt driven by the completion of transmitted or received 8-bit data loads the program counter with the contents of locations $1FF4 and $1FF5. An analog subsystem interrupt — An analog subsystem interrupt driven by a voltage comparison loads the program counter with the contents of locations $1FF2 and $1FF3. A Core Timer interrupt — A Core Timer overflow or a real time interrupt loads the program counter with the contents of locations $1FF0 and $1FF1. A COP watchdog reset — A timeout of the COP watchdog resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. Software can enable real time interrupts so that the MCU can periodically exit the wait mode to reset the COP watchdog. External reset — A logic zero on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. • • • • • • 6.3 DATA-RETENTION MODE In the data retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 VDC. The data retention feature allows the MCU to remain in a low power consumption state during which it retains data, but the CPU cannot execute instructions. MOTOROLA 6-4 LOW POWER MODES MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION To put the MCU in the data retention mode: 1. Drive the RESET pin to a logic zero. 2. Lower the VDD voltage. The RESET pin must remain low continuously during data retention mode. To take the MCU out of the data retention mode: 1. Return VDD to normal operating voltage. 2. Return the RESET pin to a logic one. 6.4 SLOW MODE The Slow Mode feature permits a slow down of all the internal operations and thus reduces power consumption. It is particularly useful while going to the WAIT mode. Slow mode is enabled by setting the SCLK bit in the Miscellaneous Control Register ($0B). BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 U = UNAFFECTED BY RESET Figure 6-2. Miscellaneous Control Register (MCR) SCLK — Slow Clock Setting this bit to one will slow down the internal oscillator. Setting this bit to zero the system will run at the nominal bus speed (fosc/2). This bit is cleared during power-on or external reset. 1 = Slow clock selected: Internal operating frequency, fOP =fBUS =fOSC/1600. 0 = Normal clock selected: Internal operating frequency, fOP =fBUS =fOSC/2. MC68HC05SB7 REV 2.1 LOW POWER MODES MOTOROLA 6-5 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 6-6 LOW POWER MODES MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 7 INPUT/OUTPUT PORTS In normal operating mode there are 19 bidirectional I/O lines arranged as three I/ O ports (Port A, B and C). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). All port I/O pins can sink a current of 5mA when programmed as outputs. 7.1 PARALLEL PORTS Port A, B and C are bidirectional ports. Each port pin is controlled by the corresponding bits in a data direction register and a data register as shown in Figure 71. Read/Write DDR Data Direction Register Bit Write Data Data Register Bit OUTPUT I/O PIN Read Data Internal HC05 Data Bus Reset (RST) Figure 7-1. Port I/O Circuitry Table 7-1. I/O Pin Functions R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Functions The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read. MC68HC05SB7 REV 2.1 INPUT/OUTPUT PORTS MOTOROLA 7-1 GENERAL RELEASE SPECIFICATION August 27, 1998 7.1.1 Port Data Registers Each port I/O pin has a corresponding bit in the Port Data Register. When a port I/ O pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. All port I/O pins can sink a current of 5mA when programmed as outputs. When a port pin is programmed as an input, any read of the Port Data Register will return the logic state of the corresponding I/O pin. 7.1.2 Port Data Direction Registers Each port I/O pin may be programmed as an input by clearing the corresponding bit in the DDR, or programmed as an output by setting the corresponding bit in the DDR. NOTE A “glitch” can be generated on an I/O pin when changing it from an input to an output unless the data register is first preconditioned to the desired state before changing the corresponding DDR bit from a “0” to a “1”. Therefore, write data to the I/O Port Data Register before writing a “1” to the corresponding Data Direction Register. 7.2 PORT A Port A is an 8-bit bidirectional port with pins shared with the PWM outputs and SM-Bus serial I/Os. The Port A Data Register is at address $0000 and the Data Direction Register is at address $0004. 7.3 PORT B Port B is a 7-bit birdirectional port with pins shared with A/D converter inputs, current detect outputs, and the 16-bit timer TCAP input. The Port B Data Register is at address $0001 and the Data Direction Register is at address $0005. When selected by mask option, port pins PB2 and PB3 becomes OSC1 and OSC2 respectively. 7.4 PORT C Port C is a 4-bit bidirectional port. The Port C Data Register is at address $0002 and the Data Direction Register is at address $0006. MOTOROLA 7-2 INPUT/OUTPUT PORTS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 8 SYSTEM CLOCK This section describes the system clock options for the MC68HC05SB7. 8.1 CLOCK SOURCES The internal operating clock of the MC68HC05SB7 is derived from two possible clock sources: • External oscillator input via the OSC1 and OSC2 pins - this is enabled by a mask option on the MC68HC05SB7. (On the MC68HC705SB7, the OSCS bit in the Mask Option Register enables/disables external osc input option.) Internal VCO generated. • VCOEN SCLK VA0 VA1 VA2 VA3 VA4 VCO MUX ÷2 fOP I/O PORT OSC1 OSC OSC2 OSCS Figure 8-1. MC68HC05SB7 Input Clock Source MC68HC05SB7 REV 2.1 SYSTEM CLOCK MOTOROLA 8-1 GENERAL RELEASE SPECIFICATION August 27, 1998 The clock source is selected by the VCOEN bit in the IRQ Status and Control Register at $0D. Table 8-1 shows a summary of the clock source selection. BIT 7 ISCR $000D reset: R W IRQE 1 BIT 6 VCOEN 1 BIT 5 LEVEL 0 BIT 4 0 0 BIT 3 IRQF 0 BIT 2 0 0 BIT 1 0 IRQR 0 0 BIT 0 0 Figure 8-2. IRQ Status and Control Register (ISCR) VCOEN — VCO ENable 1 = Internal VCO is used as clock source for the MCU. This is the default setting after a reset. 0 = External OSC is used as clock source for the MCU. If external OSC is disabled (mask option or MOR in MC68HC705SB7), the internal VCO is used as clock source. After a POR or reset, the internal VCO is selected as the default clock source. . Table 8-1. Clock Source Selection External OSC Enabled (Mask Option) Disabled (OSCS=0 in MC68HC705SB7) Internal VCO Enabled Don’t care (VCOEN=X) Disabled (VCOEN=0) Enabled (VCOEN=1) Clock Source Selected Internal External Internal Enabled (OSCS=1 in MC68HC705SB7) Enabled (OSCS=1 in MC68HC705SB7) NOTE The user must ensure that the oscillators are stable (4096 clock cycles minimum) if switching between internal and external oscillators. 8.2 VCO CLOCK SPEED 8.2.1 VCO Slow Mode The internal VCO has two operating modes: Normal mode and Slow mode. In Normal mode, the VCO frequency ranges from 1.5MHz to 5.8MHz. In Slow mode, the VCO frequency ranges from 500Hz to 4kHz. This clock speed option is selected by setting the SCLK bit in the Miscellaneous Register at $0B. The default setting at reset is Normal mode. MOTOROLA 8-2 SYSTEM CLOCK MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 U = UNAFFECTED BY RESET Figure 8-3. Miscellaneous Control Register (MCR) SCLK — Slow CLocK 1 = Slow clock selected – VCO frequency: 500Hz to 4kHz. 0 = Normal clock selected – VCO frequency: 1.5MHz to 5.8MHz. NOTE Due to process variations, operating voltages, and temperature requirements, the quoted VCO frequencies are typical limits, and should be treated as references only. It is the user’s responsibility to ensure that the resulting internal operating frequency meets user’s requirement by setting the appropriate value in the VCO Adjust Register. See below. 8.2.2 Setting the VCO Speed The speed of the internal VCO can be adjusted by configuring five bits in the VCO Adjust Register (VAR) as shown in Figure 8-4. Setting VAR=11111 will select the VCO minimum frequency, and VAR=00000 will select the maximum frequency. On reset, VAR=10000, which selects the mid-frequency. For Normal mode, when VAR=10000, VCO frequency is typically 2kHz. For Slow mode, when VAR=10000, VCO frequency is typically 3.4MHz. BIT 7 VAR $000C reset: R W 0 0 0 0 BIT 6 0 BIT 5 0 BIT 4 VA4 1 BIT 3 VA3 0 BIT 2 VA2 0 BIT 1 VA1 0 BIT 0 VA0 0 U = UNAFFECTED BY RESET Figure 8-4. VCO Adjust Register (VAR) The VCO minimum and maximum frequencies are available preprogrammed as two 16-bit values in the Personality EPROM (PEPROM). Bit locations $00 to $0F holds the minimum value, and $10 to $1F holds the maximum value. See section on Personality EPROM for further details. MC68HC05SB7 REV 2.1 SYSTEM CLOCK MOTOROLA 8-3 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 8-4 SYSTEM CLOCK MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 9 CORE TIMER This section describes the operation of the Core Timer and the Computer Operating Properly (COP) watchdog timer. Figure 9-1 shows a block diagram of the Core Timer. RESET INTERNAL CLOCK (fOP) OVERFLOW $0009 CORE TIMER COUNTER REGISTER BITS 0–7 OF 15-STAGE RIPPLE (COUNT-UP) COUNTER ÷4 ÷2 OSC1 (fOSC) fOP ÷ 1024 INTERNAL DATA BUS CORE TIMER INTERRUPT REQUEST CTOFR CTOFE $0008 CORE TIMER STATUS/CONTROL REGISTER RT1 RT0 RTIFR CTOF RTIE RTIF RESET RTI RATE SELECT $1FF0 COP REGISTER fOP ÷ 217 ÷2 COPC fOP ÷ 216 ÷2 fOP ÷ 215 ÷2 fOP ÷ 214 ÷2 ÷2 ÷2 ÷2 POWER-ON RESET ÷2 ÷2 ÷2 ÷2 S Q COP WATCHDOG RESET R RESET Figure 9-1. Core Timer Block Diagram MC68HC05SB7 REV 2.1 CORE TIMER MOTOROLA 9-1 GENERAL RELEASE SPECIFICATION August 27, 1998 9.1 CORE TIMER STATUS AND CONTROL REGISTER The read/write Core Timer status and control register contains the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and the rate selects for the real time interrupt as shown in Figure 9-2. BIT 7 CTSCR $0008 reset: R W 0 0 CTOF BIT 6 RTIF BIT 5 CTOFE 0 BIT 4 RTIE 0 BIT 3 0 CTOFR 0 BIT 2 0 RTIFR 0 BIT 1 RT1 1 BIT 0 RT0 1 Figure 9-2. Core Timer Status and Control Register (CTSCR) CTOF — Core Timer Overflow Flag This read only flag becomes set when the first eight stages of the Core Timer counter roll over from $FF to $00. The CTOF flag bit generates a timer overflow interrupt request if CTOFE is also set. The CTOF flag bit is cleared by writing a logic one to the CTOFR bit. Writing to CTOF has no effect. Reset clears CTOF. 1 = Overflow in Core Timer has occurred. 0 = No overflow of Core Timer since CTOF last cleared. RTIF — Real Time Interrupt Flag This read only flag becomes set when the selected RTI output becomes active. RTIF generates a real time interrupt request if RTIE is also set. The RTIF enable bit is cleared by writing a logic one to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF. 1 = Overflow in real time counter has occurred. 0 = No overflow of real time counter since RTIF last cleared. CTOFE — Core Timer Overflow Interrupt Enable This read/write bit enables Core Timer overflow interrupts. Reset clears CTOFE. 1 = Core Timer overflow interrupts enabled. 0 = Core Timer overflow interrupts disabled. RTIE — Real-Time Interrupt Enable This read/write bit enables real time interrupts. Reset clears RTIE. 1 = Real-time interrupts enabled. 0 = Real-time interrupts disabled. CTOFR — Core Timer Overflow Flag Reset Writing a logic one to this write only bit clears the CTOF bit. CTOFR always reads as a logic zero. Reset does not affect CTOFR. 1 = Clear CTOF flag bit. 0 = No effect on CTOF flag bit. MOTOROLA 9-2 CORE TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION RTIFR — Real-Time Interrupt Flag Reset Writing a logic one to this write only bit clears the RTIF bit. RTIFR always reads as a logic zero. Reset does not affect RTIFR. 1 = Clear RTIF flag bit. 0 = No effect on RTIF flag bit. RT1, RT0 — Real-Time Interrupt Select Bits 1 and 0 These read/write bits select one of four real time interrupt rates, as shown in Table 9-1. Because the selected RTI output drives the COP watchdog, changing the real time interrupt rate also changes the counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout period and real-time interrupt period. NOTE Changing RT1 and RT0 when a COP timeout is imminent or uncertain may cause a real time interrupt request to be missed or an additional real time interrupt request to be generated. Therefore, the COP timer should be cleared (by writing a just before changing RT1 and RT0. Table 9-1. Core Timer Interrupt Rates and COP Timeout Selection Timer Overflow Interrupt (TOF) Period (fOP ÷ 210) fOP = 2.1 MHz fOP = 1.0 MHz 0 488 µs 1024 µs 0 1 1 0 1 0 1 fOP ÷ 214 fOP ÷ fOP ÷ 215 216 RT1 RT0 RTI Rate Real-Time Interrupt (RTI) Period fOP = 2.1 MHz 7.81 ms 15.6 ms 31.3 ms 62.5 ms Minimum COP Timeout Period (7 or 8 RTI Periods) fOP = 2.1 MHz 54.7 ms 109 ms 219 ms 438 ms fOP = 1.0 MHz 16.4 ms 32.8 ms 65.5 ms 131 ms fOP = 1.0 MHz 114 ms 229 ms 458 ms 916 ms fOP ÷ 217 9.2 CORE TIMER COUNTER REGISTER (CTCR) A 15-stage ripple counter is the basis of the Core Timer. The value of the first eight stages is readable at any time from the read only timer counter register as shown in Figure 9-2. BIT 7 CTCR $0009 reset: R W 0 0 0 0 0 0 0 0 TMR7 BIT 6 TMR6 BIT 5 TMR5 BIT 4 TMR4 BIT 3 TMR3 BIT 2 TMR2 BIT 1 TMR1 BIT 0 TMR0 Figure 9-3. Core Timer Counter Register (CTCR) MC68HC05SB7 REV 2.1 CORE TIMER MOTOROLA 9-3 GENERAL RELEASE SPECIFICATION August 27, 1998 Power on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or 4064 internal clock cycles) the power on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset. Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal clock. A timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles. 9.3 COP WATCHDOG Four counter stages at the end of the Core Timer make up the computer operating properly (COP) watchdog. The COP watchdog timeout period is shown in Table 91. A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic “0” to the COPC bit of the COP register at location $1FF0. BIT 7 COPR $1FF0 reset: R W U U U U U U U 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 COPC 0 U = UNAFFECTED BY RESET Figure 9-4. COP Watchdog Register (COPR) COPC — COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = No effect on system. 0 = Reset COP watchdog timer. The COP Watchdog reset will assert the pulldown device to pull the RESET pin low for three to four clock cycles of the internal bus clock. After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic “1” to the COPON bit in the Miscellaneous Control Register (see Figure 9-5). Once enabled, the COP watchdog can only be disabled by a POR or reset. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 U = UNAFFECTED BY RESET Figure 9-5. Miscellaneous Control Register (MCR) MOTOROLA 9-4 CORE TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION COPON — COP ON COPON is a write-once bit. 1 = Enables COP watchdog system. 0 = No effect on system. NOTE If the voltage on the IRQ/VPP pin exceeds 2 × VDD, the COP watchdog is disabled, and remains disabled until the IRQ/VPP voltage falls below 2 × VDD. 9.4 CORE TIMER DURING WAIT MODE The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. 9.5 CORE TIMER DURING STOP MODE The Core Timer is cleared when going into STOP mode. When STOP is exited by an external interrupt or an external RESET, the internal oscillator will resume, followed by 4064 cycles internal processor stabilization delay. The timer is then cleared and operation resumes. MC68HC05SB7 REV 2.1 CORE TIMER MOTOROLA 9-5 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 9-6 CORE TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 10 16-BIT TIMER The MC68HC05SB7 MCU contains a 16-bit programmable Timer with an Input Capture function and an Output Compare function. Figure 10-1 shows a block diagram of the 16-bit programmable timer. PB1 TCAP INPUT SELECT MUX EDGE SELECT & DETECT LOGIC ICF ICRH ($0014) ICRL ($0015) SCL OF SMBUS CPF FLAG BIT (from analog subsystem) IEDG TMRH ($0018) TMRL ($0019) ACRH ($001A) ACRL ($001B) 16-BIT COUNTER OVERFLOW (TOF) ICEN (bit 4 of $1D) TCSEL (bit 2 of $0B) ÷4 INTERNAL CLOCK (fOSC ÷ 2) TCMP 16-BIT COMPARATOR DQ OCRH ($0016) OCRL ($0017) OLVL C OCF TIMER INTERRUPT REQUEST RESET OLVL IEDG OCIE TOIE OCF TOF ICIE ICF TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS TIMER STATUS REGISTER $0013 Figure 10-1. Programmable Timer Block Diagram MC68HC05SB7 REV 2.1 16-BIT TIMER MOTOROLA 10-1 GENERAL RELEASE SPECIFICATION August 27, 1998 The basis of the capture/compare Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers. Each register pair contains the high and low byte of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4 MHz crystal oscillator is 2 microsecond/count. The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012 and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013. 10.1 TIMER REGISTERS (TMRH, TMRL) The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in Figure 10-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter. LATCH TMRL ($0019) READ TMRL READ TMRH RESET READ ($FFFC) TMRH ($0018) TMR LSB ÷4 INTERNAL CLOCK (fOSC ÷ 2) TIMER INTERRUPT REQUEST TOF TIMER STATUS REG. $0013 INTERNAL DATA BUS 16-BIT COUNTER OVERFLOW (TOF) TIMER CONTROL REG. $0012 Figure 10-2. Programmable Timer Block Diagram MOTOROLA 10-2 TOIE 16-BIT TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION The timer registers (TMRH, TMRL) shown in Figure 10-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. BIT 7 TMRH $0018 reset: TMRL $0019 reset: R W 1 1 1 1 1 1 0 0 R W 1 TMRL7 1 TMRL6 1 TMRL5 1 TMRL4 1 TMRL3 1 TMRL2 1 TMRL1 1 TMRL0 TMRH7 BIT 6 TMRH6 BIT 5 TMRH5 BIT 4 TMRH4 BIT 3 TMRH3 BIT 2 TMRH2 BIT 1 TMRH1 BIT 0 TMRH0 Figure 10-3. Programmable Timer Registers (TMRH, TMRL) The TMRL latch is a transparent read of the LSB until the a read of the TMRH takes place. A read of the TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains fixed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when reading the MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR. Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of times does not have any effect on the 16-bit free-running counter. NOTE To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL. MC68HC05SB7 REV 2.1 16-BIT TIMER MOTOROLA 10-3 GENERAL RELEASE SPECIFICATION August 27, 1998 10.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 10-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF flag bit and Timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter. INTERNAL DATA BUS LATCH ACRL ($001B) READ ACRL READ ACRH RESET READ ($FFFC) ACRH ($001A) TMR LSB ÷4 INTERNAL CLOCK (fOSC ÷ 2) 16-BIT COUNTER Figure 10-4. Alternate Counter Block Diagram The alternate counter registers (ACRH, ACRL) shown in Figure 10-5 are readonly locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC. BIT 7 ACRH $001A reset: ACRL $001B reset: R W 1 1 1 1 1 1 0 0 R W 1 ACRL7 1 ACRL6 1 ACRL5 1 ACRL4 1 ACRL3 1 ACRL2 1 ACRL1 1 ACRL0 ACRH7 BIT 6 ACRH6 BIT 5 ACRH5 BIT 4 ACRH4 BIT 3 ACRH3 BIT 2 ACRH2 BIT 1 ACRH1 BIT 0 ACRH0 Figure 10-5. Alternate Counter Registers (ACRH, ACRL) The ACRL latch is a transparent read of the LSB until the a read of the ACRH takes place. A read of the ACRH latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF flag bit. MOTOROLA 10-4 16-BIT TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION NOTE To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL. 10.3 INPUT CAPTURE REGISTERS INTERNAL DATA BUS READ ICRH PB1 TCAP INPUT SELECT MUX EDGE SELECT & DETECT LOGIC ($FFFC) IEDG LATCH ICRH ($0014) ICRL ($0015) READ ICRL ÷4 INTERNAL CLOCK (fOSC ÷ 2) TIMER INTERRUPT REQUEST SCL CPF OF FLAG SMBUS BIT TCSEL (bit 2 of $0B) 16-BIT COUNTER INPUT CAPTURE (ICF) ICIE RESET ICF TIMER STATUS REG. $0013 INTERNAL DATA BUS ICEN (bit 4 of $1D) TIMER CONTROL REG. $0012 Figure 10-6. Timer Input Capture Block Diagram The input capture function is a means to record the time at which an event occurs. The source of the event can be selected from the following: • • • External input via the PB1 pin CPF flag from the voltage comparator in the analog subsystem SCL signal from the SMBUS The input capture source is selected by the TCSEL and ICEN bits. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 Figure 10-7. Miscellaneous Control Register (MCR) MC68HC05SB7 REV 2.1 16-BIT TIMER IEDG MOTOROLA 10-5 GENERAL RELEASE SPECIFICATION August 27, 1998 BIT 7 ACR $001D reset: R W CHG 0 BIT 6 ATD2 0 BIT 5 ATD1 0 BIT 4 ICEN 0 BIT 3 CPIE 0 BIT 2 CPEN 0 BIT 1 BIT 0 ISEN 0 0 Figure 10-8. Analog Control Register (ACR) Table 10-1. 16-bit Timer Input Capture Source TCSEL 0 0 1 1 ICEN 0 1 0 1 Selected TCAP Source External TCAP via PB1 CPF from Analog Subsystem SCL from SMBus SCL from SMBus When the input capture circuitry detects an active edge on the selected source, it latches the contents of the free-running timer counter registers into the input capture registers as shown in Figure 10-6. Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. The input capture registers are made up of two 8-bit read-only registers (ICRH, ICRL) as shown in Figure 10-9. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The edge that triggers the counter transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not affect the contents of the input capture registers. The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). BIT 7 ICRH $0014 reset: ICRL $0015 reset: R W U U U U U U U U R W U ICRL7 U ICRL6 U ICRL5 U ICRL4 U ICRL3 U ICRL2 U ICRL1 U ICRL0 ICRH7 BIT 6 ICRH6 BIT 5 ICRH5 BIT 4 ICRH4 BIT 3 ICRH3 BIT 2 ICRH2 BIT 1 ICRH1 BIT 0 ICRH0 U = UNAFFECTED BY RESET Figure 10-9. Input Capture Registers (ICRH, ICRL) MOTOROLA 10-6 16-BIT TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Reading the ICRH inhibits further captures until the ICRL is also read. Reading the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does not inhibit transfer of the free-running counter. There is no conflict between reading the ICRL and transfers from the free-running timer counters. The input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. NOTE To prevent interrupts from occurring between readings of the ICRH and ICRL, set the I bit in the condition code register (CCR) before reading ICRH and clear the I bit after reading ICRL. 10.4 OUTPUT COMPARE REGISTERS R/W OCRH OCRH ($0016) OCRL ($0017) EDGE SELECT DETECT LOGIC ÷4 R/W OCRL 16-BIT COMPARATOR OLVL TCMP ($FFFC) 16-BIT COUNTER OUTPUT COMPARE (OCF) INTERNAL CLOCK (fOSC ÷ 2) TIMER INTERRUPT REQUEST OLVL OCIE RESET TIMER CONTROL REG. $0012 OCF TIMER STATUS REG. $0013 INTERNAL DATA BUS Figure 10-10. Timer Output Compare Block Diagram The Output Compare function is a means of generating an output signal when the 16-bit timer counter reaches a selected value as shown in Figure 10-10. Software writes the selected value into the output compare registers. On every fourth internal clock cycle (every eight oscillator clock cycle) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. When a match occurs, the timer transfers the output level (OLVL) from the timer control register (TCR) to the TCMP. MC68HC05SB7 REV 2.1 16-BIT TIMER MOTOROLA 10-7 GENERAL RELEASE SPECIFICATION August 27, 1998 Software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the TCMP. The planned action on the TCMP depends on the value stored in the OLVL bit in the TCR, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in Figure 10-3. These registers are read/write bits and are unaffected by reset. Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TSR will clear the output compare flag bit (OCF). The output compare OLVL state will be clocked to its output latch regardless of the state of the OCF. BIT 7 OCRH $0016 reset: OCRL $0017 reset: R W R W OCRH7 U BIT 6 OCRH6 U BIT 5 OCRH5 U BIT 4 OCRH4 U BIT 3 OCRH3 U BIT 2 OCRH2 U BIT 1 OCRH1 U BIT 0 OCRH0 U OCRL7 U OCRL6 U OCRL5 U OCRL4 U OCRL3 U OCRL2 U OCRL1 U OCRL0 U U = UNAFFECTED BY RESET Figure 10-11. Output Compare Registers (OCRH, OCRL) To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use the following procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to the OCRH. Compares are now inhibited until OCRL is written. 3. Read the TSR to arm the OCF for clearing. 4. Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register. A software example of this procedure is shown below. 9B ... ... B7 B6 BF ... ... 9A SEI ... ... STA LDA STX ... ... CLI DISABLE INTERRUPTS ..... ..... INHIBIT OUTPUT COMPARE ARM OCF FLAG FOR CLEARING READY FOR NEXT COMPARE, OCF CLEARED ..... ..... ENABLE INTERRUPTS 16 13 17 OCRH TSR OCRL MOTOROLA 10-8 16-BIT TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 10.5 TIMER CONTROL REGISTER (TCR) The timer control register is shown in Figure 10-12 performs the following functions: • • • • • Enables input capture interrupts. Enables output compare interrupts. Enables timer overflow interrupts. Control the active edge polarity of the TCAP signal. Controls the active level of the TCMP output. Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected. BIT 7 TCR $0012 reset: R W ICIE 0 BIT 6 OCIE 0 BIT 5 TOIE 0 BIT 4 0 0 BIT 3 0 0 BIT 2 0 0 BIT 1 IEDG Unaffected BIT 0 OLVL 0 Figure 10-12. Timer Control Register (TCR) ICIE - INPUT CAPTURE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the PB1/ TCAP pin or from CPF flag bit of the analog subsystem voltage comparator. Reset clears the ICIE bit. 1 = Input capture interrupts enabled. 0 = Input capture interrupts disabled. OCIE - OUTPUT COMPARE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the TCMP pin. Reset clears the OCIE bit. 1 = Output compare interrupts enabled. 0 = Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. 1 = Timer overflow interrupts enabled. 0 = Timer overflow interrupts disabled. IEDG - INPUT CAPTURE EDGE SELECT The state of this read/write bit determines whether a positive or negative transition on the TCAP pin or the CPF flag bit of voltage comparator in the analog subsystem triggers a transfer of the contents of the timer register to the input capture register. Reset has no effect on the IEDG bit. 1 = Positive edge (low to high transition) triggers input capture. 0 = Negative edge (high to low transition) triggers input capture. MC68HC05SB7 REV 2.1 16-BIT TIMER MOTOROLA 10-9 GENERAL RELEASE SPECIFICATION August 27, 1998 OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT The state of this read/write bit determines whether a logic one or a logic zero appears on the TCMP when a successful output compare occurs. Reset clears the OLVL bit. 1 = TCMP goes high on output compare. 0 = TCMP goes low on output compare. 10.6 TIMER STATUS REGISTER (TSR) The timer status register (TSR) shown in Figure 10-13 contains flags for the following events: • An active signal on the PB1/TCAP pin or the CPF flag bit of voltage comparator in the analog subsystem, transferring the contents of the timer registers to the input capture registers. A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the TCMP. An overflow of the timer registers from $FFFF to $0000. • • Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits in the TSR. BIT 7 TSR $0013 reset: R W U U U 0 0 0 0 0 ICF BIT 6 OCF BIT 5 TOF BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 U = UNAFFECTED BY RESET Figure 10-13. Timer Status Registers (TSR) ICF - INPUT CAPTURE FLAG The ICF bit is automatically set when an edge of the selected polarity occurs on the PB1/TCAP pin. Clear the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL, $0015) of the input capture registers. Reset has no effect on ICF. OCF - OUTPUT COMPARE FLAG The OCF bit is automatically set when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with the OCF set, and then accessing the low byte (OCRL, $0017) of the output compare registers. Reset has no effect on OCF. TOF - TIMER OVERFLOW FLAG The TOF bit is automatically set when the 16-bit timer counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with the TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers. Reset has no effect on TOF. MOTOROLA 10-10 16-BIT TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 10.7 TIMER OPERATION DURING WAIT MODE During WAIT mode the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the WAIT mode. 10.8 TIMER OPERATION DURING STOP MODE When the MCU enters the STOP mode the free-running counter stops counting (the internal processor clock is stopped). It remains at that particular count value until the STOP mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If STOP mode is exited via an external reset (logic low applied to the RESET pin) the counter is forced to $FFFC. If a valid input capture edge occurs at the PB1/TCAP pin during the STOP mode the input capture detect circuitry will be armed. This action does not set any flags or “wake up” the MCU, but when the MCU does “wake up” there will be an active input capture flag (and data) from the first valid edge. If the STOP mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during the STOP mode. MC68HC05SB7 REV 2.1 16-BIT TIMER MOTOROLA 10-11 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 10-12 16-BIT TIMER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 11 PULSE WIDTH MODULATOR The PWM subsystem contains four 10-bit PWM channels, which can be used as independent D/A converters. Figure 11-1 shows the block diagram for the Pulse Width Modulator, with channel 0 in details. Internal Bus Channel 0 10-bit D/A 0 Data Register 10-bit Counter fOP ÷ 2 10-bit D/A 0 Data Register Buffer D/A 0 Multiplexer To Channel 1 To Channel 2 To Channel 3 Comparator Zero Detector S Latch R PWM0 pin Figure 11-1. PWM Block Diagram The PWM cycle time is 2048 times the MCU internal processor clock (fOP or fBUS). Duty cycle of the PWM outputs can be programmed by the corresponding D/A Data Registers (DAC0-DAC3). MC68HC05SB7 REV 2.1 PULSE WIDTH MODULATOR MOTOROLA 11-1 GENERAL RELEASE SPECIFICATION August 27, 1998 11.1 D/A DATA REGISTERS (DAC0-DAC3) Each PWM channel is programmed with a 10-bit data, in two 8-bit registers. BIT 7 DAC0 $0025 reset: R W D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-2. D/A Data Register 0 (DAC0) (MSB) BIT 7 DAC0 $0026 reset: R W 0 0 0 0 0 0 D1 0 D0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-3. D/A Data Register 0 (DAC0) (LSB) BIT 7 DAC1 $0027 reset: R W D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-4. D/A Data Register 1 (DAC1) (MSB) BIT 7 DAC1 $0028 reset: R W 0 0 0 0 0 0 D1 0 D0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-5. D/A Data Register 1 (DAC1) (LSB) BIT 7 DAC2 $0029 reset: R W D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-6. D/A Data Register 2 (DAC2) (MSB) BIT 7 DAC2 $002A reset: R W 0 0 0 0 0 0 D1 0 D0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-7. D/A Data Register 2 (DAC2) (LSB) MOTOROLA 11-2 PULSE WIDTH MODULATOR MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION BIT 7 DAC3 $002B reset: R W D9 0 BIT 6 D8 0 BIT 5 D7 0 BIT 4 D6 0 BIT 3 D5 0 BIT 2 D4 0 BIT 1 D3 0 BIT 0 D2 0 Figure 11-8. D/A Data Register 3 (DAC3) (MSB) BIT 7 DAC3 $002C reset: R W 0 0 0 0 0 0 D1 0 D0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Figure 11-9. D/A Data Register 3 (DAC3) (LSB) A value of $0000 loaded into these registers results in a continuously low output on the corresponding PWM output pin. A value of $0200 results in a 50% duty cycle output, and so on. The maximum value, $03FF corresponds to an output which is at “1” for 1023/1024 of the cycle. 1024T $000 1023T $001 512T $200 1023T $3FF T = 2 x tCYC 512T Figure 11-10. PWM Output Waveform Examples A new value written to the a D/A register pair will not be effective until the end of the current PWM period. This provides a monotonic change of the DC component of the output without overshoots or vicious starts (a vicious start is an output which gives totally erroneous PWM during the initial period following an update of the PWM registers). This feature is achieved by double buffering of the PWM D/A registers. 11.2 MUX CHANNEL ENABLE REGISTER (MCER) Since the PWM output pins PWM0-PWM3 are multiplexed with the standard I/O port pins PA0-PA3 respectively, the MCER is provided to switch between the PWM and standard I/O function for each pin. MC68HC05SB7 REV 2.1 PULSE WIDTH MODULATOR MOTOROLA 11-3 GENERAL RELEASE SPECIFICATION August 27, 1998 Each PWM channel is enabled by setting the corresponding DAn-E bit in the MCER, shown in Figure 11-11. With a PWM output enabled, the corresponding port I/O is tri-stated automatically. Reset clears the four DAn-E bits. The outputs from four channels PWM system can be inhibited by setting the PWM_I bit in MCER. This bit can be used as a global pull logic “0” for all the enabled DA’s line before enter STOP mode. The PWM_I bit is also used to disable the counter while the PWM is not in use for power saving. Reset clears this bit. BIT 7 MCER $002D reset: R W PWM_I 0 BIT 6 0 0 BIT 5 0 0 BIT 4 0 0 BIT 3 DA3-E 0 BIT 2 DA2-E 0 BIT 1 DA1-E 0 BIT 0 DA0-E 0 Figure 11-11. MUX Channel Enable Register (MCER) DAn-E — D/A Channel n Enable 1 = PWM output selected for PWMn/PAn pin. 0 = Standard I/O selected for PWMn/PAn pin. PWM_I — PWM Inhibit 1 = Inhibit all four PWM channels; PWM 10-bit counter also stopped. 0 = PWM channels not inhibited. 11.3 PWM DURING WAIT MODE In WAIT mode, the oscillator is running even though the MCU clock is not present, the PWM outputs are not affected. To reduce power consumption in WAIT mode, it is recommended to disable the PWM. 11.4 PWM DURING STOP MODE In STOP mode, the oscillator is stopped asynchronously with PWM operation. As a consequence, the PWM output will remain at the state at the moment when the oscillator is stopped. The PWM pin’s output depended on the state of PWM_I bit. If this bit is clear, it might be at its high or low state at that moment, and it remains at that state until STOP mode is exited. If the PWM_I bit is set, it will be inhibited the state of PWM output in the process and pin output will be in logic low state. After STOP mode is exited, the PWM output resumes its unfinished portion of the stopped cycle if PWM_I bit is clear by software. MOTOROLA 11-4 PULSE WIDTH MODULATOR MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 12 SM-BUS 12.1 SM-BUS INTRODUCTION The System Management Bus (SM-Bus) is a two wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. This bus is suitable for applications which need frequent communications over a short distance between a number of devices. It also provides a flexibility that allows additional devices to be connected to the bus. The maximum data rate is 100kbit/s, and the maximum communication distance and number of devices that can be connected is limited by a maximum bus capacitance of 400pF. The SM-Bus is a true multi-master bus, including collision detection and arbitration to prevent data corruption if two or more masters intend to control the bus simultaneously. This feature provides the capability for complex applications with multi-processor control. It may also be used for rapid testing and alignment of end products via external connections to an assembly-line computer. Figure 12-1 shows a block diagram of the SM-Bus interface. 12.2 SM-BUS INTERFACE FEATURES • • • • • • • • • • • Fully compatible to SM-Bus standard Multi-master operation Software programmable for one of 32 different serial clock frequencies Software selectable acknowledge bit Interrupt driven byte by byte data transfer Arbitration lost driven interrupt with automatic mode switching from master to slave Calling address identification interrupt Generate/detect the START or STOP signal Repeated START signal generation Generate/recognize the acknowledge bit Bus busy detection MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-1 GENERAL RELEASE SPECIFICATION August 27, 1998 Internal bus 8 Control register SMEN SMIEN SMSTA SMTX TXAK Status register SMCF SMAAS SMBB SMAL SRW SMIF SRXAK Frequency divider register Address register Interrupt M-Bus interrupt Address comparator SCL SCL control M-Bus clock generator sync logic TX shift register RX shift register START, STOP detector and arbitration START, STOP generator and timing sync TX control RX control SDA SDA control Figure 12-1. SM-Bus Interface Block Diagram 12.3 SM-BUS SYSTEM CONFIGURATION The SM-Bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs and the logical “AND” function is performed on both lines by two pull up resistors. 12.4 SM-BUS PROTOCOL Normally a standard communication is composed of four parts, START signal, Slave Address transmission, Data transfer, and STOP signal. These are described briefly in the following sections and illustrated in Figure 12-2. MOTOROLA 12-2 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION MSB SCL 1 1 0 0 0 0 1 LSB 1 Acknowledge bit MSB 1 1 0 0 0 0 1 LSB 1 No acknowledge SDA START signal STOP signal MSB SCL 1 1 0 0 0 0 1 LSB 1 Acknowledge bit MSB 1 1 0 0 0 0 1 LSB 1 No acknowledge SDA START signal STOP signal repeated START signal Figure 12-2. SM-Bus Transmission Signal Diagram 12.4.1 START Signal When the bus is free, (i.e. no master device is engaging the bus and both SCL and SDA lines are at logical high) a master may initiate communication by sending a START signal. As shown in Figure 12-2, a START signal is defined as a high to low transition of SDA while SCL is high. This signal denotes the beginning of new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. 12.4.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the Master. This is a seven bit long calling address followed by a R/W-bit. The R/W-bit tells the slave the desired direction of data transfer. Only the slave with a matched address will respond by sending back an acknowledge bit by pulling SDA low on the 9th clock cycle. (See Figure 12-2) 12.4.3 Data Transfer Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the direction specified by the R/W- bit sent by the calling master. MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-3 GENERAL RELEASE SPECIFICATION August 27, 1998 Each data byte is 8 bits long. Data can be changed only when SCL is low and must be held stable when SCL high as shown in Figure 12-2. The MSB is transmitted first and each byte has to be followed by an acknowledge bit. This is signalled by the receiving device by pulling the SDA low on the 9th clock cycle. Therefore one complete data byte transfer needs 9 clock cycles. If the slave receiver does not acknowledge the master, the SDA line should be left high by the slave. The master can then generate a STOP signal to abort the data transfer or a START signal (repeated start) to commence a new transfer. If the master receiver does not acknowledge the slave transmitter after a byte has been transmitted, it means an “end of data” to the slave. The slave should now release the SDA line for the master to generate a “STOP” or “START” signal. 12.4.4 Repeated START Signal As shown in Figure 12-2, a repeated START signal is used to generate a START signal without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 12.4.5 STOP Signal With reference to Figure 12-2, the master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without first generating a STOP signal. This is called repeat start. A STOP signal is defined as a low to high transition of SDA while SCL is at logical high. 12.4.6 Arbitration Procedure This interface circuit is a true multi-master system which allows more than one master to be connected to it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. A data arbitration procedure determines the priority. The masters will lose arbitration if they transmit logic “1” while another transmits logic “0”. The losing masters will immediately switch over to slave receive mode and stop its data and clock outputs. The transition from master to slave mode will not generate a STOP condition in this case. Meanwhile a software bit will be set by hardware to indicate loss of arbitration. MOTOROLA 12-4 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 12.4.7 Clock Synchronization Start counting high period WAIT SCL1 SCL2 SCL Internal counter reset Figure 12-3. Clock Synchronization Since wired-AND logic is performed on SCL line, a high to low transition on the SCL line will affect the devices connected to the bus. The devices start counting their low period and once a device's clock has gone low, it will hold the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore the synchronized clock SCL will be held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (See Figure 12-2). When all devices concerned have counted off their low period, the synchronized SCL line will be released and go high. There will then be no difference between the device clocks and the state of the SCL line and all devices will start counting their high periods. The first device to complete its high period will again pull the SCL line low. 12.4.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte. In such cases the device will halt the bus clock and force the master clock into a wait state until the slave releases the SCL line. 12.5 SM-BUS REGISTERS There are five registers used in the SM-Bus interface. They are described in the following paragraphs. MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-5 GENERAL RELEASE SPECIFICATION August 27, 1998 12.5.1 SM-Bus Address Register (SMADR) BIT 7 SMADR $0020 reset: R W SMAD7 0 BIT 6 SMAD6 0 BIT 5 SMAD5 0 BIT 4 SMAD4 0 BIT 3 SMAD3 0 BIT 2 SMAD2 0 BIT 1 SMAD1 0 U BIT 0 SMAD1-SMAD7 are the slave address bits of the SM-Bus module. 12.5.2 SM-Bus Frequency Divider Register (SMFDR) BIT 7 SMFDR $0021 reset: R W U U U BIT 6 BIT 5 BIT 4 FD4 0 BIT 3 FD3 0 BIT 2 FD2 0 BIT 1 FD1 0 BIT 0 FD0 0 FD0-FD4 are used for clock rate selection. The serial bit clock frequency is equal to the CPU clock divided by the divider shown in Table 12-1. For a 4MHz external crystal operation (2MHz internal operating frequency), the serial bit clock frequency of the SM-Bus ranges from 460Hz to 90909Hz. After POR the clock rate is set to 90909Hz. Table 12-1. SM-Bus Clock Prescaler FD4, FD3, FD2, FD1, FD0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 DIVIDER 22 24 28 34 44 48 56 68 88 96 112 136 176 192 224 272 FD4,FD3, FD2, FD1, FD0 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 DIVIDER 352 384 448 544 704 768 896 1088 1408 1536 1792 2176 2816 3072 3584 4352 MOTOROLA 12-6 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 12.5.3 SM-Bus Control Register (SMCR) BIT 7 SMCR $0022 reset: R W SMEN 0 BIT 6 SMIEN 0 BIT 5 SMSTA 0 BIT 4 SMTX 0 BIT 3 TXAK 0 BIT 2 SMUX 0 U U BIT 1 BIT 0 SMEN — SM-Bus Enable If the SM-Bus enable bit (SMEN) is set, the SM-Bus interface system is enabled. If SMEN is cleared, the interface is reset and disabled. The SMEN bit must be set first before any bits of SMCR are set. 1 = SM-Bus enabled. 0 = SM-Bus disabled. SMIEN — SM-Bus Interrupt Enable If the SM-Bus interrupt enable bit (SMIEN) is set, the interrupt occurs provided the SMIF flag in the status register is set and the I-bit in the Condition Code Register is cleared. If SMIEN is cleared, the SM-Bus interrupt is disabled. 1 = SM-Bus interrupt enabled. 0 = SM-Bus interrupt disabled. SMSTA — Master/Slave Select Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operating mode changes from master to slave. In master mode, a bit clear immediately followed by a bit set of this bit generates a repeated START signal (see Figure 12-2) without generating a STOP signal. 1 = SM-Bus is set for master mode operation. 0 = SM-Bus is set for slave mode operation. SMTX — Transmit/Receive Mode Select This bit selects the SM-Bus to transmit or receive. 1 = SM-Bus is set for transmit mode. 0 = SM-Bus is set for receive mode. TXAK — Acknowledge Enable If the transmit acknowledge enable bit (TXAK) is cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data. When TXAK is set, no acknowledge signal response (i.e., acknowledge bit = 1). 1 = Do not send acknowledge signal. 0 = Send acknowledge signal at 9th clock bit. MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-7 GENERAL RELEASE SPECIFICATION August 27, 1998 SMUX — SM-Bus Channel Select The SMUX bit selects the channel for SM-Bus communications. 1 = Channel 1 (SDA1 and SCL1 pins) selected for SM-Bus. 0 = Channel 0 (SDA0 and SCL0 pins) selected for SM-Bus. 12.5.4 SM-Bus Status Register (SMSR) BIT 7 SMSR $0023 reset: R W 1 0 0 SMCF BIT 6 SMAAS BIT 5 SMBB BIT 4 SMAL SMAL clr 0 0 0 BIT 3 BIT 2 SRW BIT 1 SMIF SMIF clr 0 1 BIT 0 RXAK SMCF — SM-Bus Data Transfer Complete This bit indicates when a byte of data is being transmitted. When this bit is set, the SMIF is also set. An interrupt request to the CPU is generated if the SMIEN bit is also set. 1 = A byte transfer has been completed. 0 = A byte is being transferred. SMAAS — SM-Bus Addressed as Slave This bit is set when its own specific address (SMADR) matches the calling address. When this bit is set, the SMIF is also set. An interrupt request to the CPU is generated if the SMIEN bit is also set. Then CPU needs to check the SRW bit and set its SMTX bit accordingly. Writing to the SM-Bus Control Register clears this bit. 1 = Currently addressed as a slave. 0 = Not addressed. SMBB — SM-Bus Busy This bit indicates the status of the bus. When a START signal is detected, the SMBB is set. If a STOP signal is detected, it is cleared. 1 = SM-Bus busy. 0 = SM-Bus idle. SMAL — SM-Bus Arbitration Lost This bit is set by hardware when the arbitration procedure is lost during a master transmission. When this bit is set, the SMIF is also set. An interrupt request to the CPU is generated if the SMIEN bit is also set. This bit must be cleared by software. 1 = Lost arbitration in master mode. 0 = No arbitration lost. MOTOROLA 12-8 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SRW — Slave Read/Write Select When SMAAS is set, the R/W command bit of the calling address sent from master is latched into the R/W command bit (SRW). By checking this bit, the CPU can select slave transmit/receive mode according to the command of master. 1 = Read from slave, from calling master. 0 = Write to slave from calling master. SMIF — SM-Bus Interrupt Flag 1 = An SM-Bus interrupt has occurred. 0 = An SM-Bus interrupt has not occurred. This bit is set when one of the following events occur: – Transmission (either transmit or receive mode) of one byte completed. The bit is set at the falling edge of the 9th clock. – Receive a calling address which matches its own specific address in slave receive mode. – Arbitration lost. RXAK — Receive Acknowledge When this bit is “0”, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is “1”, it means no acknowledge signal is detected at the 9th clock. This bit is set upon reset. 1 = No acknowledgment signal detected. 0 = Acknowledgment signal detected after 8 bits data transmitted. MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-9 GENERAL RELEASE SPECIFICATION August 27, 1998 12.5.5 SM-Bus Data I/O Register (SMDR) BIT 7 SMDR $0024 reset: R W SMD7 0 BIT 6 SMD6 0 BIT 5 SMD5 0 BIT 4 SMD4 0 BIT 3 SMD3 0 BIT 2 SMD2 0 BIT 1 SMD1 0 BIT 0 SMD0 0 In master transmit mode, data written to this register is sent (MSB first) to the bus automatically. In master receive mode, reading from this register initiates receiving of the next byte of data. In slave mode, the same function is available after it is addressed. 12.5.6 SM-Bus logic Level Two choices of logic level is available for the SM-Bus: TTL or CMOS. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 Figure 12-4. Miscellaneous Control Register (MCR) SMINLEV — SM-Bus Input Level Select This read/write bit selects whether SM-Bus input level is TTL or CMOS. Reset clears the SMINLEV bit. 1 = TTL input level is selected. 0 = CMOS input level is selected. 12.5.7 SCL as16-bit Timer Input Capture The SCL signal can be routed to the 16-bit Timer Input Capture by setting the TCSEL bit in the Miscellaneous Control Register. TCSEL — 16-bit Timer Input Capture Source Select This read/write bit selects the input capture source to the 16-bit Timer. Reset clears TCSEL. 1 = SM-Bus SCL is routed to input capture of 16-bit Timer. 0 = CPF or external TCAP pin (depends on the state of ICEN bit in ACR, $1D) is routed to 16-bit Timer. See section Input Capture of 16-bit Timer for more details. MOTOROLA 12-10 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 12.6 PROGRAMMING CONSIDERATIONS 12.6.1 Initialization 1. Update Frequency Divider Register (FDR) to select a SCL frequency. 2. Update SM-Bus Address Register (SMADR) to define its own slave address. 3. Set SMEN bit of SM-Bus Control Register (SMCR) to enable the SMBus interface system. 4. Modify the bits of SM-Bus Control Register (SMCR) to select Master/ Slave mode, Transmit/Receive mode, interrupt enable or not. 12.6.2 Generation of a START Signal and the First Byte of Data Transfer After completion of the initialization procedure, serial data can be transmitted by selecting the “master transmitter” mode. If the device is connected to a multi-master bus system, the state of the SM-Bus busy bit (SMBB) must be tested to check whether the serial bus is free. If the bus is free (SMBB = 0), the start condition and the first byte (the slave address) can be sent. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below: SEI BRSET ; ; ; ; ; ; ; ; ; ; ; DISABLE INTERRUPT CHECK THE SMBB BIT OF THE STATUS REGISTER. IF IT IS SET, WAIT UNTIL IT IS CLEAR SET TRANSMIT MODE SET MASTER MODE i.e. GENERATE START CONDITION GET THE CALLING ADDRESS TRANSMIT THE CALLING ADDRESS ENABLE INTERRUPT CHFALG 5,SMSR,CHFLAG TXSTART BSET BSET LDA STA CLI 4,SMCR 5,SMCR #CALLING SMDR 12.6.3 Software Responses after Transmission or Reception of a Byte Transmission or reception of a byte will set the data transferring bit (SMCF) to 1, which indicates one byte communication is finished. Also, the SM-Bus interrupt bit (SMIF) is set to generate an SM-Bus interrupt if the interrupt function is enable during initialization. Software must clear the SMIF bit in the interrupt routine first. The SMCF bit will be cleared by reading from the SM-Bus DATA I/O Register (SMDR) in receive mode or writing to SMDR in transmit mode. Software may serve the SM-Bus I/O in the main program by monitoring the SMIF bit if the interrupt function is disabled. The following is an example of a software response by a “master transmitter” in the interrupt routine (see Figure 12-5). MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-11 GENERAL RELEASE SPECIFICATION August 27, 1998 CLEAR SMIF Y MASTER MODE N TX TX/RX RX Y ARBITRATION LOST N LAST BYTE TRANSMITTED Y LAST BYTE TO BE READ N Y CLEAR SMAL Y SMAAS = 1 N N N SMAAS = 1 Y RXAK=0 Y N LAST 2nd BYTE TO BE READ Y (READ) N SRW= 1 GENERATE STOP SIGNAL SET TX MODE N (WRITE) RX TX/RX TX READ SMDR AND STORE WRITE NEXT BYTE TO SMDR SET TXAK = 1 GENERATE STOP SIGNAL WRITE TO SMDR Y ACK FROM RECEIVER N TX NEXT BYTE SET RX MODE READ DATA FROM SMDR AND STORE SWITCH TO RX MODE DUMMY READ FROM SMDR DUMMY READ FROM SMDR RTI Figure 12-5. Flow-chart of SM-Bus Interrupt Routine MOTOROLA 12-12 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION ISR BCLR BRCLR BRCLR BRSET 1,SMSR 5,SMCR,SLAVE 4,SMCR,RECEIVE 0,SMSR,END TRANSMIT LDA STA DATABUF SMDR ; ; ; ; ; ; ; ; ; ; CLEAR THE SMIF FLAG CHECK THE SMSTA FLAG, BRANCH IF SLAVE MODE CHECK THE MODE FLAG, BRANCH IF IN RECEIVE MODE CHECK ACK FROM RECEIVER IF NO ACK, END OF TRANSMISSION GET THE NEXT BYTE OF DATA TRANSMIT THE DATA 12.6.4 Generation of the STOP Signal A data transfer ends with a STOP signal generated by the “master” device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter: MASTX BRSET LDA BEQ LDA STA DEC BRA BCLR RTI 0,SMSR,END TXCNT END DATABUF SMDR TXCNT EMASTX 5,SMCR ; ; ; ; ; ; ; ; ; ; ; IF NO ACK, BRANCH TO END GET VALUE FROM THE TRANSMITTING COUNTER IF NO MORE DATA, BRANCH TO END GET NEXT BYTE OF DATA TRANSMIT THE DATA DECREASE THE TXCNT EXIT GENERATE A STOP CONDITION RETURN FROM INTERRUPT END EMASTX If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. This can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver. MASR DEC BEQ LDA DECA BNE BSET BRA BCLR LDA STA RTI RXCNT ENMASR RXCNT ; LAST BYTE TO BE READ ; ; ; ; ; CHECK LAST 2ND BYTE TO BE READ NOT LAST ONE OR LAST SECOND LAST SECOND, DISABLE ACK TRANSMITTING LAMAR NXMAR 3,SMCR NXMAR 5,SMCR SMDR RXBUF ENMASR NXMAR ; LAST ONE, GENERATE “STOP” ; SIGNAL ; READ DATA AND STORE MC68HC05SB7 REV 2.1 SM-BUS MOTOROLA 12-13 GENERAL RELEASE SPECIFICATION August 27, 1998 12.6.5 Generation of a Repeated START Signal If at the end of data transfer the master still wants to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is shown below. RESTART BCLR BSET LDA STA 5,SMCR 5,SMCR #CALLING SMDR ; ; ; ; ; ANOTHER START (RESTART) IS GENERATED BY THESE TWO CONSEQUENCE INSTRUCTION GET THE CALLING ADDRESS TRANSMIT THE CALLING ADDRESS 12.6.6 Slave Mode In the slave service routine, the master addressed as slave bit (SMAAS) should be tested to see if a calling of its own address has just been received. If SMAAS is set, software should set the transmit/receive mode select bit (SMTX bit of SMCR) according to the R/W-command bit (SRW). Writing to the SMCR clears the SMAAS automatically. A data transfer may then be initiated by writing information to SMDR or dummy reading from SMDR. In the slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. If RXAK is set, indicating an “end of data” signal from the master receiver, then it must switch from transmitter mode to receiver mode by software and a dummy read must follow to release the SCL line so that the master can generate a stop signal. 12.6.7 Arbitration Lost If more than one master want to acquire the bus simultaneously, only one master wins and the others lost arbitration. The arbitration lost devices immediately switch to slave receive mode by hardware. Their data output to the SDA line is stopped, but internal transmitting clock still run until the end of the byte transmitting. An interrupt occurs when this dummy “byte” transmitting is accomplished with SMAL=1 and SMSTA = 0. If one master attempt to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the SMSTA bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the SMAL to indicate that the attempt to engage the bus is failed. Consideration of these cases, the slave service routine should test the SMAL first, software should clear the SMAL bit if it is set. 12.7 OPERATION DURING WAIT MODE During WAIT mode the SM-Bus block is idle. If in slave mode it will wake up on receiving a valid start condition. If the interrupt is enabled the CPU will come out of WAIT mode after the end of a byte transmission. 12.8 OPERATION DURING STOP MODE In Stop Mode the SM-Bus is disabled. MOTOROLA 12-14 SM-BUS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 13 CURRENT SENSE AMPLIFIER The Current Sense Amplifier module, used in conjunction with the Analog Subsystem, is designed to monitor charge and discharge currents in smart battery applications. 13.1 CURRENT SENSE AMPLIFIER APPLICATION A typical connection for the Current Sense Amplifier (CSA) block is illustrated in Figure 13-1. With a sense resistor, RSENSE of 0.01 Ω, the voltage setup across the node CSA and VSS (ground) will vary to the current (in either charging or discharging mode) as shown in Table 13-1. Table 13-1. Voltage Across the Sense Resistor against Current Current flowing 10mA 1A 5A RSENSE =0.01Ω Voltage across the Sense Resistor, RSENSE 0.1mV 10mV 50mV In this case, the CSA is required to measure a current from 10mA to 5A over the operating temperature from 0°C to 70°C. With the A/D in the Analog Subsystem set up for 12-bit resolution, the step size is approximately 1.22mV (VDD =5V). To measure the 0.1mV for the 10mA current flow, a gain of greater than 10 is required. The CSA module is designed with two gain settings, 10 and 30. With a 10-bit A/D, and a gain of 30, the CSA can measure current with a typical resolution of 17mA steps. After amplification, the resultant signal is fed to channel 6 (MUX6) of the analog subsystem for A/D conversion. MC68HC05SB7 REV 2.1 CURRENT SENSE AMPLIFIER MOTOROLA 13-1 GENERAL RELEASE SPECIFICATION August 27, 1998 Batt+ CSCAL (bit 4 of $0A) CSEN (bit 7 of $0A) CSA + x30 (bit 6 of $0A) x10 (bit 5 of $0A) Gain Adjustment VMID (For internal test) To analog MUX 6 input 0.01Ω RSENSE Batt– VSS VDD D VDET Typically –15mV Q CDEN (bit 3 of $0A) CDET Interrupt + – R CDIFR (bit 1 of $0A) CDIE (bit 2 of $0A) Port B I/O Logic PB2/ CS0 PB3/ CS1 CS0 and CS1 pins are not available for CSA functions when OSC1 and OSC2 are used; i.e. external crystal osc. option is used. Logic CDEN (bit 3 of $0A) CSSEL (bit 3 of $0B) Figure 13-1. Current Sense Amplifier Block 13.2 CURRENT SENSE INTERRUPT The CSA can generate an interrupt once it detects a (discharge) current passes through the current sensing resistor, RSENSE. The trip current depends on the value of the sense resistor; it is voltage developed across RSENSE, VDET that trips the interrupt. VDET is set typically at –15mV, with –10mV being the minimum. 13.3 CSA STATUS AND CONTROL REGISTER (CSSCR) The CSA status and control register is shown in Figure 13-2. MOTOROLA 13-2 CURRENT SENSE AMPLIFIER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION BIT 7 CSSCR $000A reset: R W CSEN 0 BIT 6 X30 0 BIT 5 X10 0 BIT 4 CSCAL 0 BIT 3 CDEN 0 BIT 2 CDIE 0 BIT 1 0 CDIFR 0 BIT 0 CDIF 0 Figure 13-2. CSA Status and Control Register (CSSCR) CSEN — Current Sense Amplifier Enable This read/write bit enables the CSA module. Reset clears the CSEN bit. 1 = CSA block enabled. 0 = CSA block disabled. X30, X10 — Current Sense Amplifier Gain Select These read/write bits enable the respective gain to be selected. See Table 13-2. Reset clears the X30 and X10 bits. Table 13-2. Current Sense Amplifier Gain Select X30 0 1 1 X10 Don’t care 0 1 GAIN SELECTED X10 X30 Undetermined CSCAL — Current Sense Amplifier Calibration Enable This read/write bit enables the CSA calibration. Reset clears the CSCAL bit. 1 = CSA calibration enabled; current amplifier input connected to ground (VSS). 0 = CSA calibration disabled; current amplifier input from CSA pin. CDEN — Current Detect Enable This read/write bit enables the current detect comparator and current detect output pin (CS0 or CS1) logic. Reset clears the CDEN bit. 1 = Current detect comparator enabled. 0 = Current detect comparator disabled. CDIE — Current Detect Interrupt Enable This read/write bit enables interrupts caused by detecting the current passing through the sensing resistor, RSENSE. Reset clears the CDIE bit. 1 = Current detect interrupt enabled. 0 = Current detect interrupt disabled. CDIFR — Current Detect Interrupt Flag Reset Writing a logic “1” to this write-only bit clears the CDIF bit. CDIFR always reads as a logic zero. Reset does not affect CDIFR. 1 = Clear CDIF bit. 0 = No affect on CDIF bit. MC68HC05SB7 REV 2.1 CURRENT SENSE AMPLIFIER MOTOROLA 13-3 GENERAL RELEASE SPECIFICATION August 27, 1998 CDIF — Current Detect Interrupt Flag This read-only bit is set when the voltage developed across the sense resistor, RSENSE is equal to or greater than VDET (the CSA comparator trip voltage, typically –15mV) CDIF generates an interrupt request to the CPU if CDIE is also set. The CDIF bit is cleared by writing a logic “1” to the CDIFR bit. Writing to CDIF has no effect. Reset clears CDIF. 1 = Current detect interrupt has occurred. 0 = No current detect interrupt since CDIF last cleared. If the OSC1 and OSC2 pins are not enabled (by mask option). The current detect interrupt from CDIF bit can be reflected to one of two output port pins, PB2/CS0 and PB3/CS1. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 U = UNAFFECTED BY RESET Figure 13-3. Miscellaneous Control Register (MCR) CSSEL — Current Sense detect output Select This read/write bit selects either CS0 pin or CS1 pin is used to reflect the current detect interrupt. Reset clears the CSSEL bit. 1 = CS1 enabled, CS0 disabled. 0 = CS0 enabled, CS1 disabled. Table 13-3. Current Detect Output Select CDEN 0 0 1 1 CSSEL 0 1 0 1 PB2/CS0 PB2 PB2 CS0 PB2 PB3/CS1 PB3 PB3 PB3 CS1 CS0 and CS1 are not available when OSC1 and OSC2 are used for external oscillator option. 13.4 CSA OPERATION DURING WAIT MODE In WAIT mode the CSA module continues to operate and may generate an interrupt to trigger the MCU out of WAIT mode. 13.5 CSA OPERATION DURING STOP MODE In STOP mode the CSA module is disabled; but a CSA interrupt (by CDIF) can wake-up the MCU from the STOP mode. MOTOROLA 13-4 CURRENT SENSE AMPLIFIER MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 14 TEMPERATURE SENSOR The MC68HC05SB7 MCU can measure temperature in two ways: by using the internal temperature sensor, or by using an external thermistor. 14.1 INTERNAL TEMPERATURE SENSOR The internal temperature sensor is designed to measure temperature over the 0 °C to 70 °C range; with its voltage output connected to channel 5 of the Analog Subsystem (AN5, see Analog Subsystem section). The temperature sensor is disabled/enabled by the TSEN bit in the Miscellaneous Control Register at $0B. The TSEN bit also disables/enables the BandGap reference voltage. BIT 7 MCR $000B reset: R W TSEN 0 BIT 6 LVRON 1 BIT 5 0 COPON 0 BIT 4 SCLK 0 BIT 3 CSSEL 0 BIT 2 TCSEL 0 BIT 1 ESVEN 0 BIT 0 SMINLEV 0 Figure 14-1. Miscellaneous Control Register (MCR) TSEN — Internal Temperature Sensor and BandGap Reference Enable This read/write bit enables the internal temperature sensor and BandGap reference. Reset clears TSEN. 1 = Temperature sensor and bandgap reference enabled. 0 = Temperature sensor and bandgap reference disabled. NOTE The temperature gradient is typically 2.2mV/°C ±10%. The internal temperature sensor is a semiconductor type sensor. Due to process variations, the absolute output voltage at a given temperature will vary from one device to another. It is the user’s responsibility to measure and calibrate the temperature sensor output voltage when the MCU is in the target system. As an option, the temperature sensor voltage at 80°C is available preprogrammed into the PEPROM. See PEPROM section. MC68HC05SB7 REV 2.1 TEMPERATURE SENSOR MOTOROLA 14-1 GENERAL RELEASE SPECIFICATION August 27, 1998 14.2 EXTERNAL TEMPERATURE SENSOR In fast charge control applications, where close monitoring of the charging process is required (especially temperature), an external temperature sensor (thermistor) is recommended. This external thermistor connects to the TM pin (see Figure 14-2), and its voltage measured via channel 4 (AN4, see Analog Subsystem section) of the Analog Subsystem. For faster temperature response time and more accurate measurement (required for fast charge control), the thermistor should be mounted directly to the battery pack. Batt+ MC68HC05SB7 VM VDD TM Batt– Thermistor Figure 14-2. External Temperature Sensor Connection 14.3 TEMPERATURE SENSOR OPERATION DURING WAIT MODE During WAIT mode the temperature sensor continues to operate normally. 14.4 TEMPERATURE SENSOR OPERATION DURING STOP MODE In STOP mode the temperature sensor is disabled. MOTOROLA 14-2 TEMPERATURE SENSOR MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 15 ANALOG SUBSYSTEM The analog subsystem of the MC68HC05SB7 is based on an on-chip voltage comparator as shown in Figure 15-1. This configuration provides following features: • • The voltage comparator with external access to both inverting and noninverting inputs The voltage comparator can be connected as a single-slope A/D. The possible single-slope A/D connection provides the following features: – A/D conversions can use VDD or an external voltage as a reference with software used to calculate ratiometric or absolute results – Channel access to up to eight inputs via multiplexer control with independent multiplexer control allowing multiple input connections – Access to VDD and VSS for calibration – Divide by 2 to extend input voltage range – The comparator can be inverted to calculate input offsets – Internal sample and hold capacitor Voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the unknown input voltage that is being measured. The beginning of the A/D conversion time can be started by several means: • • • • • • Output compare from the 16-bit programmable Timer Timer overflow from the 16-bit programmable Timer Direct software control via a register bit Input capture in the 16-bit programmable Timer Interrupt generated by the comparator output Software polling of the comparator output using software loop time The end of the A/D conversion time can be captured by several means: MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-1 GENERAL RELEASE SPECIFICATION August 27, 1998 OCF TOF PB1 TCAP VDD ICHG CAP IDISCHG ICF 2 TO 1 MUX SCL 2 TO 1 MUX TCAP TCSEL CPIE VDD + COMP – INV 100K CPF ANALOG STATUS REGISTER (ASR) PORTB LOGIC PB7 AN0 PORTB LOGIC PB6 AN1 PORTB LOGIC PB5 AN2 PORTB LOGIC PB4 AN3 MUX0 100K SAMPLE CAP CMP MUX1 ANALOG CONTROL REGISTER (ACR) CHARGE CURRENT CONTROL LOGIC BIT 2 OF MCR ($0B) CHG ATD1 ATD2 ISEN CPEN ICEN 16-BIT PROG. TIMER MUX2 ANALOG INTERRUPT CHANNEL SELECT BUS HOLD DHOLD INV VREF VREF MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 IBREF MUX3 MUX2 MUX1 MUX0 ANALOG MUX REGISTER 1 (AMUX1) MUX3 MUX4 TM AN4 (see Figure 13-1) CSA CURRENT SENSE AN6 AMPLIFIER CIRCUIT MUX7 AN7 MUX6 VAOFF VSS MUX5 AN5 IBREF INTERNAL TEMPERATURE SENSOR INTERNAL BANDGAP REFERENCE TSEN BIT 7 OF MCR ($0B) IBREF MUX7 MUX6 MUX5 MUX4 –+ DENOTES INTERNAL CHIP AVSS VIB Figure 15-1. Analog Subsystem Block Diagram MOTOROLA 15-2 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 ANALOG MUX REGISTER 2 (AMUX2) VM INTERNAL HC05 BUS August 27, 1998 GENERAL RELEASE SPECIFICATION 15.1 ANALOG MULTIPLEX REGISTERS The Analog Multiplex Registers (AMUX1 and AMUX2) control the general interconnection and operation. The control bits in AMUX1 and AMUX2 are shown in Figure 15-2 and Figure 15-2 respectively. BIT 7 AMUX1 $0003 reset: R W HOLD 1 BIT 6 DHOLD 0 BIT 5 INV 0 BIT 4 VREF 0 BIT 3 MUX3 0 BIT 2 MUX2 0 BIT 1 MUX1 0 BIT 0 MUX0 0 Figure 15-2. Analog Multiplex Register 1 (AMUX1) BIT 7 AMUX2 $0007 reset: R W 0 0 0 0 BIT 6 BIT 5 0 BIT 4 IBREF 0 BIT 3 MUX7 0 BIT 2 MUX6 0 BIT 1 MUX5 0 BIT 0 MUX4 0 Figure 15-3. Analog Multiplex Register 2 (AMUX2) HOLD, DHOLD These read/write bits control the source connection to the input to the negative input of voltage comparator shown in Figure 15-1. This allows the channel selection bus or the 1:2 divided channel selection bus to charge the internal sample capacitor and to also be presented to comparator. The decoding of these sources is given in Table 15-1. During a reset the HOLD bit is set and the DHOLD bit is cleared, which connects the internal sample capacitor to the channel selection bus. And since a reset also clears the MUX0:7 bits then the channel selection bus will be connected to VSS and the internal sample capacitor will be discharged to VSS following the reset. Table 15-1. Comparator Input Sources HOLD 0 DHOLD 0 Case Sample Hold Source To Negative Input of Comparator Internal sample capacitor connected to only the negative input of comparator; and subjected to a very low leakage current. Signal to channel selection bus is divided by 2 and connected to both the internal sample capacitor and negative input of comparator. Signal to channel selection bus is connected directly to both the internal sample capacitor and negative input of comparator. — 0 1 Divided Input 1 1 0 1 Direct Input Not allowed MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-3 GENERAL RELEASE SPECIFICATION August 27, 1998 NOTE When sampling a voltage for later conversion the HOLD and DHOLD bit should be cleared before making any changes in the MUX channel selection. If the MUX channel and the HOLD/DHOLD are changed on the same write cycle to the AMUX1 register, the sampled voltage may be altered during the channel switching. INV This is a read/write bit that controls the phase of the voltage comparator. This bit allows voltage comparisons with either input node of the voltage comparator to be presented to the rest of the circuit as the “positive” or “negative” input. The voltage comparator is defined as non-inverted when the internal positive node is connected to the external positive input and the output is not inverted. In this case the output will go to a logical one when the voltage on the positive input is higher than the voltage on the negative input. Any input offset voltage in the voltage comparator will be with respect to the negative input. The voltage comparator is defined as inverted when the internal negative node is connected to the external positive input and the output is inverted. In this case the output will still go to a logical one when the voltage on the positive input is higher than the voltage on the negative input. In the inverted case any input offset voltage in the voltage comparator will be with respect to the positive input. This bit is cleared by a reset of the device. 1 = The voltage comparator is internally inverted. 0 = The voltage comparator is not internally inverted. V+ VIO RISE WHEN V+ > V– V– + COMP – INV=0 V+ VIO RISE WHEN V+ > V– V– + COMP – INV=1 Figure 15-4. INV Bit Action NOTE The effect of changing the state of the INV bit is to only change the polarity of the input offset voltage. It does not change the output phase of the CPF flag with respect to the external port pins. The comparator may generate an output flag when the inputs are exchanged due to a change in the state of the INV bit. It is therefore recommended that the INV bit MOTOROLA 15-4 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION not be changed while waiting for a comparator flag. Further, any changes to the state of the INV bit should be followed by writing a logical one to CPFR bit to clear an extraneous CPF flag that may have occurred. VREF This is a read/write bit that connects the channel select bus to VDD for purposes of making a reference voltage measurement. It cannot be selected if any of the other input sources to the channel select bus are selected as shown in Table 15-2. This bit is cleared by a reset of the device. 1 = Channel select bus connected to VDD if MUX7:0 and IBREF are cleared. 0 = Channel select bus cannot be connected to VDD. IBREF This is a read/write bit that connects the channel select bus to VIB for purposes of making a reference voltage measurement. It cannot be selected if any of the other input sources to the channel select bus are selected as shown in Table 15-2. This bit is cleared by a reset of the device. 1 = Channel select bus connected to VIB if MUX7:0 and VREF are cleared. 0 = Channel select bus cannot be connected to VIB. MUX7:0 These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage comparator for purposes of making a voltage measurement. They can be selected individually or combined with any of the other input sources to the channel select bus as shown in Table 15-2. NOTE The VAOFF voltage source shown in Figure 15-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single VSS pin. The offset raises the internal VSS reference (AVSS) in the analog subsystem with respect to the external VSS pin. Turning on the VSS MUX to the channel select bus connects it to this internal AVSS reference line. When making A/D conversions this AVSS offset gets placed on the external ramping capacitor since the discharge device on the CAP pin discharges the external capacitor to the internal AVSS line. Under these circumstances the positive input (+) to the comparator will always be higher than the negative input (– ) until the negative input reaches the AVSS offset voltage plus any offset in the comparator. Therefore, input voltages cannot be resolved if they are less than the sum of the AVSS offset and the comparator offset, because they will always yield a low output from the comparator MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-5 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel Select Bus Connected to: M U X 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M U X 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 M U X 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 M U X 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 M U VDD X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 MOTOROLA 15-6 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Channel Select Bus Connected to: M U X 4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 M U X 3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 M U X 2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 M U X 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 M U VDD X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-7 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 0 0 0 ! 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel Select Bus Connected to: M U X 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M U X 3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 M U X 2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 M U X 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M U VDD X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MOTOROLA 15-8 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 XX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Channel Select Bus Connected to: M U X 4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 M U X 3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 M U X 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 M U X 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 M U VDD X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-9 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX0 XX0 XX0 XX0 XX0 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel Select Bus Connected to: M U X 4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 M U X 3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 M U X 2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 M U X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 M U VDD X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MOTOROLA 15-10 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Channel Select Bus Connected to: M U X 4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 M U X 3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 M U X 2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 M U X 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 M U VDD X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-11 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 0 0 0 0 0 0 0 ! 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel Select Bus Connected to: M U X 4 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 M U X 3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 M U X 2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M U X 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M U VDD X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MOTOROLA 15-12 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Channel Select Bus Connected to: M U X 4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 M U X 3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 M U X 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 M U X 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 M U VDD X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z ON ON ON ON ON ON ON ON Z Z Z Z Z Z Z Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON ON Z Z Z Z ON ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON ON Z Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-13 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-2. Channel Select Bus Combinations Analog Multiplex Registers (AMUX1 and AMUX2) I V MMM B R UUU R E XXX E F 765 F XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 XX1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 Channel Select Bus Connected to: M U X 4 1 1 1 1 1 1 1 1 1 0 0 M U X 3 0 1 1 1 1 1 1 1 1 0 0 M U X 2 1 0 0 0 0 1 1 1 1 0 0 M U X 1 1 0 0 1 1 0 0 1 1 0 0 M U VDD X 0 1 0 1 0 1 0 1 0 1 0 0 Z Z Z Z Z Z Z Z Z Z ON VIB AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Z Z Z Z Z Z Z Z Z ON Z ON ON ON ON ON ON ON ON ON Z Z ON ON ON ON ON ON ON ON ON Z Z ON ON ON ON ON ON ON ON ON Z Z ON ON ON ON ON ON ON ON ON Z Z Z ON ON ON ON ON ON ON ON Z Z ON Z Z Z Z ON ON ON ON Z Z ON Z Z ON ON Z Z ON ON Z Z ON Z ON Z ON Z ON Z ON Z Z Z Z Z Z Z Z Z Z Z Z Z X = Don’t Care Z = High Impedance 15.2 ANALOG CONTROL REGISTER The Analog Control Register (ACR) controls the power up, interrupt and flag operation. The analog subsystem draws about 470 µA of current while it is operating. The resulting power consumption can be reduced by powering down the analog subsystem when not in use. This can be done by clearing two enable bits (ISEN and CPEN) in the ACR at $001D. Since these bits are cleared following a reset, the voltage comparator and the charge current source will be powered down following a reset of the device. The control bits in the ACR are shown in Figure 15-2. All the bits in this register are cleared by a reset of the device. BIT 7 ACR $001D reset: R W CHG 0 BIT 6 ATD2 0 BIT 5 ATD1 0 BIT 4 ICEN 0 BIT 3 CPIE 0 BIT 2 CPEN 0 0 BIT 1 BIT 0 ISEN 0 Figure 15-5. Analog Control Register (ACR) MOTOROLA 15-14 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION CHG The CHG enable bit allows direct control of the charge current source and the discharge device; and also reflects the state of the discharge device. This bit is cleared if the ISEN enable bit is also cleared. This bit is cleared by a reset of the device. 1 = The charge current source is sourcing current out of the CAP pin. Writing a logical one enables the charging current out of the CAP pin, if the ISEN bit is also set. 0 = The discharge device is sinking current into the CAP pin. Writing a logical zero disables the charging current and enables the discharging current into the CAP pin. ATD1:2 The ATD1:2 enable bits select one of the four operating modes used for making A/D conversions via the single-slope method.These four modes are given in Table 15-3. These bits have no effect if the ISEN enable bit is cleared. These bits are cleared by a reset of the device; and thereby returning the analog subsystem to the manual A/D conversion method. Table 15-3. A/D Conversion Options A/D Option Mode Charge Control Current Source and Discharge Disabled A/D Options ISEN ATD2 ATD1 CHG Current Flow To/From CAP Disabled 0 X X X Current control disabled, no source or sink current. Begin sinking current when the CHG bit is cleared; and continue to sink current until the CHG bit is set. Begin sourcing current when the CHG bit is set; and continue to source current until the CHG bit is cleared. Begin sinking current when the CHG bit is cleared; and continue to sink current until the CHG bit is set. (The CHG bit is cleared by writing a logical zero to it; or when the CPF flag bit is set.) Begin sourcing current when the CHG bit is set; and continue to source current until the CHG bit is cleared. (The CHG bit is cleared by writing a logical zero to it; or when the CPF flag bit is set.) The CHG bit remains cleared as long as current is being sunk. Begin sourcing current when the next Timer TOF occurs. The CHG bit remains set as long as current is being sourced. Begin sinking current when the next Timer ICF occurs. 1 0 Manual Charge and Discharge 1 0 0 0 0 0 1 1 1 Manual Charge and Automatic Discharge 1 0 1 0 0 1 1 2 Automatic Charge and Discharge (TOF-ICF) Synchronized to Timer 1 1 0 0 1 1 0 1 MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-15 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-3. A/D Conversion Options A/D Option Mode Charge Control Automatic Charge and Discharge (OCF-ICF) Synchronized to Timer A/D Options ISEN 1 ATD2 ATD1 1 1 CHG 0 Current Flow To/From CAP The CHG bit remains cleared as long as current is being sunk. Begin sourcing current when the next Timer OCF occurs. The CHG bit remains set as long as current is being sourced. Begin sinking current when the next Timer ICF occurs. 3 1 1 1 1 ICEN This is a read/write bit that enables a voltage comparison to trigger the input capture register of the programmable Timer when the CPF flag bit is set. Therefore an A/D conversion could be started by receiving an OCF or TOF from the programmable Timer; and then terminated when the voltage on the external ramping capacitor reaches the level of the unknown voltage. The time of termination will be stored in the 16-bit buffer located at $0014 and $0015. This bit is automatically set whenever Mode 2 or 3 is selected by setting the ATD2 control bit. This bit is cleared by a reset of the device. 1 = Connects the CPF flag bit to the Timer input capture register. 0 = Connects the PB1/TCAP pin to the Timer input capture register. NOTE When the ICEN bit is set the input capture function of the programmable Timer is not connected to the PB1/TCAP pin but is driven by the CPF output flag from the comparator. To return to capturing times from external events, the ICEN bit must first be cleared before the timed event occurs. NOTE The TCSEL bit in the Miscellaneous Control Register (bit 2 in $0B) must be cleared for ICEN control. TCSEL=1 will select the SCL signal from the SMBus as 16-bit Timer Input Capture source, irrespective of ICEN setting. CPIE This is a read/write bit that enables an analog interrupt when the CPF flag bits is set to a logical one. This bit is cleared by a reset of the device. 1 = Enables analog interrupt when comparator flag bit is set. 0 = Disables analog interrupt when comparator flag bit is set. MOTOROLA 15-16 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION CPEN The CPEN enable bit will power down voltage comparator in the analog subsystem. Powering down a comparator will drop the supply current by about 100 µA. This bit is cleared by a reset of the device. 1 = Writing a logical one powers up voltage comparator. 0 = Writing a logical zero powers down voltage comparator NOTE The voltage comparator powers up slower than digital logic; and its output may go through indeterminate states which might set the CPF flag. It is therefore recommended to power up the charge current source first (ISEN); then to power up the comparator, and finally clear the bit by writing a logic one to the CPFR bit in the ACR. ISEN The ISEN enable bit will power down the charge current source and disable the discharge device in the analog subsystem. Powering down the current source will drop the supply current by about 200 µA. This bit is cleared by a reset of the device. 1 = Writing a logical one powers up the ramping current source and enables the discharge device on the CAP pin. 0 = Writing a logical zero powers down the ramping current source and disables the discharge device on the CAP pin. NOTE The analog subsystem has support circuitry which draws about 70 µA of current. This current will be powered down if the comparator and the charge current source are powered down (ISEN and CPEN all cleared). Powering up the comparator or the charge current source will activate the support circuitry. 15.3 ANALOG STATUS REGISTER The Analog Status Register (ASR) controls the interrupt and flag operation. The control bits in the ASR are shown in Figure 15-2. All the bits in this register are cleared by a reset of the device. BIT 7 ASR $001E reset: R W 0 0 CPF BIT 6 BIT 5 0 CPFR 0 0 0 0 0 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 Figure 15-6. Analog Status Register MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-17 GENERAL RELEASE SPECIFICATION August 27, 1998 CPF This read-only flag bit is set when the voltage on the positive input of comparator rises above the voltage on its negative input. This bit is reset by writing a logical one to the CPFR reset bit in the ASR. This bit is cleared by a reset of the device. 1 = The voltage on positive input of comparator was above the voltage on its negative input since CPF had been cleared. 0 = The voltage on positive input of comparator has not been above the voltage on its negative input since CPF had been cleared. CPFR Writing a logical one to this write-only flag clears the CPF flag in the ASR. Writing a logical zero to this bit has no effect. Reading the CPFR bit will return a logical zero. By default this bit looks cleared following a reset of the device. 1 = Clears the CPF flag bit. 0 = No effect. NOTE The CPFR bit should be written with a logical one following a power up of the comparator. This will clear out any latched CPF flag bit which might have been set during the slower power up sequence of the analog circuitry. If both inputs to the comparator are above the maximum common-mode input voltage (VDD –1.5V) the output of the comparator is indeterminate and may set the comparator flag. Applying a reset to the device may only temporarily clear this flag as long as both inputs of a comparator remain above the maximum commonmode input voltages. MOTOROLA 15-18 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 15.4 A/D CONVERSION METHODS The control bits in the ACR provide various options to charge or discharge current through the CAP pin in order to perform single-slope A/D conversions using an external capacitor from the CAP pin to VSS as shown in Figure 15-7. The various A/D conversion triggering options are given in Table 15-3. VDD – 1.5 VDC Charge Time = C x VX I VOLTAGE ON CAPACITOR CONNECTED TO (+) INPUT CHARGE TIME TO MATCH UNKNOWN MAXIMUM CHARGE TIME TO VDD – 1.5 VDC UNKNOWN VOLTAGE ON (–) INPUT DISCHARGE TIME TO RESET CAPACITOR +5V VDD TM Using VDD as Voltage Reference PB7/AN0 UNKNOWN SIGNALS PB6/AN1 PB5/AN2 PB4/AN3 RAMP CAP CAP VSS MC68HC05SB7 +5V VDD TM Using an External Voltage Reference UNKNOWN SIGNALS REFERENCE VOLTAGE RAMP CAP PB7/AN0 PB6/AN1 PB5/AN2 PB4/AN3 CAP VSS MC68HC05SB7 Figure 15-7. Single-Slope A/D Conversion Method The top three bits of the ACR control the charging and discharging current into or out of the CAP pin. These three bits will have no affect on the CAP pin if the ISEN enable bit is cleared. Any clearing of the ISEN bit will immediately disable both the MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-19 GENERAL RELEASE SPECIFICATION August 27, 1998 charge current source and the discharge device. Since all these bits and the ISEN bit are cleared when the device is reset, the MC68HC05SB7 starts with the charge and discharge function disabled. The length of time required to reach the maximum voltage to be measured will determine the resolution of the reading. The time to ramp the external capacitor voltage to match the maximum voltage is dependent on: • • • • • Desired resolution. Clock rate for timing function. Any prescaling of the clock to the timing function. Charging current to external capacitor. Value of the external capacitor. C × V MAX t CHG = ---------------------I CHG Each parameter can also be expressed by the following equations: P×N t CHG = ------------f OSC I CHG × P × N V MAX = ----------------------------C × f OSC V MAX × C × f OSC N = -------------------------------------I CHG × P I CHG × N × P C = ----------------------------V MAX × f OSC where the signal names and parameters used are given in Table 15-4. NOTE Noise on the system ground or the external ramping capacitor can cause the comparator to trip prematurely. Therefore in any given application it is best to use the fastest possible ramp rate (shortest possible time). The values of each parameter are related by the general equation: NOTE The value of any capacitor connected directly to the CAP pin should be limited to less than 2µF. Larger capacitances will create signal noise. MOTOROLA 15-20 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION NOTE Sufficient time should be allowed to discharge the external capacitor or subsequent charge times will be shortened with resultant errors in timing conversion. NOTE If the unknown voltage applied to the comparator is greater than its commonmode range (VDD –1.5 volts) the external capacitor will try to charge to the same level. This will cause both comparator inputs to be above the common-mode range and the output will be indeterminate. All A/D conversion software methods should have a maximum time check to determine if this case is occurring. Table 15-4. A/D Conversion Signals and Definitions Name ICHG IDIS VCAP VX VMAX tCHG tDIS C N P fOSC Function Charging current on external ramping capacitor Discharge current on external ramping capacitor Voltage on external ramping capacitor Voltage of unknown on (–) input of voltage comparator Maximum voltage on external ramping capacitor TIme to charge external capacitor Time to discharge external capacitor Capacitance of external ramping capacitor Number of counts for ICHG to charge C to VX Prescaler into timing function Clock source frequency (excluding any prescaling) Conditions ICHG = 80 - 120 µA IDIS > 1 mA VSS < VCAP < (VDD – 1.5) VSS < VX < (VDD –1.5) VMAX = VDD – 1.0 ∆t from VSS to VX ∆t from VMAX to VSS 0.001 to 1.000 µF 0 to 65536 fOSC ÷ loop time for software timing fOSC ÷ 8 for Core Timer fOSC ÷ 8 for Programmable TImer 0 to 4.2 MHz Table 15-5 gives examples of voltage ranges, resolution, ramp times and capacitor sizes for various conversion methods. MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-21 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-5. Sample Conversion Timing Bits 8 Counts 256 VMAX (VDC) 3.5 A/D Method Software Loop (10 cycles) Mode 0 (manual) Clock Source Ext Pin Oscillator VCO fOSC (MHz) 2.0 0.5 1.0 tCHG (µs) 2560 4096 2048 1024 512 16384 8192 4096 2048 65536 32768 16384 8192 C (µF) 0.073 0.117 0.059 0.029 0.015 0.468 0.234 0.117 0.059 1.872 0.936 0.468 0.234 8 256 3.5 Programmable Timer, Mode 1 (TOF to ICF) Ext Pin Oscillator 2.0 4.0 VCO 10 1024 3.5 Programmable Timer, Mode 1 (TOF to ICF) 0.5 1.0 Ext Pin Oscillator 2.0 4.0 VCO 12 4096 3.5 Programmable Timer, Mode 1 (TOF to ICF) 0.5 1.0 Ext Pin Oscillator 2.0 4.0 The general architecture of the MC68HC05SB7 and mode selection bits in the ACR allow four methods based on simple single-slope A/D conversion. Each of these methods is shown in the following figures: • • • • Manual start and stop (Mode 0) Figure 15-8. Manual start and automatic discharge (Mode 1) Figure 15-9. Automatic start and stop from TOF to ICF (Mode 2) Figure 15-10. Automatic start and stop from OCF to ICF (Mode 3) Figure 15-11. The description of the signals and parameters used in these figures are given in Table 15-4. MOTOROLA 15-22 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG X ICHG CX tMAX tDIS (MIN) VMAX CHG COMP TOF OCF ICF 0 1 2 3 4 5 1 Point 0 1 2 3 4 5 Action Begin initial Discharge and select Mode 0 by clearing the CHG, ATD2 and ATD1 control bits in the ACR. VCAP falls to VSS. Stop Discharge and begin Charge by setting CHG control bit in ACR. VCAP rises to VX and comparator output trips, setting CPF. VCAP Reaches VMAX. Begin next Discharge by clearing the CHG control bit in the ACR. Software/Hardware Action Software write. Wait out minimum tDIS time. Software write. Wait out tCHG time. Wait out tCHG time. Software write. Dependent Variable(s) Software. VMAX, IDIS, CX. Software. VX, ICHG, CX. VMAX, ICHG, CX. Software. Figure 15-8. A/D Conversion - Full Manual Control (Mode 0) MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-23 GENERAL RELEASE SPECIFICATION August 27, 1998 tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG X ICHG CX tDIS (MIN) VMAX CHG COMP TOF OCF ICF 0 1 2 3 1 2 Point 0 1 2 Action Begin initial Discharge and select Mode 1 by clearing CHG and ATD2; and setting ATD1 in the ACR. VCAP falls to VSS. Stop Discharge and begin Charge by setting CHG control bit in ACR. VCAP rises to VX and comparator output trips, setting CPF which clears CHG control bit in the ACR. Software/Hardware Action Software write. Wait out minimum tDIS time. Software write. Wait out tCHG time. CPF clears CHG control bit. Dependent Variable(s) Software. VMAX, IDIS, CX. Software. 3 VX, ICHG, CX. Figure 15-9. A/D Conversion - Manual/Auto Discharge Control (Mode 1) MOTOROLA 15-24 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG X ICHG CX tDIS (MIN) VMAX CHG COMP (TCAP) TOF OCF ICF 0 1 2 3 1 2 Point 0 1 2 Action Begin initial Discharge and select Mode 2 by clearing CHG and ATD1 and setting ATD2 in the ACR. VCAP falls to VSS. Stop Discharge and begin Charge when the next TOF sets the CHG control bit in ACR. VCAP rises to VX and comparator output trips, setting CPF which causes an ICF from the Timer and clears the CHG control bit in ACR. Software/Hardware Action Software write. (ICEN bit also set) Wait out minimum tDIS time. Timer TOF sets the CHG control bit in the ACR. Wait out tCHG time. Timer ICF clears the CHG control bit in the ACR. Dependent Variable(s) Software. VMAX, IDIS, CX. Free-running Timer counter overflow, fOSC, P. 3 VX, ICHG, CX. Figure 15-10. A/D Conversion - TOF/ICF Control (Mode 2) MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-25 GENERAL RELEASE SPECIFICATION August 27, 1998 tDIS tDIS (MIN) VCAP tCHG VX VX = tCHG X ICHG CX tDIS (MIN) VMAX CHG COMP (TCAP) TOF OCF ICF 0 1 2 3 1 3 Point 0 Action Begin initial Discharge and select Mode 3 by clearing CHG and setting ATD2 and ATD1 in the ACR. VCAP falls to VSS. Set Timer output compare registers (OCRU, OCRL) to desired charge start time. Stop Discharge and begin Charge when the next OCF sets the CHG control bit in ACR. VCAP rises to VX and comparator output trips, setting CPF which causes an ICF from the Timer and clears the CHG control bit in ACR. Software/Hardware Action Software write. (ICEN bit also set) Wait out minimum tDIS time. Software write to OCRH, OCRL. Timer OCF sets the CHG control bit in the ACR. Wait out tCHG time. Timer ICF clears the CHG control bit in the ACR. Dependent Variable(s) Software. 1 VMAX, IDIS, CX, Software. 2 Free-running Timer counter overflow, fOSC, P. 3 VX, ICHG, CX. Figure 15-11. A/D Conversion - OCF/ICF Control (Mode 3) MOTOROLA 15-26 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 15.5 VOLTAGE MEASUREMENT METHODS The various methods for obtaining a voltage measurement can use software techniques to express these voltages as absolute or ratiometric readings. NOTE All A/D conversion methods should include a test for a maximum elapsed time in order to detect error cases where the inputs may be outside of the design specification. 15.5.1 Absolute Voltage Readings The absolute value of a voltage measurement can be calculated in software by first taking a reference reading from a fixed source and then comparing subsequent unknown voltages to that reading as a percentage of the reference voltage multiplied times the known reference value. The accuracy of absolute readings will depend on the error sources taken into account using the features of the analog subsystem and appropriate software as described in Table 15-6. As can be seen from this table, most of the errors can be reduced by frequent comparisons to a known voltage, use of the inverted comparator inputs, and averaging of multiple samples. Table 15-6. Absolute Voltage Reading Errors Error Source Change in Reference Voltage Change in Magnitude of Ramp Current Source Non-Linearity of Ramp Current Source vs. Voltage Change in Magnitude of Ramp Capacitor Frequency Shift in Internal Low-Power Oscillator Frequency Shift in External Oscillator Sampling Capacitor Leakage Internal Voltage Divider Ratio Noise internal to MCU Accuracy Improvements Possible In Hardware Provide closer tolerance reference In Software Calibration and storage of reference source over temperature and supply voltage Compare unknown with recent measurement from reference Calibration and storage of voltages at 1/4, 1/2, 3/4 and FS Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference OR avoid use of divided input Average multiple readings on both the reference and the unknown voltage Not adjustable Not adjustable Provide closer tolerance ramp capacitor Use external oscillator with crystal Provide closer tolerance crystal Use faster conversion times Not adjustable Close decoupling at VDD and VSS pins and reduce supply source impedance MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-27 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-6. Absolute Voltage Reading Errors Error Source Accuracy Improvements Possible In Hardware Close decoupling of power supply, low source impedances, good board layout, use of multi-layer board In Software Average multiple readings on both the reference and the unknown voltage Noise external to MCU Internal Absolute Reference If a stable source of VDD is provided, the reference measurement point can be internally selected. In this case the reference reading can be taken by setting the VREF bit and clearing the MUX7:0 bits in the AMUX register. This connects the channel selection bus to the VDD pin. Alternatively, the internal bandgap voltage can be used as the reference measurement point, by setting the IBREF bit in AMUX2 Register and TSEN bit in the Miscellaneous Control Register. External Absolute Reference If a stable external source is provided, the reference measurement point can be any one of the channel selected pins from PB4 through PB7. In this case the reference reading can be taken by setting the MUX bit in the AMUX which connects channel selection bus to the pin connected to the external reference source. 15.5.2 Ratiometric Voltage Readings The ratiometric value of a voltage measurement can be calculated in software by first taking a reference reading from a reference source and then comparing subsequent unknown voltages to that reading as a percentage of the reference value. The accuracy of ratiometric readings will depend on variety of sources, but will generally be better than for absolute readings. Many of these error sources can be taken into account using the features of the analog subsystem and appropriate software as described in Table 15-7. As with absolute measurements most of the errors can be reduced by frequent comparisons to the reference voltage, use of the inverted comparator inputs, and averaging of multiple samples. Internal Ratiometric Reference If readings are to be ratiometric to VDD, the reference measurement point can be internally selected. In this case the reference reading can be taken by setting the VREF bit and clearing the MUX7:0 bits in the AMUX register which connects the channel selection bus to the VDD pin. Alternatively, the internal bandgap voltage can be used as the reference measurement point, by setting the IBREF bit in AMUX2 Register and TSEN bit in the Miscellaneous Control Register. MOTOROLA 15-28 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION External Ratiometric Reference If readings are to be ratiometric to some external source, the reference measurement point can be connected to any one of the channel selected pins from PB4 through PB7. In this case the reference reading can be taken by setting the MUX bit in the AMUX which connects channel selection bus to the pin connected to the external reference source. Table 15-7. Ratiometric Voltage Reading Errors Error Source Change in Reference Voltage Change in Magnitude of Ramp Current Source Non-Linearity of Ramp Current Source vs. Voltage Change in Magnitude of Ramp Capacitor Frequency Shift in Internal Low-Power Oscillator Frequency Shift in External Oscillator Sampling Capacitor Leakage Internal Voltage Divider Ratio Noise internal to MCU Accuracy Improvements Possible In Hardware Not required for ratiometric Not required for ratiometric Not adjustable Not required for ratiometric Not required for ratiometric Not required for ratiometric Use faster conversion times Not required for ratiometric Close decoupling at VDD and VSS pins and reduce supply source impedance Close decoupling of power supply, low source impedances, good board layout, use of multi-layer board In Software Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Calibration and storage of voltages at 1/4, 1/2, 3/4 and FS Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Compare unknown with recent measurement from reference Average multiple readings on both the reference and the unknown voltage Average multiple readings on both the reference and the unknown voltage Noise external to MCU 15.6 VOLTAGE COMPARATOR FEATURES The internal comparator can also be used as simple voltage comparator. Voltage Comparator Voltage comparator can be used as a simple comparator if its charge current source and discharge device are disabled by clearing the ISEN bit in the ACR. If ISEN bit is set the internal ramp discharge device connected to CAP may become active and try to pulldown any voltage source that may be connected to that pin. Also, since voltage comparator is always connected to two of the Port B I/O pins, these pins should be configured as inputs and have their software programmable pulldowns disabled. The required setup to use voltage comparator as a simple comparator are shown in Table 15-8. MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-29 GENERAL RELEASE SPECIFICATION August 27, 1998 Table 15-8. Voltage Comparator Setup Conditions Current Source Enable ISEN = 0 Discharge Device Disable ISEN = 0 Port B Pin as Inputs DDRB4 = 0 DDRB5 = 0 Prog. Timer Input Capture Source ICEN = 0 15.7 CURRENT SOURCE FEATURES The internal current source connected to the CAP pin supplies about 100 µA of current when the ramp discharge device is disabled and the current source is active. Therefore this current source can be used in an application if the ISEN enable bit is set to power up the current source is enabled by setting the A/D conversion method to manual Mode 0 (ATD1 and ATD2 cleared) and the charge current enabled (CHG set). 15.8 SAMPLE AND HOLD When using the internal sample capacitor to capture a voltage for later conversion, the HOLD and DHOLD bit must be cleared first before changing any channel selection. If both the HOLD (or DHOLD) bit and the channel selection are changed on the same write cycle, the sample may be corrupted during the switching transitions. NOTE The sample capacitor can be affected by excessive noise created with respect to the device’s VSS pin such that it may appear to leak down or charge up depending on the voltage level stored on the sample capacitor. It is recommended to avoid switching large currents through the port pins while a voltage is to remain stored on the same capacitor. The additional option of adding an offset voltage to the bottom of the sample capacitor allows unknown voltages near VSS to be sampled and then shifted up past the comparator offset and the device offset caused by a single VSS return pin. The offset also provides a means to measure the internal VSS level regardless of the comparator offset in order to determine NOFF as described in Section 15.5. 15.9 PORT B INTERACTION WITH ANALOG INPUTS The analog subsystem is connected directly to the Port B I/O pins without any intervening gates. It is therefore possible to measure the voltages on Port B pins set as inputs; or to have the analog voltage measurements corrupted by Port B pins set as outputs. MOTOROLA 15-30 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 15.9.1 Port B Pins As Inputs All the Port B pins will power up as inputs or return to inputs following a reset of the device since the bits in the Port B Data Direction register will be reset. If any Port B pins are to be used for analog voltage measurements they should be left as inputs. In this case, not only can the voltage on the pin be measured, but the “logic” state of the Port B pins to be read from location $0002. 15.10 NOISE SENSITIVITY In addition to the normal effects of electrical noise on the analog input signal there can also be other noise related effects caused by the digital-to-analog interface. Since there is only one VSS return for both the digital and the analog subsystems on the device, currents in the digital section may affect the analog ground reference within the device. This can add voltage offsets to measured inputs or cause channel-to-channel crosstalk. In order to reduce the impact of these effects, there should be no switching of heavy I/O currents to or from the device while there is a critical analog conversion or voltage comparison in process. Limiting switched I/O currents to 2 to 4 mA during these times is recommended. A noise reduction benefit can be gained with 0.1µF bypass capacitors from each analog input (PB7:4) to the VSS pin. Also, try to keep all the digital power supply or load currents from passing through any conductors which are the return paths for an analog signal. MC68HC05SB7 REV 2.1 ANALOG SUBSYSTEM MOTOROLA 15-31 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 15-32 ANALOG SUBSYSTEM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 16 PERSONALITY EPROM This section describes how to program the 64-bit personality EPROM (PEPROM). Figure 16-1 shows the structure of the bit programmable PEPROM subsystem. INTERNAL DATA BUS PEPROM STATUS/CONTROL REGISTER PEPGM PEPRZF 0 0 0 0 PEDATA 0 RESET SINGLE SENSE AMPLIFIER IRQ/VPP ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 COL 0 COL 1 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 VPP SWITCH 8-TO-1 COLUMN DECODER AND MULTIPLEXER 8-TO-1 ROW DECODER AND MULTIPLEXER VPP SWITCH PEB5 PEB4 PEB3 PEB2 PEB1 PEB0 ROW ZERO DECODER 0 0 PEPROM SELECT REGISTER INTERNAL DATA BUS RESET Figure 16-1. Personality EPROM MC68HC05SB7 REV 2.1 PERSONALITY EPROM MOTOROLA 16-1 GENERAL RELEASE SPECIFICATION August 27, 1998 16.1 PEPROM REGISTERS Two I/O registers control programming and reading of the PEPROM: • • The PEPROM bit select register (PEBSR). The PEPROM status and control register (PESCR). 16.1.1 PEPROM Bit Select Register (PEBSR) The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM array. Reset clears all the bits in the PEPROM bit select register. BIT 7 PEBSR $000E reset: R W PEB7 0 BIT 6 PEB6 0 BIT 5 PEB5 0 BIT 4 PEB4 0 BIT 3 PEB3 0 BIT 2 PEB2 0 BIT 1 PEB1 0 BIT 0 PEB0 0 Figure 16-2. PEPROM Bit Select Register (PEBSR) PEB7 and PEB6 — Not connected to the PEPROM array These read/write bits are available as storage locations. Reset clears PEB7 and PEB6. PEB5–PEB0 — PEPROM Bit Select Bits These read/write bits select one of 64 bits in the PEPROM as shown in Table 16-1. Bits PEB2–0 select the PEPROM row, and bits PEB5–3 select the PEPROM column. Reset clears PEB5–PEB0, selecting the PEPROM bit in row zero, column zero. 16.1.2 PEPROM Status and Control Register (PESCR) The PEPROM status and control register (PESCR) controls the PEPROM programming voltage. This register also transfers the PEPROM bits to the internal data bus and contains a flag bit when row zero is selected. BIT 7 PESCR $000F reset: R W PEDATA U BIT 6 0 0 BIT 5 PEPGM 0 BIT 4 0 0 BIT 3 0 0 BIT 2 0 0 BIT 1 0 0 BIT 0 PEPRZF 1 U = UNAFFECTED BY RESET Figure 16-3. PEPROM Status and Control Register (PESCR) PEDATA — PEPROM Data This read-only bit is the state of the PEPROM sense amplifier and shows the state of the currently selected bit. Reset does not affect the PEDATA bit. 1 = PEPROM data is a logic one. 0 = PEPROM data is a logic zero. MOTOROLA 16-2 PERSONALITY EPROM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION PEPGM — PEPROM Program Control This read/write bit controls the switches that apply the programming voltage on the IRQ/VPP pin to the selected PEPROM cell. Reset clears the PEPGM bit. 1 = Programming voltage applied to array bit. 0 = Programming voltage not applied to array bit. PEPRZF — PEPROM Row Zero Flag This read-only bit is set when the PEPROM bit select register selects the first row (row zero) of the PEPROM array. Selecting any other row clears PEPRZF. Monitoring PEPRZF can reduce the code needed to access one byte of eight PEPROM locations. Reset clears the PEPROM bit select register thereby setting the PEPRZF bit by default. 1 = Row zero selected. 0 = Row zero not selected. Table 16-1. PEPROM Bit Selection PEBSR $00 - $07 $08 - $0F $10 - $17 $18 - $1F $20 - $27 $28 - $2F $30 - $37 $38 - $3F PEPROM Bit Selected Row 0 - Row 7 Row 0 - Row 7 Row 0 - Row 7 Row 0 - Row 7 Row 0 - Row 7 Row 0 - Row 7 Row 0 - Row 7 Row 0 - Row 7 Column 0 Column 1 Column 2 Column 3 Column 4 Column 5 Column 6 Column 7 16.2 PEPROM PROGRAMMING The PEPROM can be programmed by user software with the VPP voltage level applied to the IRQ/VPP pin. The following sequence shows how to program each PEPROM bit: 1. Select a PEPROM bit by writing to the PEBSR. 2. Set the PEPGM bit in the PESCR. 3. Wait 3 milliseconds. 4. Clear the PEPGM bit. 5. Move to next PEPROM bit to be programmed in step 1. MC68HC05SB7 REV 2.1 PERSONALITY EPROM MOTOROLA 16-3 GENERAL RELEASE SPECIFICATION August 27, 1998 NOTE While the PEPGM bit is set and the VPP voltage level is applied to the IRQ/VPP pin, do not access bits that are to be left unprogrammed (erased). To program the PEPROM, VDD must be greater than 4.5 Vdc. 16.3 PEPROM READING The following sequence shows how to read the PEPROM: 1. Select a bit by writing to the PEBSR. 2. Read the PEDATA bit in the PESCR. 3. Store the PEDATA bit in RAM or in a register. 4. Select another bit by changing the PEBSR. 5. Continue reading and storing the PEDATA bits until the required personality EPROM data is retrieved and stored. Reading the PEPROM is easiest when each PEPROM column contains one byte. Selecting a row 0 bit selects the first bit, and incrementing the PEPROM bit select register (PEBSR) selects the next bit in row 1 from the same column. Incrementing PEBSR seven more times selects the remaining bits of the column and ends up selecting the bit in row 0 of the next column, thereby setting the row 0 flag, PEPRZF. NOTE A PEPROM byte that has been read can be transferred to the personality EPROM bit select register (PEBSR) so that subsequent reads of the PEBSR quickly yield that PEPROM byte. 16.4 PEPROM ERASING MCUs with windowed packages permit PEPROM erasure with ultraviolet light. Erase the PEPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of a PEPROM bit is a logic zero. MOTOROLA 16-4 PERSONALITY EPROM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 16.5 PEPROM PREPROGRAMMED OPTIONS The MC68HC05SB7 is available with a factory preprogrammed PEPROM. The following measured parameters are available: • • • • The internal VCO minimum frequency: [programmed or left blank] The internal VCO maximum frequency: [programmed or left blank] The internal bandgap reference voltage: [programmed or left blank] The internal temperature sensor voltage: [programmed or left blank] Each parameter is stored as a 16-bit value in the PEPROM, as shown in the Table 16-1. Unprogrammed bits are blank, and are available for user programming. Table 16-2. PEPROM Preprogrammed Option PEBSR (LSB - MSB) $00 - $0F $10 - $1F $20 - $2F $30 - $3F Note: 1. measured at 80°C DATA VCO Minimum Frequency (fVCOMIN) VCO Maximum Frequency (fVCOMAX) Internal Bandgap Voltage (VIB) Temperature Sensor Voltage1 16.5.1 Data Format in Preprogrammed PEPROM The 16-bit value is a binary representation of the measured data (4 digits, with the decimal point removed). Some examples are shown below. For a measured data for fVCOMIN =1.500MHz, it is converted to 1500 or 5DC (hex) and the hex data is programmed as 0000 0101 1101 1100. For a measured data for fVCOMAX =5.800MHz, it is converted to 5800 or 16A8 (hex) and the hex data is programmed as 0001 0110 1010 1000. For a measured data for VIB =1.211V, it is converted to 1211 or 4BB (hex) and the hex data is programmed as 0000 0100 1011 1011. For a measured data for VTEMP =836.0mV, it is converted to 8360 or 20A8 (hex) and the hex data is programmed as 0010 0000 1010 1000. MC68HC05SB7 REV 2.1 PERSONALITY EPROM MOTOROLA 16-5 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 16-6 PERSONALITY EPROM MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 17 INSTRUCTION SET This section describes the addressing modes and instruction types. 17.1 ADDRESSING MODES The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following: • • • • • • • • Inherent Immediate Direct Extended Indexed, No Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset Relative 17.1.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. 17.1.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-1 GENERAL RELEASE SPECIFICATION August 27, 1998 17.1.3 Direct Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 17.1.4 Extended Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 17.1.5 Indexed, No Offset Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. 17.1.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. MOTOROLA 17-2 INSTRUCTION SET MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 17.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. 17.1.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 17.1.9 Instruction Types The MCU instructions fall into the following five categories: • • • • • Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-3 GENERAL RELEASE SPECIFICATION August 27, 1998 17.1.10 Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 17-1 lists the register/memory instructions. Table 17-1. Register/Memory Instructions Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB MOTOROLA 17-4 INSTRUCTION SET MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 17.1.11 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 17-2 lists the read-modify-write instructions. Table 17-2. Read-Modify-Write Instructions Instruction Arithmetic Shift Left Arithmetic Shift Right Clear Bit in Memory Set Bit in Memory Clear Complement (One’s Complement) Decrement Increment Logical Shift Left Logical Shift Right Negate (Two’s Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST 17.1.12 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-5 GENERAL RELEASE SPECIFICATION August 27, 1998 third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 17-3 lists the jump and branch instructions. Table 17-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MOTOROLA 17-6 INSTRUCTION SET MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 17.1.13 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 17-4 lists these instructions. Table 17-4. Bit Manipulation Instructions Instruction Clear Bit Branch if Bit Clear Branch if Bit Set Set Bit Mnemonic BCLR BRCLR BRSET BSET 17.1.14 Control Instructions These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 17-5, use inherent addressing. Table 17-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-7 GENERAL RELEASE SPECIFICATION August 27, 1998 17.1.15 Instruction Set Summary Table 17-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 17-6. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description HINZC Add with Carry A ← (A) + (M) + (C) ¤ — ¤ ¤ ¤ IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX A9 ii B9 dd C9 hh ll D9 ee ff E9 ff F9 AB ii BB dd CB hh ll DB ee ff EB ff FB A4 ii B4 dd C4 hh ll D4 ee ff E4 ff F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 dd Add without Carry A ← (A) + (M) ¤ — ¤ ¤ ¤ Logical AND A ← (A) ∧ (M) —— ¤ ¤ — Arithmetic Shift Left (Same as LSL) C b7 b0 0 —— ¤ ¤ ¤ ¤ ff dd Arithmetic Shift Right b7 b0 C —— ¤ ¤ ¤ DIR INH INH IX1 IX REL ff Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 ————— rr dd dd dd dd dd dd dd dd rr rr BCLR n opr Clear Bit n Mn ← 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— ————— REL REL BCS rel BEQ rel Branch if Carry Bit Set (Same as BLO) Branch if Equal PC ← (PC) + 2 + rel ? C = 1 PC ← (PC) + 2 + rel ? Z = 1 MOTOROLA 17-8 INSTRUCTION SET MC68HC05SB7 REV 2.1 Cycles 2 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 Effect on CCR Operand Address Mode August 27, 1998 GENERAL RELEASE SPECIFICATION Table 17-6. Instruction Set Summary (Continued) Opcode Source Form BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Description PC ← (PC) + 2 + rel ? H = 0 PC ← (PC) + 2 + rel ? H = 1 HINZC ————— ————— REL REL REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL 28 29 22 24 2F 2E rr rr rr rr rr rr PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — PC ← (PC) + 2 + rel ? C = 0 PC ← (PC) + 2 + rel ? IRQ = 1 PC ← (PC) + 2 + rel ? IRQ = 0 ————— ————— ————— Bit Test Accumulator with Memory Byte (A) ∧ (M) —— ¤ ¤ — A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 p 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 00 02 04 06 08 0A 0C 0E 21 rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC ← (PC) + 2 + rel ? C = 1 ————— PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — PC ← (PC) + 2 + rel ? I = 0 PC ← (PC) + 2 + rel ? N = 1 PC ← (PC) + 2 + rel ? I = 1 PC ← (PC) + 2 + rel ? Z = 0 PC ← (PC) + 2 + rel ? N = 0 PC ← (PC) + 2 + rel ? 1 = 1 ————— ————— ————— ————— ————— ————— BRCLR n opr rel Branch if bit n clear PC ← (PC) + 2 + rel ? Mn = 0 ———— ¤ BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 ———— ¤ BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 ————— MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-9 Cycles 3 3 3 3 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 Effect on CCR Operand Address Mode GENERAL RELEASE SPECIFICATION August 27, 1998 Table 17-6. Instruction Set Summary (Continued) Opcode Source Form Operation Description Cycles 5 5 5 5 5 5 5 5 6 2 2 dd 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 Effect on CCR HINZC BSET n opr Set Bit n Mn ← 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine Clear Carry Bit Clear Interrupt Mask PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel C←0 I←0 M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 ————— REL AD CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X ———— 0 — 0 ——— INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX 98 9A 3F 4F 5F 6F 7F Clear Byte —— 0 1 — Compare Accumulator with Memory Byte (A) – (M) —— ¤ ¤ ¤ A1 ii B1 dd C1 hh ll D1 ee ff E1 ff F1 33 43 53 63 73 dd Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) —— ¤ ¤ 1 Compare Index Register with Memory Byte (X) – (M) —— ¤ ¤ ¤ A3 ii B3 dd C3 hh ll D3 ee ff E3 ff F3 3A 4A 5A 6A 7A dd Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 —— ¤ ¤ — EXCLUSIVE OR Accumulator with Memory Byte A ← (A) ⊕ (M) —— ¤ ¤ — A8 ii B8 dd C8 hh ll D8 ee ff E8 ff F8 MOTOROLA 17-10 INSTRUCTION SET MC68HC05SB7 REV 2.1 Operand rr ff ff ff Address Mode August 27, 1998 GENERAL RELEASE SPECIFICATION Table 17-6. Instruction Set Summary (Continued) Opcode Source Form INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP Operation Description M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 HINZC Increment Byte —— ¤ ¤ — DIR INH INH IX1 IX DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH 3C 4C 5C 6C 7C dd ff Unconditional Jump PC ← Jump Address ————— BC dd CC hh ll DC ee ff EC ff FC BD dd CD hh ll DD ee ff ED ff FD A6 ii B6 dd C6 hh ll D6 ee ff E6 ff F6 AE ii BE dd CE hh ll DE ee ff EE ff FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D ii dd Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Conditional Address ————— Load Accumulator with Memory Byte A ← (M) —— ¤ ¤ — Load Index Register with Memory Byte X ← (M) —— ¤ ¤ — Logical Shift Left (Same as ASL) C b7 b0 0 —— ¤ ¤ ¤ ff dd Logical Shift Right 0 b7 b0 C —— 0 ¤ ¤ ff Unsigned Multiply X : A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) 0 ——— 0 11 5 3 3 6 5 2 Negate Byte (Two’s Complement) —— ¤ ¤ ¤ ff No Operation ————— MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-11 Cycles 5 3 3 6 5 2 3 4 3 2 5 6 7 6 5 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 Effect on CCR Operand Address Mode GENERAL RELEASE SPECIFICATION August 27, 1998 Table 17-6. Instruction Set Summary (Continued) Opcode Source Form ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description HINZC Logical OR Accumulator with Memory A ← (A) ∨ (M) —— ¤ ¤ — IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH AA ii BA dd CA hh ll DA ee ff EA ff FA 39 49 59 69 79 36 46 56 66 76 9C dd Rotate Byte Left through Carry Bit C b7 b0 —— ¤ ¤ ¤ ff dd Rotate Byte Right through Carry Bit C b7 b0 —— ¤ ¤ ¤ ff Reset Stack Pointer SP ← $00FF SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) ————— RTI Return from Interrupt ¤ ¤ ¤ ¤ ¤ INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X Return from Subroutine ————— INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX 81 A2 ii B2 dd C2 hh ll D2 ee ff E2 ff F2 99 9B B7 dd C7 hh ll D7 ee ff E7 ff F7 8E BF dd CF hh ll DF ee ff EF ff FF Subtract Memory Byte and Carry Bit from Accumulator A ← (A) – (M) – (C) —— ¤ ¤ ¤ Set Carry Bit Set Interrupt Mask C←1 I←1 ———— 1 — 1 ——— Store Accumulator in Memory M ← (A) —— ¤ ¤ — Stop Oscillator and Enable IRQ Pin — 0 ——— Store Index Register In Memory M ← (X) —— ¤ ¤ — MOTOROLA 17-12 INSTRUCTION SET MC68HC05SB7 REV 2.1 Cycles 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2 9 6 2 3 4 5 4 3 2 2 4 5 6 5 4 2 4 5 6 5 4 Effect on CCR Operand Address Mode August 27, 1998 GENERAL RELEASE SPECIFICATION Table 17-6. Instruction Set Summary (Continued) Opcode Source Form SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Operation Description HINZC Subtract Memory Byte from Accumulator A ← (A) – (M) —— ¤ ¤ ¤ IMM DIR EXT IX2 IX1 IX A0 ii B0 dd C0 hh ll D0 ee ff E0 ff F0 SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) — 1 ——— SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte X ← (A) ————— INH 83 10 TAX TST opr TSTA TSTX TST opr,X TST ,X TXA Transfer Accumulator to Index Register INH DIR INH INH IX1 IX INH 97 3D 4D 5D 6D 7D 9F dd Test Memory Byte for Negative or Zero (M) – $00 —— ¤ ¤ — ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts A ← (X) ————— WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n — 0 ——— opr PC PCH PCL REL rel rr SP X Z # ∧ ∨ ⊕ () –( ) ← ? : ¤ — INH 8F Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Loaded with If Concatenated with Set or cleared Not affected MC68HC05SB7 REV 2.1 INSTRUCTION SET MOTOROLA 17-13 Cycles 2 3 4 5 4 3 2 4 3 3 5 4 2 2 Effect on CCR Operand Address Mode Table 17-7. Opcode Map Read-Modify-Write DIR 3 3 5 3 3 6 5 9 2 3 4 5 4 Bit Manipulation Branch REL 2 BRA REL 2 3 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 6 2 IMM 2 2 DIR 3 3 EXT 3 4 IX2 2 5 Control IX 7 NEG RTS 1 INH 2 Register/Memory IMM A SUB CMP IMM 2 2 DIR 3 3 EXT 3 4 IX2 2 5 MOTOROLA 17-14 INH 4 NEGA CMP SBC DIR 3 3 EXT 3 4 DIR 5 NEGX CMP SBC CPX EXT 3 4 DIR 6 NEG CMP SBC IX2 2 5 INH 8 RTI CMP IX1 1 4 IX1 9 SUB SUB SUB SUB IX1 1 4 INH B C D E F 3 INH DIR EXT IX2 IX1 IX MSB LSB SUB IX 3 MSB LSB NEG 0 1 5 5 0 BRN REL 3 11 BRSET0 BSET0 3 DIR 2 5 DIR 2 5 0 CMP IX 3 1 BHI REL 3 5 3 6 5 10 1 INH 3 2 IMM 2 2 BRCLR0 MUL COM DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 IX 1 5 INH 2 IMM 2 2 DIR 3 3 BCLR0 SBC COMX LSRX INH 2 IX1 1 IX 2 IMM 2 2 DIR 3 3 3 DIR 2 5 DIR 2 5 1 SBC IX1 1 4 2 BLS REL 2 3 BRSET1 COMA LSRA INH 1 BSET1 COM LSR BIT 2 5 3 3 6 5 IMM 2 2 SBC IX 3 3 DIR 2 5 DIR 2 5 2 CPX IX2 2 5 IX1 1 4 3 COM LSR BIT DIR 3 3 BRCLR1 BCC REL 2 3 REL 3 DIR 1 BCLR1 LSR AND AND AND SWI CPX CPX CPX AND CPX IX 3 3 DIR 2 5 DIR 2 5 3 AND AND IX2 2 5 IX1 1 4 IX 3 4 BCS/BLO BNE REL 2 3 2 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 IX 5 2 IMM 2 BRSET2 BSET2 3 DIR 2 5 DIR 2 5 EXT 3 4 4 BIT EXT 3 4 5 ROR ASR DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 IX 5 1 INH 2 BRCLR2 RORA ASRA ASL/LSL IX 5 1 INH 2 2 BCLR2 RORX ASRX CLC SEC IX 5 1 INH 2 2 BIT IX2 2 5 BIT IX1 1 4 BIT IX 3 3 DIR 2 5 DIR 2 5 5 LDA LDA LDA LDA EXT 3 5 IX2 2 6 IX1 1 5 IX 4 6 ROR ASR EOR IMM 2 2 BRSET3 BEQ REL 2 3 BSET3 ASR TAX 2 2 ROR LDA LDA DIR 3 4 3 DIR 2 5 DIR 2 5 6 STA DIR 3 3 7 BHCC REL 2 3 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 BRCLR3 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ROL DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 BCLR3 STA EXT 3 4 STA IX2 2 5 STA IX1 1 4 STA IX 3 3 DIR 2 5 DIR 2 5 7 EOR DIR 3 3 8 BHCS REL 2 3 BRSET4 ROLA DECA INH 1 INH 2 IX1 1 IX BSET4 ROLX DECX DEC DEC 1 EOR EXT 3 4 EOR IX2 2 5 EOR IX1 1 4 EOR IX 3 3 DIR 2 5 DIR 2 5 8 ADC IMM 2 2 INSTRUCTION SET ROL ROL ADC BPL REL 2 3 DIR 1 9 DEC CLI BRCLR4 BCLR4 ADC DIR 3 3 EXT 3 4 ADC IX2 2 5 ADC IX1 1 4 ADC IX 3 3 DIR 2 5 DIR 2 5 9 ORA INH 2 2 IMM 2 2 A BMI REL 3 5 3 3 6 5 BRSET5 BSET5 ORA DIR 3 3 ORA EXT 3 4 ORA IX2 2 5 ORA IX1 1 4 ORA IX 3 3 DIR 2 5 DIR 2 5 A SEI 1 INH 2 2 B BMC REL 2 3 DIR 1 4 INH 1 3 INH 2 3 IX1 1 5 BRCLR5 INC TST DIR 1 INH 1 INH 2 IX1 1 BCLR5 INCA TSTA TSTX TST TST IX ADD IMM 2 ADD DIR 3 2 ADD EXT 3 3 ADD IX2 2 4 ADD IX1 1 3 ADD IX 2 3 DIR 2 5 DIR 2 5 B RSP JMP JMP JMP JMP JMP 1 INH 2 2 6 DIR 3 5 EXT 3 6 IX2 2 7 IX1 1 6 IX 5 C INCX INC INC IX 4 BRSET6 BMS REL 2 3 BSET6 3 DIR 2 5 DIR 2 5 C NOP 1 2 INH 2 D BIL REL 3 5 3 3 BRCLR6 BCLR6 BSR REL 2 2 JSR DIR 3 3 JSR EXT 3 4 JSR IX2 2 5 JSR IX1 1 4 JSR IX 3 3 DIR 2 5 DIR 2 5 D STOP 1 2 E BIH REL 2 DIR 1 INH 1 INH 2 BRSET7 CLR CLRA CLRX CLR BSET7 LDX IMM 2 6 5 2 INH 2 LDX DIR 3 4 LDX EXT 3 5 LDX IX2 2 6 LDX IX1 1 5 LDX IX 4 3 DIR 2 5 DIR 2 5 E CLR IX1 1 IX 1 F BRCLR7 BCLR7 WAIT INH 1 TXA INH 2 STX DIR 3 STX EXT 3 STX IX2 2 STX IX1 1 STX IX 3 DIR 2 DIR 2 F MSB LSB LSB of Opcode in Hexadecimal 0 3 0 MSB of Opcode in Hexadecimal 5 Number of Cycles BRSET0 Opcode Mnemonic DIR Number of Bytes/Addressing Mode MC68HC05SB7 REV 2.1 REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset INH = Inherent IMM = Immediate DIR = Direct EXT = Extended August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 18 ELECTRICAL SPECIFICATIONS This section describes the electrical and timing specifications of the MC68HC05SB7. 18.1 MAXIMUM RATINGS NOTE Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. The device is not intended to operate at these conditions. The MCU contains circuitry that protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range from VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Supply Voltage Bootloader Mode (IRQ/VPP Pin Only) Current Drain Per Pin Excluding VDD and VSS Operating Junction Temperature Storage Temperature Range Symbol VDD VIN I TJ Tstg Value –0.3 to +7.0 VSS – 0.3 to 17 25 +150 –65 to +150 Unit V V mA °C °C 18.2 OPERATING TEMPERATURE RANGE Characteristic Symbol TA Value TL to TH 0 to +70 Unit °C Operating Temperature Range MC68HC05SB7 (Standard) 18.3 THERMAL CHARACTERISTICS Characteristic Symbol θJA θJA Value 60 60 Unit °C/W °C/W Thermal Resistance SOIC SSOP MC68HC05SB7 REV 2.1 ELECTRICAL SPECIFICATIONS MOTOROLA 18-1 GENERAL RELEASE SPECIFICATION August 27, 1998 18.4 SUPPLY CURRENT CHARACTERISTICS Characteristic Symbol Min Typ Max Unit VDD = 4.5 to 5.5 Vdc Run, All Analog and LVR enabled Internal VCO at 2.5kHz External Oscillator at 4.2MHz Wait Internal VCO at 2.5kHz External Oscillator at 4.2 MHz Stop - all clocks disabled All Analog/LVR disabled and CSA enabled All Analog and LVR disabled All Analog disabled and LVR enabled All Analog and LVR enabled NOTES: 1. 2. 3. 4. IDD IDD — — 3 4.8 5 8 mA mA IDD IDD — — 1 1.3 1.5 2 mA mA µA µA µA µA IDD IDD IDD IDD — — — — 280 6 8 200 500 10 20 350 5. 6. 7. VDD as indicated, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25°C only. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50pF on all outputs, CL = 20pF on OSC2. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD – 0.2 VDC. Stop IDD measured with OSC1 = VDD. Wait IDD is affected linearly by the OSC2 capacitance. 18.5 PEPROM PROGRAMMING CHARACTERISTICS Characteristic Symbol VPP IPP tEPGM Min — — 2 Typ 13.7 3 — Max — 10 — Unit V mA ms PEPROM Programming Voltage PEPROM Programming Current PEPROM Programming Time per Byte NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. MOTOROLA 18-2 ELECTRICAL SPECIFICATIONS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 18.6 DC ELECTRICAL CHARACTERISTICS Characteristic Symbol VOL VOH VOH VOL Min — VDD – 0.1 VDD – 0.8 — — — — — — 0.7 X VDD VSS — — 1.1 2.0 Typ — — — — — — — — — — — — — 1.2 2.2 Max 0.1 — — 0.4 4 — 12 — 3 VDD 0.3 x VDD ±1 ±10 1.3 2.4 Unit V V V V mA mA mA mA mA V V µA µA V mV/°C Output Voltage Iload = 10.0 µA Iload = – 10.0 µA Output High Voltage (Iload = – 0.8 mA) PA0:7, PB1:7, PC4:7, RESET Output Low Voltage (Iload = 1.6 mA) PA0:7, PB1:7, PC4:7, RESET High Source Current (VOH = VDD – 0.5 to 1.0 Vdc) Source current per pin, PA0:7, PB1:7, PC4:7 Source current total for all pins High Sink Current (VOL = VSS + 1.5 Vdc) Sink current per pin, PA0:7, PB1:7, PC4:7 Sink current total for all pins High Source Current (VOH = VDD – 0.2Vdc) Source current for pin, ESV Input High Voltage PA0:7, PB1:7, PC4:7, RESET, OSC1, IRQ/VPP Input Low Voltage PA0:7, PB1:7, PC4:7, RESET, OSC1, IRQ/VPP Input Current PA0:7, PB1:7, PC4:7, RESET, OSC1, IRQ/VPP I/O Ports High-Z Leakage Current PA0:7, PB1:7, PC4:7 Internal Bandgap Voltage Internal Temperature Sensor Temperature Gradient IOH IOH IOL IOL IOH VIH VIL IIN IOZ VBG NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25°C only. MC68HC05SB7 REV 2.1 ELECTRICAL SPECIFICATIONS MOTOROLA 18-3 GENERAL RELEASE SPECIFICATION August 27, 1998 18.7 ANALOG SUBSYSTEM CHARACTERISTICS Characteristic Symbol VIO VCMR ICMP RDIV ISOURCE IRAMP IRAMP IDIS VIN Min 5 — — 0.49 80 — — 0.8 VSS Max 10 VDD – 1.5 150 0.51 120 220 1.0 — VDD – 1.5 Unit mV V µA µA µA %FS mA V Voltage Comparator Input Offset Voltage Voltage Comparator Input Common-Mode Range Voltage Comparator Supply Current Voltage Comparator Input Divider Ratio External Capacitor Current Source Current Source Supply Current Source Current Linearity Discharge Sink Current (VOUT = 0.4 V) External Capacitor Voltage Range Comparator Input Impedance Comparator Used as comparator only (DHOLD =0) Used as A/D function (DHOLD =1) Multiplexer Switch Resistance Internal Sample & Hold Capacitor Capacitance Charge/Discharge Time (0 to 3.5 VDC, DHOLD =0) Charge/Discharge Time (0 to 3.5 VDC, DHOLD =1) ZIN ZIN RMUX CSH tSHCHG tSHDCHG 0.8 80 4.5 4 20 60 — — 7 6 — — MΩ kΩ kΩ pF µs µs NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. MOTOROLA 18-4 ELECTRICAL SPECIFICATIONS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION 18.8 CONTROL TIMING Characteristic Symbol fOSC fOSC fOSC fOSC fOP fOP tCYC tRESL tTH, tTL tILIH tILIL tOH,tOL tPROP tDELAY tPROP tDELAY tDELAY Min 0.1 DC 1.5 0.5 0.05 DC 476 4.0 284 284 see note 3 110 — — — — — Max 4.2 4.2 5.8 4 2.1 2.1 — — — — — — 10 100 10 100 100 Unit MHz MHz MHz kHz MHz MHz ns tCYC ns ns tCYC ns µs µs µs µs µs Frequency of Oscillation (OSC) Crystal Oscillator Option External Clock Source Internal VCO (SCLK = 0)2 Internal VCO (SCLK = 1)2 Internal Operating Frequency, Crystal or External Clock (fOSC/2) Crystal Oscillator Option External Clock Source Cycle Time Crystal Oscillator or External Clock source Timer Resolution Input Capture (TCAP) pulse width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width (external clock input) Voltage Comparator Switching Time (10 mV overdrive, either input) Voltage Comparator Power Up Delay (Bias Circuit already powered up) External Capacitor Switching Time (IDIS to IRAMP) External Capacitor Current Source Power Up Delay (Bias Circuit already powered up) Bias Circuit Power Up Delay NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. 2. Due to process variations, operating voltages, and temperature requirements, the quoted VCO frequencies are typical limits, and should be treated as reference only. It is the user’s responsibility to ensure that the resulting internal operating frequency meets user’s requirement by setting the appropriate value in the VCO Adjust Register. 3. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. MC68HC05SB7 REV 2.1 ELECTRICAL SPECIFICATIONS MOTOROLA 18-5 GENERAL RELEASE SPECIFICATION August 27, 1998 18.9 RESET CHARACTERISTICS Characteristic Symbol VLVRR VLVRF VLVRH VPOR SVDDR SVDDF tRL tRPD Min 1.3 1.2 100 0 0.1 0.05 1.5 3 Typ 2.3 2.2 — — — — — — Max 3.1 3.0 — 100 — — — 4 Unit V V mV mV V/µs V/µs tCYC tCYC Low Voltage Reset Rising Recovery Voltage Falling Reset Voltage LVR Hysteresis POR Recovery Voltage2 POR VDD Slew Rising Falling Rate 2 RESET Pulse Width (when bus clock active) RESET Pulldown Pulse Width (from internal reset) NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. 2. By design, not tested. OSC11 tRL RESET 4096 tCYC2 Internal Clock3 Internal Address Bus3 Internal Data Bus3 1FFE 1FFF NEW PCH NEW PCL NEW PCH NEW PCL Op code NOTES: 1. Represents the internal gating of the OSC1 pin. 2. Normal delay of 4064 tCYC. 3. Internal timing signal and data information not available externally. Figure 18-1. Stop Recovery Timing Diagram MOTOROLA 18-6 ELECTRICAL SPECIFICATIONS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION Internal Reset1 RESET Pin tRPD Internal Clock3 4096 tCYC2 Internal Address Bus3 Internal Data Bus3 1FFE 1FFF NEW PCH NEW PCL NEW PCH NEW PCL NOTES: 1. Represents the internal reset from low voltage reset, illegal opcode fetch or COP Watchdog timeout. 2. Normal delay of 4064 tCYC. 3. Internal timing signal and data information not available externally. Figure 18-2. Internal Reset Timing Diagram VDD VLVRL VLVRH Low Voltage Reset RESET Pin1 tRPD Internal Clock3 4096 tCYC2 Internal Address Bus3 Internal Data Bus3 1FFE 1FFF NEW PCH NEW PCL NEW PCH NEW PCL NOTES: 1. RESET pin pulled down be internal device. 2. Normal delay of 4064 tCYC. 3. Internal timing signal and data information not available externally. Figure 18-3. Low Voltage Reset Timing Diagram MC68HC05SB7 REV 2.1 ELECTRICAL SPECIFICATIONS MOTOROLA 18-7 GENERAL RELEASE SPECIFICATION August 27, 1998 18.10 SM-BUS DC ELECTRICAL CHARACTERISTICS Characteristic LOW level input voltage HIGH level input voltage LOW level output voltage (open drain); at 2.86mA sink current (RPULLUP=1.7kΩ and CLOAD=400pF) Symbol VIL VIH VOL Min VSS 0.7 x VDD VSS Max 0.3 x VDD 5.5 0.135 Unit V V V NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. 2. For SM-Bus specification: logic "LOW"=0.6V or less; logic "HIGH"=1.4V or above. 18.11 SM-BUS CONTROL TIMING 18.11.1SM-Bus Interface Input Signal Timing Parameter Start condition hold time Clock low period SDA/SCL rise time Data hold time SDA/SCL fall time Clock high period Data set up time Start condition set up time (for repeated start condition only) Stop condition set up time Symbol tHD.STA tLOW tR tHD.DAT tF tHIGH tSU.DAT tSU.STA tSU.STO Min 2 4.7 — 300 — 4 250 2 2 Max — — 1 — 300 — — — — Unit tCYC tCYC µs ns ns tCYC ns tCYC tCYC NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. 18.11.2SM-Bus Interface Output Signal Timing Parameter Start condition hold time Clock low period SDA/SCL rise time Data hold time SDA/SCL fall time Clock high period Data set up time Start condition set up time (for repeated start condition only) Stop condition set up time Symbol tHD.STA tLOW tR tHD.DAT tF tHIGH tSU.DAT tSU.STA tSU.STO Min 8 11 — 300 — 11 tLOW–tCYC 10 10 Max — — 1 — 300 — — — — Unit tCYC tCYC µs ns ns tCYC ns tCYC tCYC NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. MOTOROLA 18-8 ELECTRICAL SPECIFICATIONS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION tR tF SDA SCL tHD.STA tLOW tHD.DAT tHIGH tSU.DAT tSU.STA tSU.STO Figure 18-4. SM-Bus Timing Diagram MC68HC05SB7 REV 2.1 ELECTRICAL SPECIFICATIONS MOTOROLA 18-9 GENERAL RELEASE SPECIFICATION August 27, 1998 MOTOROLA 18-10 ELECTRICAL SPECIFICATIONS MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION SECTION 19 MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 28-pin SOIC and 28-pin SSOP packages. 19.1 28 28-PIN SOIC (CASE 751F) -A15 14X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8° 0° 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8° 0° 0.395 0.415 0.010 0.029 -B1 14 P 0.010 (0.25) M B M 28X D 0.010 (0.25) M T A S B S M R X 45° -T26X C G K -TSEATING PLANE F J MC68HC05SB7 REV 2.1 MECHANICAL SPECIFICATIONS MOTOROLA 19-1 GENERAL RELEASE SPECIFICATION August 27, 1998 19.2 28-PIN SSOP 1.00 1.00 DIA. 3 2 1 D/2 2.36 DIA. PIN H+ 1.00 0.20 ME M E/2 HI L N I PP I NE 6 TOP VIEW 12-16° + e 0.12 b8 A A2 MT E D S BOTTOM VIEW -C-T3 0.076 -D4 A1 SEATING PLANE C 7 -ESEE DETAIL "A" 4 SIDE VIEW 0.235 MIN END VIEW b1 0° MIN. GAUGE PLANE PARTING LINE R c G 0.25 BSC M L G 5 SEATING PLANE L1 SECTION G-G DETAIL 'A' NOTES: 1. MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES). 2. DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982. 3. "T" IS A REFERENCE DATUM. 4. "D" & "E" ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE, MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE. 5. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. 6. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. 7. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE. 8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.07mm AT LEAST MATERIAL CONDITION. 9. CONTROLLING DIMENSION: MILLIMETERS. 10. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS. 11. THIS PACKAGE OUTLINE DRAWING COMPLIES WITH JEDEC SPECIFICATION NO. MO-150 FOR THE LEAD COUNTS SHOWN S Y M B O L DIMENSIONS IN MM MIN. MAX. NOM. 1.73 0.05 1.68 0.25 0.25 0.09 0.09 10.07 5.20 7.65 0.63 1.86 0.13 1.73 — 0.30 — 0.15 10.20 5.30 0.65 BSC 7.80 0.75 1.25 REF. 28 4 0.15 1.99 0.21 1.78 0.38 0.33 0.20 0.16 10.33 5.38 7.90 0.95 DIMENSIONS IN INCH MIN. NOM. MAX. .068 .002 .066 .010 .010 .004 .004 .397 .205 .301 .025 .073 .005 .068 — .012 — .006 .402 .209 .0256 BSC .307 .030 .049 REF. 28 4 .006 .078 .008 .070 .015 .013 .008 .006 .407 .212 .311 .037 A A1 A2 b b1 c c1 D E e H L L1 N M R 0 0.09 8 0 .004 MOTOROLA 19-2 MECHANICAL SPECIFICATIONS S- P b WITH LEAD FINISH c1 8 BASE METAL 10 N O T E 8,10 10 10 10 4 4 5 6 8 MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION APPENDIX A MC68HC705SB7 This appendix describes the MC68HC705SB7, the emulation part for MC68HC05SB7. The entire MC68HC05SB7 data sheet applies to the MC68HC705SB7, with exceptions outlined in this appendix. A.1 INTRODUCTION The MC68HC705SB7 is an EPROM version of the MC68HC05SB7, and is available for user system evaluation and debugging. The MC68HC705SB7 is functionally identical to the MC68HC05SB7 with the exception of the 6106 bytes user ROM is replaced by 6106 bytes user EPROM. The mask option for the external pin oscillator on the MC68HC05SB7 is controlled by the Mask Option Register at $002F on the MC68HC705SB7. This device is available in 28-pin SOIC package. A.2 MEMORY The MC68HC705SB7 memory map is shown on Figure A-1. $0000 $002F $0030 $003F $0040 USER RAM 224 BYTES $011F $0120 $05FF $0600 USER EPROM 6144 BYTES $1DFF $1E00 $1FEF $1FF0 $1FFF BOOTLOADER ROM 496 BYTES USER VECTORS 16 BYTES STACK RAM 64 BYTES UNIMPLEMENTED 1248 BYTES $00C0 $00FF I/O REGISTERS 48 BYTES UNIMPLEMENTED 16 BYTES Figure A-1. MC68HC705SB7 Memory Map MC68HC05SB7 REV 2.1 MOTOROLA A-1 GENERAL RELEASE SPECIFICATION August 27, 1998 A.3 PERSONALITY EPROM (PEPROM) The 64-bit PEPROM is left blank for user programming. A.4 MASK OPTION REGISTER The EPROM programmable Mask Option Register is used for setting EPROM security and enabling the external pin oscillator. BIT 7 MOR $002F reset: erased: R W EPMSEC U 0 BIT 6 OSCS U 0 BIT 5 U BIT 4 U BIT 3 U BIT 2 U BIT 1 U BIT 0 U - U = UNAFFECTED BY RESET Figure A-2. MC68HC705SB7 Mask Option Register (MOR) EPMSEC — EPROM Security Bit 1 = Access to the EPROM array in non-user mode is denied. 0 = Access to the EPROM array in non-user mode is enabled. This write-only bit controls the non-user mode access to the EPROM array on the MCU. When programmed to “1”, any accesses of the EPROM locations will return undefined results. EPMSEC Programming The state of the EPMSEC security bit should be programmed using a programmer board (available from Motorola). In order to program the EPMSEC bit the desired state must be written to the MOR address and then the MPGM bit in the EPROG register must be used. The following sequence will program the EPMSEC bit: 1. Write the desired data to the EPMSEC bit in MOR. 2. Apply the programming voltage to the IRQ/VPP pin. 3. Set the MPGM bit in the EPROG. 4. Wait for the programming time (tMPGM). 5. Clear the MPGM bit in the EPROG. 6. Remove the programming voltage from the IRQ/VPP pin. Once the EPMSEC bit has been programmed to a “1”, access to the contents of the EPROM in the non-user mode will be denied. It is therefore recommended that the User EPROM in the part first be programmed and fully verified before setting the EPMSEC bit. OSCS — Oscillator Select Bit 1 = External pin oscillator (EPO) enabled. 0 = External pin oscillator (EPO) disabled. MOTOROLA A-2 MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION The OSCS bit enables the OSC1 and OSC2 pins for external oscillator connection. OSC1 replaces PB2/CS0 and OSC2 replaces PB3/CS1. This is selected by a mask option on the MC68HC05SB7 device. A.5 BOOTLOADER MODE Bootloader mode is entered upon the rising edge of RESET if IRQ/VPP pin is at VTST and PB1/TCAP at VDD. The Bootloader program is masked in the ROM area from $1E00 to $1FEF. This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from an external EPROM. The bootloader performs one programming pass at 1ms per byte then does a verify pass. A.6 EPROM PROGRAMMING This section describes how to program the 6160-byte EPROM and the EPROM security bit. In packages with no quartz window, the EPROM functions as one-time programmable ROM (OTPROM) Programming the on-chip EPROM is achieved by using the Program Control Register located at address $001E. The programming software copies to the 6144-byte space located at EPROM addresses $0600 – $1DFF and to the 16-byte space at addresses $1FF0 – $1FFF which includes the mask option register (MOR) at address $002F. Please contact Motorola for programming board availability. A.6.1 EPROM Programming Register (EPROG) The EPROM programming register shown in Figure A-3 contains the control bits for programming the EPROM and MOR. In normal operation, the EPROM programming register is a read-only register that contains all logic zeros. BIT 7 EPROG $001C reset: R W 0 0 0 0 0 UNIMPLEMENTED 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 ELAT 0 BIT 1 MPGM 0 BIT 0 EPGM 0 RESERVED FOR TEST Figure A-3. EPROM Programming Register (EPROG) EPGM — EPROM Programming This read/write bit applies the voltage from the IRQ/VPP pin to the EPROM. To write the EPGM bit, the ELAT bit must already be set. Clearing the ELAT bit also clears the EPGM bit. Reset clears EPGM. 1 = EPROM programming power switched on. 0 = EPROM programming power switched off. MC68HC05SB7 REV 2.1 MOTOROLA A-3 GENERAL RELEASE SPECIFICATION August 27, 1998 MPGM — Mask Option Register (MOR) Programming This read/write bit applies programming power from the IRQ/VPP pin to the MOR. Reset clears MPGM. 1 = MOR programming power switched on. 0 = MOR programming power switched off. ELAT — EPROM Bus Latch This read/write bit configures address and data buses for programming the EPROM array. EPROM data cannot be read when ELAT is set. Clearing the ELAT bit also clears the EPGM bit. Reset clears ELAT. 1 = Address and data buses configured for EPROM programming of the array. The address and data bus are latched in the EPROM array when a subsequent write to the array is made. Data in the EPROM array cannot be read. 0 = Address and data buses configured for normal operation. Whenever the ELAT bit is cleared the EPGM bit is also cleared. Both the EPGM and the ELAT bit cannot be set using the same write instruction. Any attempt to set both the ELAT and EPGM bit on the same write instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. A.6.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit in the EPROG register. 2. Write the desired data to the desired EPROM address. 3. Set the EPGM bit in the EPROG register for the specified programming time (tEPGM). 4. Clear the EPGM bit 5. Clear the ELAT bit The last two steps must be performed with separate CPU writes. CAUTION It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. Figure A-4 shows the flow required to successfully program the EPROM. MOTOROLA A-4 MC68HC05SB7 REV 2.1 August 27, 1998 GENERAL RELEASE SPECIFICATION START ELAT=1 Write EPROM byte EPGM=1 Wait 1ms EPGM=0 ELAT=0 Y Write additional byte? N END Figure A-4. EPROM Programming Sequence A.7 EPROM ERASING MCUs with windowed packages permit EPROM erasure with ultraviolet light. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of an EPROM bit is a logic one. MC68HC05SB7 REV 2.1 MOTOROLA A-5 GENERAL RELEASE SPECIFICATION August 27, 1998 A.8 EPROM PROGRAMMING SPECIFICATIONS Characteristic Symbol tMPGM VPP IPP tEPGM — 4 Min 4 Typ — 13.7 3 — Max — Unit µs V MOR Programming Time EPROM Programming Voltage EPROM Programming Current EPROM Programming Time per Byte 5 — mA µs NOTES: 1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted. MOTOROLA A-6 MC68HC05SB7 REV 2.1 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-800-441-2447 or 1-303-675-2140 JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MfaxTM, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE 1-602-244-6609; US and Canada ONLY 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax is a trademark of Motorola, Inc. © Motorola, Inc., 1998 HC05SB7GRS/H