MPC5553MZQ132

Freescale Semiconductor Data Sheet: Product Preview Document Number: MPC5553 Rev. 2, 03/2007 MPC5553 Microcontroller Data Sheet by: Microcontroller Division This document provides electrical specifications, pin assignments, and package diagrams for the MPC5553 microcontroller device. For functional characteristics, refer to the MPC5553/MPC5554 Microcontroller Reference Manual. Contents 1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 6 3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Electromagnetic Interference Characteristics . . . . . 9 3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10 3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 11 3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13 3.9 Oscillator and FMPLL Electrical Characteristics . . 20 3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22 3.11 H7Fa Flash Memory Electrical Characteristics . . . 23 3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 46 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 56 1 Overview The MPC5553 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the Power Architecture™ embedded technology. This family of parts contains many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family. The host processor core of this device complies with the Power Architecture embedded category that is 100% user-mode compatible (with floating point library) with the original Power PC™ user instruction set architecture (UISA). The embedded architecture has enhancements that improve the performance in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. This family of parts 4 © Freescale Semiconductor, Inc., 2007. All rights reserved. Overview contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM and 1.5 Mbyte internal Flash memory. The internal SRAM and flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5500 family are performed by an enhanced time processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIO) signals. The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps Ethernet/IEEE® 802.3 networks and is compatible with three different standard MAC (media access controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or 100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support. MPC5553 Microcontroller Data Sheet, Rev. 2.0 2 Freescale Semiconductor Ordering Information 2 Ordering Information M PC 5553 M ZP 80 R2 Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status Temperature Range M = –40° C to 125° C Package Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-free VF = 208MAPBGA SnPb VM = 208MAPBGA Pb-free ZQ = 324PBGA SnPb VZ = 324PBGA Pb-free Operating Frequency 80 = 80 MHz 112 = 112 MHz 132 = 132 MHz Tape and Reel Status R2 = Tape and seel (blank) = Trays Note: Not all options are available on all devices. Refer to Table 1. Qualification Status P = Pre qualification M = Full spec qualified Figure 1. MPC5500 Family Part Number Example Table 1. Orderable Part Numbers Speed (MHz) Freescale Part Number1 Package Description Nominal MPC5553MVR132 MPC5553MVR112 MPC5553MVR80 MPC5553MVZ132 MPC5553MVZ112 MPC5553MVZ80 MPC5553MVM132 MPC5553MVM112 MPC5553MVM80 MPC5553MZP132 MPC5553MZP112 MPC5553MZP80 MPC5553MZQ132 MPC5553MZQ112 MPC5553MZQ80 MPC5553 Lead 324 package MPC5553 Lead 416 package MPC5553 Lead-free 208 package MPC5553 Lead-free 324 package MPC5553 Lead-free 416 package 132 112 80 132 112 80 132 112 80 132 112 80 132 112 80 Max3 (fMAX) 132 114 82 132 114 82 132 114 82 132 114 82 132 114 82 –40° C 125° C –40° C 125° C –40° C 125° C –40° C 125° C –40° C 125° C Min (TL) Max (TH) Operating Temperature2 MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 3 Electrical Characteristics Table 1. Orderable Part Numbers (continued) Speed (MHz) Freescale Part Number1 Package Description Nominal MPC5553MVF132 MPC5553MVF112 MPC5553MVF80 1 Operating Temperature2 Min (TL) Max (TH) Max3 (fMAX) 132 114 82 132 MPC5553 Lead 208 package 112 80 –40° C 125° C All devices are PPC5553, rather than MPC5553, until the product qualifications. Not all configurations are available in the PPC parts. 2 The lowest operating temperature is referenced by TL; the highest operating temperature is referenced by TH. 3 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including any frequency modulation. 80 MHz parts allow for 80 MHz + 2% modulation. However, 132 MHz devices allow 128 MHz plus two percent frequency modulation only. 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Table 2. Absolute Maximum Ratings1 Spec 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic 1.5 V core supply voltage 3 Symbol VDD VPP VDDF VFLASH VSTBY VDDSYN VDD33 VRC33 VDDA VDDE 4 Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –1.06 –1.06 –0.3 –0.1 –VDDA –0.3 Max2 1.7 6.5 1.7 4.6 1.7 4.6 4.6 4.6 5.5 4.6 6.5 6.57 4.68 5.5 0.1 VDD 5.5 Unit V V V V V V V V V V V V V V V V Flash program/erase voltage Flash core voltage Flash read voltage SRAM standby voltage Clock synthesizer voltage 3.3 V I/O buffer voltage Voltage regulator control input voltage Analog supply voltage (reference to VSSA) I/O supply voltage (fast I/O pads) voltage5 4 I/O supply voltage (slow and medium I/O pads) DC input VDDEH powered I/O pads VDDE powered I/O pads VDDEH VIN 13 14 15 16 Analog reference high voltage (reference to VRL) VSS differential voltage VDD differential voltage VREF differential voltage VRH VSS – VSSA VDD – VDDA VRH – VRL MPC5553 Microcontroller Data Sheet, Rev. 2.0 4 Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Spec 17 18 19 20 21 22 23 24 25 26 27 28 29 1 Characteristic VRH to VDDA differential voltage VRL to VSSA differential voltage VDDEH to VDDA differential voltage VDDF to VDD differential voltage This spec has been moved to Table 9, spec 43a. VSSSYN to VSS differential voltage VRCVSS to VSS differential voltage Maximum DC digital input current (per pin, applies to all digital pins)5 9 Symbol VRH – VDDA VRL – VSSA VDDEH – VDDA VDDF – VDD VSSSYN – VSS VRCVSS – VSS IMAXD IMAXA TJ TSTG TSDR MSL Min –5.5 –0.3 –VDDA –0.3 Max2 5.5 0.3 VDDEH 0.3 Unit V V V V –0.1 –0.1 –2 –3 TL –55.0 — — 0.1 0.1 2 3 150.0 150.0 260.0 3 V V mA mA oC oC oC Maximum DC analog input current 10 (per pin, applies to all analog pins) Maximum operating temperature range 11 Die junction temperature Storage temperature range Maximum solder temperature 12 Moisture sensitivity level 13 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima can affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.5 V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC. 4 All functional non-supply I/O pins are clamped to V SS and VDDE, or VDDEH. 5 AC signal overshoot and undershoot of up to +/– 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 6 Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC current greater than –0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state. 7 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 8 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 9 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 10 Total injection current for all analog input pins must not exceed 15 mA. 11 Lifetime operation at these specification limits is not guaranteed. 12 Solder profile per CDF-AEC-Q100. 13 Moisture sensitivity per JEDEC test method A112. MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 5 Electrical Characteristics 3.2 Thermal Characteristics Table 3. Thermal Characteristics Package The shaded rows in the following table indicate information specific to a four-layer device. Spec MPC5553 Thermal Characteristic Symbol 208 MAPBGA 41 25 33 22 15 7 2 324 PBGA 30 21 24 17 12 8 2 416 PBGA 29 21 23 18 13 9 2 Unit 1 2 3 4 5 6 7 1 Junction to ambient 1, 2, natural convection (one-layer board) Junction to ambient , natural convection (four-layer board 2s2p) Junction to ambient (@200 ft./min., one-layer board) Junction to ambient (@200 ft./min., four-layer board 2s2p) Junction to board Junction to case 4 1, 3 RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT °C/W °C/W °C/W °C/W °C/W °C/W °C/W (four-layer board 2s2p) 6, 5 Junction to package top natural convection 2 3 4 5 6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 3.2.1 General Notes for Specifications at Maximum Junction Temperature An estimation of the device junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJA × PD) where: TA = ambient temperature for the package (oC) RθJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: MPC5553 Microcontroller Data Sheet, Rev. 2.0 6 Freescale Semiconductor Electrical Characteristics • • • • Construction of the application board (number of planes) Effective size of the board which cools the component Quality of the thermal and electrical connections to the planes Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: • One oz (35 micron nominal thickness) internal planes • Components are well separated • Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RθJB = junction-to-board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction-to-ambient thermal resistance (oC/W) RθJC = junction-to-case thermal resistance (oC/W) RθCA = case-to-ambient thermal resistance (oC/W) MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 7 Electrical Characteristics RθJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RθCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (ΨJT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TT = thermocouple temperature on top of the package (oC) ΨJT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. A small amount of epoxy is placed on the thermocouple junction and approximately 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA., 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the web at http://www.jedec.org. • 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. • 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. • 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. MPC5553 Microcontroller Data Sheet, Rev. 2.0 8 Freescale Semiconductor Electrical Characteristics 3.3 Package The MPC5553 is available in packaged form. Package options are listed in Section 2, “Ordering Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings. 3.4 Spec 1 2 3 4 5 6 7 1 EMI (Electromagnetic Interference) Characteristics Table 4. EMI Testing Specifications1 Characteristic Scan range Operating frequency VDD operating voltages VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages VPP, VDDEH, VDDA operating voltages Maximum amplitude Operating temperature Minimum 0.15 — — — — — — Typical — — 1.5 3.3 5.0 — — Maximum 1000 132 — — — 142 323 25 oC Unit MHz MHz V V V dBuV EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554 and applied to the MPC5500 family as generic EMI performance data. 2 Measured with single-chip EMI program. 3 Measured with expanded EMI program. 3.5 ESD Characteristics Table 5. ESD Ratings1, 2 Characteristic Symbol Value 2000 R1 C 1500 100 500 (all pins) 750 (corner pins) — — — 1 1 1 V Unit V Ω pF ESD for Human Body Model (HBM) HBM circuit description ESD for Field Induced Charge Model (FDCM) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) Interval of pulses 1 2 — — second All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. Device failure is defined as: if after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing will be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 9 Electrical Characteristics 3.6 Voltage Regulator Controller (VRC) and Power-On Reset (POR) Electrical Specifications Table 6. VRC/POR Electrical Specifications Spec 1 2 3 4 5 6 7 Characteristic 1.5 V (VDD) POR negated (ramp up) 1.5 V (VDD) POR asserted (ramp down) 3.3 V (VDDSYN) POR negated (ramp up) 3.3 V (VDDSYN) POR asserted (ramp down) RESET pin supply (VDDEH6) POR negated (ramp up)1 RESET pin supply (VDDEH6) POR asserted (ramp down)1 VRC33 voltage before the regulator controller allows the pass transistor to start turning on VRC33 voltage when the regulator controller allows the pass transistor to completely turn on2, 3 VRC33 voltage greater than the voltage at which the VRC keeps the 1.5 V supply in regulation4, 5 Current can be sourced by VRCCTL – 40o C 25o C 150o C (Tj) Symbol V_POR15 V_POR33 V_POR5 V_TRANS_START V_TRANS_ON V_VRC33REG I_VRCCTL6 Min 1.1 1.1 2.0 2.0 2.0 2.0 1.0 2.0 3.0 Max 1.35 1.35 2.85 2.85 2.85 2.85 2.0 2.85 — Units V V V V V V mA 11.0 9.0 7.5 VDD33_LAG — — — — 1.0 mA mA mA V 8 Voltage differential during power up such that: VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and VDDEH6 reach the V_POR33 and V_POR5 minimums respectively. Absolute value of slew rate on power supply pins Required gain: IDD / I_VRCCTL (@VDD = 1.35 V, fsys = fMAX)5, 7 – 40o C 25o C 150o C (Tj) 9 10 — BETA8 55.09 58.09 70.0 9 50 V/ms — — 500 — — — 1 2 3 4 5 6 7 8 VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to V_POR5. Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range. It is possible to reach the current limit during ramp up—do not treat this event as short circuit current. At peak current for device. Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance (less than 1 Ω). VRCCTL must have a nominal 1 μF phase compensation capacitor to ground. VDD must have a 20 μF (nominal) bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of eight 0.01 μF, two 0.1 μF, and one 1 μF capacitors around the package on the VDD supply signals. I_VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, V_VRCCTL = 2.2 V. Values are based on IDD from high-use applications as explained in the IDD Electrical Specification. BETA is measured on a per-part basis and is calculated as (IDD ÷ I_VRCCTL), and represents the worst-case external transistor BETA. MPC5553 Microcontroller Data Sheet, Rev. 2.0 10 Freescale Semiconductor Electrical Characteristics 9 Preliminary value. Final specification pending characterization. 3.7 Power-Up/Down Sequencing Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing, VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is nit used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).” Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33.” Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification. There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies are powered. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type). Table 7. Power Sequence Pin Status for Fast Pads Pin Status for Fast Pad Output Driver VDDE Low VDDE VDDE VDDE VDDE VDDE VDD33 — Low Low VDD33 VDD33 VDD33 VDD — Low VDD Low VDD VDD POR Asserted Asserted Asserted Asserted Asserted Negated pad_fc (fast) Low High High High impedance (Hi-Z) Hi-Z Functional MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 11 Electrical Characteristics Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and pad_sh (slow type). Table 8. Power Sequence Pin Status for Medium / Slow Pads Pin Status for Medium and Slow Pad Output Driver VDDEH Low VDDEH VDDEH VDDEH VDD — Low VDD VDD POR Asserted Asserted Asserted Negated pad_mh (medium) pad_sh (slow) Low High impedance (Hi-Z) Hi-Z Functional 3.7.1 Input Value of Pins During POR Dependent on VDD33 When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification applies during power up only. VDD33 has no lead or lag requirements when powering down. 3.7.2 Power-Up Sequence (VRC33 Grounded) The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET POR negate. VDDSYN and RESET Power VDD 2.0 V 1.35 V VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V Figure 2. Power-Up Sequence (VRC33 Grounded) MPC5553 Microcontroller Data Sheet, Rev. 2.0 12 Freescale Semiconductor Electrical Characteristics 3.7.3 Power-Down Sequence (VRC33 Grounded) The only requirement for the power-down sequence when VRC33 is grounded is that if VDD decreases to less than its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power is allowed to increase to its operating range. This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset properly. 3.8 DC Electrical Specifications Table 9. DC Electrical Specifications Spec 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Characteristic Core supply voltage (average DC RMS voltage) I/O supply voltage (fast I/O) I/O supply voltage (slow / medium I/O) 3.3 V I/O buffer voltage Voltage regulator control input voltage Analog supply voltage1 Symbol VDD VDDE VDDEH VDD33 VRC33 VDDA VPP VFLASH VSTBY VDDSYN VIH_F VIL_F VIH_S VIL_S VHYS_F VHYS_S VINDC VOH_F VOH_S VOL_F VOL_S Min 1.35 1.62 3.0 3.0 3.0 4.5 4.5 3.0 0.8 3.0 0.65 × VDDE VSS – 0.3 Max 1.65 3.6 5.25 3.6 3.6 5.25 5.25 3.6 1.2 3.6 VDDE + 0.3 0.35 × VDDE Unit V V V V V V V V V V V V V V V V V V V V V pF pF pF pF Flash programming voltage2 Flash read voltage SRAM standby voltage3 Clock synthesizer operating voltage Fast I/O input high voltage Fast I/O input low voltage Medium / slow I/O input high voltage Medium / slow I/O input low voltage Fast I/O input hysteresis Medium / slow I/O input hysteresis Analog input voltage Fast I/O output high voltage ( IOH_F = –2.0 mA ) Slow / medium I/O output high voltage ( IOH_S = –2.0 mA ) Fast I/O output low voltage ( IOL_F = 2.0 mA ) Slow / medium I/O output low voltage ( IOL_S = 2.0 mA ) Load capacitance (fast I/O) DSC (SIU_PCR[8:9] ) = 0b00 DSC (SIU_PCR[8:9] ) = 0b01 DSC (SIU_PCR[8:9] ) = 0b10 DSC (SIU_PCR[8:9] ) = 0b11 4 0.65 × VDDEH VDDEH + 0.3 VSS – 0.3 0.35 × VDDEH 0.1 × VDDE 0.1 × VDDEH VSSA – 0.3 0.8 × VDDE 0.8 × VDDEH — — — — — — VDDA + 0.3 — — 0.2 × VDDE 0.2 × VDDEH 10 20 30 50 CL MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 13 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Spec 24 25 26 Characteristic Input capacitance (digital pins) Input capacitance (analog pins) Input capacitance (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[12]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) Symbol CIN CIN_A CIN_M Min — — — Max 7 10 12 Unit pF pF pF 27a Operating current5 1.5 V supplies @ 132 MHz: VDD (including VDDF max current)6, 7 @1.65 V typical use VDD (including VDDF max current)6, 7 @1.35 V typical use VDD (including VDDF max current) 7, 8 @1.65 V high use VDD (including VDDF max current)7, 8@1.35 V high use 27b Operating current 51.5 V supplies @ 114 MHz: VDD (including VDDF max current)6, 7@1.65 V typical use VDD (including VDDF max current)6, 7@1.35 V typical use VDD (including VDDF max current)7, 8 @1.65 V high use VDD (including VDDF max current)7, 8 @1.35 V high use 27c Operating current5 1.5 V supplies @ 82 MHz: VDD (including VDDF max current)6, 7 @1.65 V typical use VDD (including VDDF max current)6, 7 @1.35 V typical use VDD (including VDDF max current)7, 8 @1.65 V high use VDD (including VDDF max current)7, 8 @1.35 V high use 27d Refer to Figure 3 for an interpolation of this data. 10 IDDSTBY @ 25o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDDSTBY @ 60o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDDSTBY @ 150o C (Tj) VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V 28 Operating current 3.3 V supplies @ 132 MHz VDD3311 IDD33 — 2 + (values derived from procedure of Footnote 11) 10 15 mA IDD IDD IDD IDD — — — — 3509 2909 4009 3309 mA mA mA mA IDD IDD IDD IDD — — — — 4609 3809 5209 4209 mA mA mA mA IDD IDD IDD IDD — — — — 5509 4509 6009 4909 mA mA mA mA IDDSTBY IDDSTBY IDDSTBY — — — 20 30 50 μA μA μA μA μA μA μA μA μA IDDSTBY IDDSTBY IDDSTBY — — — 70 100 200 IDDSTBY IDDSTBY IDDSTBY — — — 1200 1500 2000 VFLASH VDDSYN IVFLASH IDDSYN — — mA mA MPC5553 Microcontroller Data Sheet, Rev. 2.0 14 Freescale Semiconductor Electrical Characteristics Table 9. DC Electrical Specifications (continued) Spec 29 Characteristic Operating current 5.0 V supplies (12 MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog reference supply current (VRH, VRL) VPP 30 Operating current VDDE12 supplies: VDDEH1 VDDE2 VDDE3 VDDEH4 VDDE5 VDDEH6 VDDE7 VDDEH8 VDDEH9 Fast I/O weak pullup current13 1.62–1.98 V 2.25–2.75 V 3.00–3.60 V Fast I/O weak pulldown current13 1.62–1.98 V 2.25–2.75 V 3.00–3.60 V 32 Slow / medium I/O weak pullup/down current14 3.0–3.6 V 4.5–5.5 V I/O input leakage current15 DC injection current (per pin) Analog input current, channel off 16 IACT_F 10 20 20 IACT_S IINACT_D IIC IINACT_A IINACT_AD VSS – VSSA VRL VRL – VSSA VRH VRH – VRL VSSSYN – VSS VRCVSS – VSS VDDF – VDD VRC33 – VDDSYN 10 20 – 2.5 – 2.0 –150 – 2.5 – 100 VSSA – 0.1 –100 VDDA – 0.1 4.5 –50 –50 –100 –0.1 100 130 170 150 170 2.5 2.0 150 2.5 100 VSSA + 0.1 100 VDDA + 0.1 5.25 50 50 100 0.1 18 Symbol Min Max Unit IDDA IREF IPP IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 — — — — — — — — — — — — 10 20 20 20.0 1.0 25.0 Refer to Footnote 12 mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA μA μA μA μA mA nA μA mV V mV V V mV mV mV V 31 110 130 170 33 34 35 35a Analog input current, shared analog / digital pins (AN[12], AN[13], AN[14], AN[15]) 36 37 38 39 40 41 42 43 VSS differential voltage17 Analog reference low voltage VRL differential voltage Analog reference high voltage VREF differential voltage VSSSYN to VSS differential voltage VRCVSS to VSS differential voltage VDDF to VDD differential voltage2 43a VRC33 to VDDSYN differential voltage MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 15 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Spec 44 45 46 1 2 Characteristic Analog input differential signal range (with common mode 2.5 V) Operating temperature range, ambient (packaged) Slew rate on power-supply pins Symbol VIDIFF TA = (TL to TH) — Min – 2.5 TL — Max 2.5 TH 50 Unit V οC V/ms | VDDA0 – VDDA1 | must be < 0.1 V. VPP can drop to 3.0 V during read operations. 3 During standby operation, if standby operation is not required, connect VSTBY to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Average current measured on Automotive benchmark. 7 Peak currents can be higher on specialized code. 8 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents are possible if an idle loop that crosses cache lines is run from cache. Design and write code to avoid this condition. 9 Preliminary. Final specification pending characterization. 10 Figure 3 shows an illustration of the IDD STBY values interpolated for these temperature values. 11 Power requirements for the V supply depend on the frequency of operation and load of all I/O pins, and the voltages on DD33 the I/O segments. Refer to Table 11 for values to calculate power dissipation for specific operation. 12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 13 Absolute value of current, measured at V and V . IL IH 14 Absolute value of current, measured at V and V . IL IH 15 Weak pullup/down inactive. Measured at V = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE 16 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae. 17 V SSA refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V. 18 Up to 0.6 V during power up and power down. MPC5553 Microcontroller Data Sheet, Rev. 2.0 16 Freescale Semiconductor Electrical Characteristics Figure 3 shows an approximate interpolation of the ISTBY worst-case specification to help estimate the values at different voltages and temperatures. The vertical lines inside the graph show the actual specifications listed in Table 9. Refer to the IDDSTBY specifications (27d) in Table 9 for more information. ISTBY Related to Junction Temperature 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0.8V 1.0V 1.2V µA Temperature (C) Figure 3. ISTBY Worst-case Specifications 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 17 Electrical Characteristics Table 10. I/O Pad Average DC Current1 Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 Pad Type Symbol Frequency (MHz) 25 Load2 (pF) 50 50 50 200 50 50 50 200 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 Voltage (V) 5.25 5.25 5.25 5.25 5.25 5.25 5.25 5.25 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 Drive Select / Slew Rate Control Setting 11 01 00 00 11 01 00 00 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Current (mA) 8.0 3.2 0.7 2.4 17.3 6.5 1.1 3.9 2.8 5.2 8.5 11.0 1.6 2.9 4.2 6.7 2.4 4.4 7.2 9.3 1.3 2.5 3.5 5.7 1.7 3.1 5.1 6.6 1.0 1.8 2.5 4.0 Slow IDRV_SH 10 2 2 50 20 3.33 3.33 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 Medium IDRV_MH Fast IDRV_FC These values are estimates from simulation and are not tested. Currents apply to output pins only. All loads are lumped. MPC5553 Microcontroller Data Sheet, Rev. 2.0 18 Freescale Semiconductor Electrical Characteristics 3.8.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. VDD33 Pad Average DC Current1 Spec Pad Type Symbol Frequency (MHz) Load2 (pF) Inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 VDD33 (V) VDDE (V) Drive Select Current (mA) Slow Medium I33_SH I33_MH 66 66 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 0.5 0.5 Outputs 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 5.5 5.5 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 NA NA 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0.003 0.003 0.35 0.53 0.62 0.79 0.35 0.44 0.53 0.7 0.30 0.45 0.52 0.67 0.30 0.37 0.45 0.60 0.21 0.31 0.37 0.48 0.21 0.27 0.32 0.42 Fast I33_FC These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 19 Electrical Characteristics 3.9 Oscillator and FMPLL Electrical Characteristics Table 12. FMPLL Electrical Specifications (VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic PLL reference frequency range: Crystal reference External reference Dual controller (1:1 mode) System frequency 1 System clock period Loss of reference frequency 3 Self clocked mode (SCM) frequency 4 EXTAL input high voltage crystal mode 5 Symbol Minimum Maximum Unit MHz 1 fref_crystal fref_ext fref_1:1 fsys tCYC fLOR fSCM VIHEXT 8 8 24 fICO(MIN) ÷ 2RFD — 100 7.4 VXTAL + 0.4 V [(VDDE5 ÷ 2) + 0.4 V] 20 20 fsys ÷ 2 fMAX 2 1 ÷ fsys 1000 17.5 MHz ns kHz MHz 2 3 4 5 — — V V 6 All other modes (dual controller (1:1), bypass, external reference) EXTAL input low voltage crystal mode 6 7 All other modes (dual controller (1:1), bypass, external reference) 8 9 10 11 XTAL current 7 Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL Crystal manufacturer’s recommended capacitive load Discrete load capacitance to connect to EXTAL Discrete load capacitance to connect to XTAL PLL lock time9 Dual controller (1:1) clock skew (between CLKOUT and EXTAL) 10, 11 Duty cycle of reference Frequency un-LOCK range Frequency LOCK range VILEXT IXTAL CS_XTAL CS_EXTAL CL CL_EXTAL CL_XTAL tlpll tskew tDC fUL fLCK — [(VDDE5 ÷ 2) – 0.4 V] 3 1.5 1.5 Refer to crystal specification (2 × CL) – CS_EXTAL – CPCB_EXTAL8 (2 × CL) – CS_XTAL – CPCB_XTAL8 750 2 V VIHEXT VILEXT — VXTAL – 0.4 V V 0.8 — — Refer to crystal specification — mA pF pF pF 12 pF 13 14 15 16 17 18 — pF μs ns — –2 40 – 4.0 – 2.0 60 4.0 2.0 % % fSYS % fSYS MPC5553 Microcontroller Data Sheet, Rev. 2.0 20 Freescale Semiconductor Electrical Characteristics Table 12. FMPLL Electrical Specifications (continued) (VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic CLKOUT period jitter,12, 13 measured at fSYS maximum peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over 2 ms interval) Frequency modulation range limit 14 (do not exceed fsys maximum) ICO frequency fico = [ fref × (MFD + 4) ] ÷ (PREDIV + 1)15 Predivider output frequency (to PLL) Symbol CJITTER — — 5.0 0.01 % fCLKOUT Minimum Maximum Unit 19 20 CMOD fico fPREDIV 0.8 2.4 %fSYS MHz 21 22 1 2 48 fsys fMAX 4 MHz All internal registers retain data at 0 Hz. Up to the maximum frequency rating of the device (refer to Table 1). 3 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked mode. 4 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f LOR. SCM frequency is measured on the CLKOUT ball with the divider set to divide-by-two of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 5 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vextal – Vxtal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock. 6 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vxtal – Vextal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock. 7I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 8C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal startup time. 10 PLL is operating in 1:1 PLL mode. 11 V DDE = 3.0–3.6 V 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider is set to divide-by-two. 13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 14 Modulation depth selected must not result in f sys value greater than the fsys maximum specified value. 15 f RFD). sys = fico ÷ (2 MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 21 Electrical Characteristics 3.10 Spec 1 2 3 4 5 6 7 8 9 10 11 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications (Operating) Characteristic ADC clock (ADCLK) frequency1 Conversion cycles Differential Single ended Stop mode recovery time2 Resolution 3 Symbol FADCLK CC Minimum 1 13 + 2 (15) 14 + 2 (16) Maximum 12 13 + 128 (141) 14 + 128 (142) — — 4 8 34 64 4 5 Unit MHz ADCLK cycles μs mV Counts3 Counts Counts Counts Counts Counts mA TSR — INL6 INL12 DNL6 DNL12 OFFWC GAINWC IINJ EINJ 10 1.25 –4 –8 –3 4 INL: 6 MHz ADC clock INL: 12 MHz ADC clock DNL: 6 MHz ADC clock DNL: 12 MHz ADC clock Offset error with calibration Full-scale gain error with calibration Disruptive input injection current 7, 8, 9, 10 –6 4 –4 5 –8 6 –1 86 1 12 Incremental error due to injection current. All channels have same 10 kΩ < Rs