MB15E05SR

FUJITSU SEMICONDUCTOR DATA SHEET DS04-21377-1E ASSP Single Serial Input PLL Frequency Synthesizer On-chip 2.0 GHz Prescaler MB15E05SR s DESCRIPTION The Fujitsu MB15E05SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz prescaler. The 2.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation. The supply voltage range is between 2.7 V and 5.0 V. A refined charge pump supplies well-balanced output currents of 1.0 mA and 4.0 mA. The charge pump current is selectable by serial data. The phase noise of MB15E05SR was drastically improved comparing wuth the former single PLL, MB15E05SL. The data format of serial data and the pin assignments except for φP φR and OSCout pins are same as the former , one, so it is easy to replace the former one. MB15E05SR is ideally suited for the base station of GSM (Global System for Mobile Communications) and PCS. s FEATURES • • • • High frequency operation: 2.0 GHz Max Low power supply voltage: VCC = 2.7 V to 5.0 V Ultra Low power supply current: ICC = 7.0 mA Typ (VCC = Vp = 3.75 V, Ta = +25°C, in locking state) Direct power saving function:Power supply current in power saving mode Typ 0.1 µA (VCC = Vp = 3.75 V, Ta = +25°C) (Continued) s PACKAGES 16-pin plastic TSSOP 16-pad plastic BCC (FPT-16P-M07) (LCC-16P-M06) MB15E05SR (Continued) • Dual modulus prescaler: 64/65 or 128/129 • Serial input 14-bit programmable reference divider: R = 3 to 16,383 • Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 • Software selectable charge pump current • On-chip phase control for phase comparator • Built-in digital locking detector circuit to detect PLL locking and unlocking. • Operating temperature: Ta = –40 °C to +85 °C s PIN ASSIGNMENTS 16-pin TSSOP OSCIN N.C. VP VCC DO GND Xfin fin 1 2 3 4 5 6 7 8 Top view 16-pad BCC N.C. N.C. LD/fout N.C. PS LE Data Clock N.C. VP VCC DO GND Xfin 1 2 16 15 14 13 3 Top view 12 4 11 5 10 6 7 8 9 N.C. LD/fout N.C. PS LE Data 16 15 14 13 12 11 10 9 OSCIN N.C. fin Clock (FPT-16P-M07) (LCC-16P-M06) 2 MB15E05SR s PIN DESCRIPTIONS Pin no. TSSOP 1 2 3 4 5 6 7 8 9 10 11 BCC 16 1 2 3 4 5 6 7 8 9 10 Pin name OSCIN N.C. VP VCC DO GND Xfin fin Clock Data LE I/O I – – – O – I I I I I Descriptions Programmable reference divider input. Connection to a TCXO. No connection. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be selected via programming of the FC bit. Ground. Prescaler complementary input, which should be grounded via a capacitor. Prescaler input. Connection to an external VCO should be done via AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. Power saving mode control. This pin must be set at “L” at Power-ON. (Open is prohibited.) PS = “H”; Normal mode PS = “L”; Power saving mode No connection. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected via programming of the LDS bit. LDS = “H”; outputs fout (fr/fp monitoring output) LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.) No connection. No connection. 12 13 14 15 16 11 12 13 14 15 PS N.C. LD/fout N.C. N.C. I – O – – 3 MB15E05SR s BLOCK DIAGRAM 1 OSCIN(16) Reference oscillator circuit Binary 14-bit reference couter 14-bit latch SW FC LDS CS 4-bit latch Phase comparator 12 PS(11) Intermittent mode control (power save) C N T Lock detector 19-bit shift register 11 LE (10) 1-bit control latch LD/fr/fp selector 14 LD/fout (13) 7-bit latch 11-bit latch Charge pump (2) 3 VP 5 (4) DO Data 10 (9) Binary 7-bit swallow counter Binary 11-bit programmable counter fp Clock 9 (8) Xfin 7 (6) 8 fin (7) Prescaler 64/65 128/129 SW 6 GND (5) 4 VCC (3) () : TSSOP : BCC 4 MB15E05SR s ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VP VI VO VO Tstg Condition – – – Except Do Do – Rating Min –0.5 VCC –0.5 GND GND –55 Max 5.5 6.0 VCC +0.5 VCC VP +125 Unit V V V V V °C Remark WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min 2.7 VCC GND –40 Typ 3.75 – – – Max 5.0 5.5 VCC +85 Unit V V V °C Remark WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB15E05SR s ELECTRICAL CHARACTERISTICS (VCC = 2.7 V to 5.0 V, Ta = –40 °C to +85 °C) Parameter Power supply current*1 Power saving current Operating frequency fin OSCIN fin*3 OSCIN*3 “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current “H” level output voltage “L” level output voltage “H” level output voltage “L” level output voltage High impedance cutoff current “H” level output current “L” level output current “H” level output current Do “L” level output current IDOL/ IDOH vs VDO vs Ta IDOL Data, Clock, LE, PS Data, Clock, LE, PS OSCIN LD/fout Do Do LD/fout Symbol ICC IPS fIN fosc Pfin VOSC VIH VIL IIH*4 IIL*4 IIH I IL*4 Condition fin = 2000 MHz, VCC = VP = 3.75 V PS = “L” – – 50 Ω system (Refer to the measurement circuit.) – – – – – – – VCC = VP = 3.75 V, IOH = –1 mA VCC = VP = 3.75 V, IOL = 1 mA VCC = VP = 3.75 V, IDOL = 0.5 mA VCC = VP = 3.75 V, VOFF = 0.5 V to VP – 0.5 V VCC = VP = 3.75 V VCC = VP = 3.75 V VCC = 3.75 V, VP = 3.75 V, VDO = VP/2, Ta = +25°C CS bit = “1” CS bit = “0” CS bit = “1” CS bit = “0” Value Min – – 300 3 –15 0.5 VCC × 0.7 – –1.0 –1.0 0 –100 VCC – 0.4 – – – – 1.0 – – – – – – – Typ 7.0 0.1 – – – – – – – – – – – – – – – – – –4.0 –1.0 4.0 1.0 5 10 3 *2 Max – 20 2000 40 +2 VCC – VCC × 0.3 +1.0 +1.0 +100 0 – 0.4 – 0.4 2.5 –1.0 – – – – – – – – Unit mA µA MHz MHz dBm Vp-p V µA µA V V nA mA Input sensitivity VOH VOL VDOH VDOL IOFF IOH IOL IDOH*4 VCC = VP = 3.75 V, IDOH = –0.5 mA VP – 0.4 mA IDOMT*5 VDO = VP/2 IDOVD*6 0.5 V ≤ VDO ≤ VP – 0.7 V IDOTA*7 – 40°C ≤ Ta ≤ +85°C, VDO = VP/2 % % % Charge pump current rate , *1: Conditions; fosc = 13 MHz, Vosc = 1.2 VPP Ta = +25°C, in locking state. *2: VCC = VP = 3.75 V, fosc = 13 MHz, Vosc = 1.2 VPP Ta = +25°C, in power saving mode , *3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency. *4: The symbol “–” (minus) means direction of current flow. *5: VCC = VP = 3.75 V, Ta = +25°C (||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%) (Continued) 6 MB15E05SR (Continued) *6: VCC = VP = 3.75 V, Ta = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH) *7: VCC = VP = 3.75 V, VDO = VP/2 (||IDO(+85°C)| – |IDO(–40°C)| |/2) / (|IDO(+85°C)| + |IDO(–40°C)| /2) × 100(%) (Applied to each IDOL, IDOH) I1 IDOL I3 I2 IDOH I2 I4 I1 0.5 VP/2 VP − 0.7 VP Charge Pump Output Voltage (V) 7 MB15E05SR s FUNCTIONAL DESCRIPTION 1. Pulse Swallow Function The divide ratio can be calculated using the following equation: fVCO = [(P × N) + A] × fOSC ÷ R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) P : Preset divide ratio of modulus prescaler (64 or 128) 2. Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high, stored data is latched according to the control bit data as follows: Table 1. Control Bit Control bit (CNT) H L (1) Shift Register Configuration Programmable Reference Counter LSB Data Flow 1 CNT 2 R1 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 10 11 12 13 14 15 16 17 18 19 MSB Destination of serial data For the programmable reference divider For the programmable divider R9 R10 R11 R12 R13 R14 SW FC LDS CS CNT R1 to R14 SW FC LDS CS : Control bit : Divide ratio setting bit for the programmable reference counter (3 to 16,383) : Divide ratio setting bit for the prescaler (64/65 or 128/129) : Phase control bit for the phase comparator : LD/fOUT signal select bit : Charge pump current select bit [Table 1] [Table 2] [Table 5] [Table 8] [Table 7] [Table 6] Note: Start data input with MSB first. 8 MB15E05SR Programmable Counter LSB 1 CNT 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 MSB Data Flow 9 N1 10 N2 11 N3 12 N4 13 N5 14 N6 15 N7 16 N8 17 18 19 N9 N10 N11 CNT : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note: Data input with MSB first. [Table 1] [Table 3] [Table 4] Table 2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio(R) 3 4 ⋅ 16383 R14 0 0 ⋅ 1 R13 0 0 ⋅ 1 R12 0 0 ⋅ 1 R11 0 0 ⋅ 1 R10 0 0 ⋅ 1 R9 0 0 ⋅ 1 R8 0 0 ⋅ 1 R7 0 0 ⋅ 1 R6 0 0 ⋅ 1 R5 0 0 ⋅ 1 R4 0 0 ⋅ 1 R3 0 1 ⋅ 1 R2 1 0 ⋅ 1 R1 1 0 ⋅ 1 Note: Divide ratio less than 3 is prohibited. Table 3. Binary 11-bit Programmable Counter Data Setting Divide ratio(N) 3 4 ⋅ 2047 N11 0 0 ⋅ 1 N10 0 0 ⋅ 1 N9 0 0 ⋅ 1 N8 0 0 ⋅ 1 N7 0 0 ⋅ 1 N6 0 0 ⋅ 1 N5 0 0 ⋅ 1 N4 0 0 ⋅ 1 N3 0 1 ⋅ 1 N2 1 0 ⋅ 1 N1 1 0 ⋅ 1 Note: Divide ratio less than 3 is prohibited. 9 MB15E05SR Table 4. Binary 7-bit Swallow Counter Data Setting Divide ratio (A) 0 1 ⋅ 127 A7 0 0 ⋅ 1 A6 0 0 ⋅ 1 A5 0 0 ⋅ 1 A4 0 0 ⋅ 1 A3 0 0 ⋅ 1 A2 0 0 ⋅ 1 A1 0 1 ⋅ 1 Table 5. Prescaler Data Setting SW 1 0 Prescaler divide ratio 64/65 128/129 Table 6. Charge Pump Current Setting CS 1 0 Current value ±4.0 mA ±1.0 mA Table 7. LD/fout Output Select Data Setting LDS 1 0 LD/fout output signal fout signal LD signal (2) Relation between the FC Input and Phase Characteristics The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and DO is shown below. Table 8. FC Bit Data Setting (LDS = “1”) FC = 1 DO fr > fP fr < fP fr = fP H L Z* fout = fr LD/fout DO L H Z* fout = fp FC = 0 LD/fout *: High impedance 10 MB15E05SR When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. • When the LPF and VCO characteristics are similar to (1), set FC bit high. • When the VCO characteristics are similar to (2), set FC bit low. (1) PLL LPF VCO VCO Output Frequency (2) LPF Output Voltage Note : Give attention to the polarity for using active type LPF. 11 MB15E05SR 3. Power Saving Mode (Intermittent Mode Control Circuit) Table 10. PS Pin Setting PS pin H L Normal mode Power saving mode Status The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the signal PLL, the lock detector, LD, remains high, indicating a locked condition. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : • When power (VCC) is first applied, the device must be in standby mode, PS = Low. • The serial data input after the power supply becomes stable and the the power saving mode is released after completed the data input.. OFF tV ≥ 1 µs ON VCC Clock Data LE tPS ≥ 100 ns PS (1) (2) (3) (1) PS = L (power saving mode) at Power ON (2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data. 12 MB15E05SR s SERIAL DATA INPUT TIMING 1st data Control bit ∼ Data MSB ∼ ∼ Clock LSB Invalid data 2nd data t1 t7 LE t2 t3 t6 ∼ t4 t5 On the rising edge of the clock, one bit of data is transferred into the shift register. Parameter t1 t2 t3 t4 Min 20 20 30 30 Typ – – – – Max – – – – Unit ns ns ns ns Parameter t5 t6 t7 Min 100 20 100 Typ – – – Max – – – Unit ns ns ns Note: LE should be “L” when the data is transferred into the shift register. 13 MB15E05SR s PHASE COMPARATOR OUTPUT WAVEFORM fr fp t WU t WL LD [FC = “1”] DO [FC = “0”] DO Notes: • Phase error detection range: –2π to +2π • Pulses on Do signal during locked state are output to prevent dead zone. • LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCIN input frequency. tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz) tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz) • LD becomes high during the power saving mode (PS = “L”). 14 MB15E05SR s MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) 1000 pF 1000 pF S.G. 50 Ω fin 8 Xfin GND 7 6 DO 5 VCC 4 VP 3 N.C. 2 OSCIN 1 50 Ω 0.1 µF 0.1 µF 1000 pF S.G. 9 10 11 12 PS 13 14 15 16 Clock Data LE Controller (setting divide ratio) N.C. LD/fout N.C. N.C. Oscilloscope VCC Note: TSSOP-16 15 MB15E05SR s TYPICAL CHARACTERISTICS 1. fin input sensitivity Input sensitivity - Input frequency 10 Ta = +25 °C Input sensitivity Pfin (dBm) 0 Catalog guaranteed range −10 −20 −30 −40 −50 0 500 1000 1500 2000 2500 3000 3500 4000 VCC = 2.7 V VCC = 3.75 V VCC = 5.0 V spec Input frequency fin (MHz) 2. OSCIN input sensitivity Input sensitivity - Input frequency 10.0 Ta = +25 °C 0.0 Catalog guaranteed range Input sensitivity VOSC (dBm) −10.0 −20.0 −30.0 VCC = 2.7 V VCC = 3.0 V VCC = 3.75 V VCC = 5.0 V SPEC 0 20 40 60 80 100 120 140 160 180 −40.0 −50.0 Input frequency fOSC (MHz) 16 MB15E05SR 3. Do output current 1.0 mA mode VDO - IDO Charge pump output current IDO (mA) 10.00 Ta = +25˚C, VCC = VP = 3.75 V 2.00m /div −10.00 0.00 1.00/div 7.00 Charge pump output voltage VDO (V) 4.0 mA mode VDO - IDO Charge pump output current IDO (mA) 10.00 Ta = +25˚C, VCC = VP = 3.75 V 2.00m /div −10.00 0.00 1.00/div 7.00 Charge pump output voltage VDO (V) 17 MB15E05SR 4. fin input impedance 4: 13.325 Ω 13.563 Ω 1.0793 nH 2 000.000 000 MHz 1 : 90.984 Ω −323.39 Ω 300 MHz 4 2 : 21.859 Ω −77.918 Ω 1 GHz 3 : 18.568 Ω −28.728 Ω 1.5 GHz 1 3 2 START 300.000 000 MHz STOP 2 000.000 000 MHz 5. OSCIN input impedance 4: 32.719 Ω −801.28 Ω 4.9656 pF 40.000 000 MHz 1: 633.5 Ω −9.258 kΩ 3 MHz 038.63 Ω −3.0145 kΩ 10 MHz 083.94 Ω −1.5534 kΩ 20 MHz 2: 3: 4 1 2 3 START 3.000 000 MHz STOP 40.000 000 MHz 18 MB15E05SR s REFERENCE INFORMATION Test Circuit S.G. OSCIN fin Do LPF fVCO = 1619.1 MHz KV = 44 MHz/V fr = 300 kHz fOSC = 19.2 MHz (2.6 VPP) LPF 27 kΩ 2.7 kΩ 15000 pF VCC =VP = 3.75 V VVCO = 3.0 V Ta = +25 °C CP : 4 mA mode Spectrum Analyzer 1000 pF VCO 120 pF PLL Reference Leakage ATTEN 10 dB RL 0 dBm VAVG 16 10 dB/ ∆MKR −81.83 dB 300 kHz ∆MKR 300 kHz −81.83 dB CENTER 1.619100 GHz VBW 10 kHz RBW 10 kHz SPAN 1.000 MHz SWP 50.0 ms PLL Phase Noise ATTEN 10 dB RL 0 dBm VAVG 16 10 dB/ ∆MKR −86.34 dB/Hz 1.00 kHz ∆MKR 1.00 kHz −86.34 dB/Hz CENTER 1.61910000 GHz VBW 30 Hz RBW 30 Hz SPAN 10.00 kHz SWP 1.92 s (Continued) 19 MB15E05SR (Continued) PLL Lock Up time 1607.1 MHz 1331.1 MHz, within ±1kHz Lch Hch 290 µs x : −289.99777 µs y : −23.8776 MHz PLL Lock Up time 1631.1 MHz 1607.1 MHz, within ±1kHz Hch Lch 300 µs x : −300.00071 µs y : −23.8754 MHz ® ∆Mkr ® ® ∆Mkr ® 100.0050 MHz 100.0050 MHz 2.0 kHz/div 2.0 kHz/div 99.9950 MHz 0s 1.5000000 s 99.9950 MHz 0s 1.5000000 s ∆Mkr x : −289.99777 µs y : −23.8776 MHz ∆Mkr x : −300.00071 µs y : −23.8754 MHz 120.0000 MHz 120.0000 MHz 10.0000 MHz/div 10.0000 MHz/div 70.0000 MHz 0s 1.5000000 s 80.0000 MHz 0s 1.5000000 s 20 MB15E05SR s APPLICATION EXAMPLE LPF Lock Det. VCO OUTPUT From a controller N.C. 16 N.C. 15 LD/fout 14 N.C. 13 PS 12 LE 11 Data 10 Clock 9 MB15E05SL 1 OSCIN 2 N.C. 3 VP 4 VCC 5 DO 6 GND 7 Xfin 8 fin 1000 pF 1000 pF 1000 pF TCXO 0.1 µF 0.1 µF VP: 5.5 V Max Note: TSSOP-16 s USAGE PRECAUTIONS To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting device into or removing device from a socket. -Protect leads with a conductive sheet when transporting a board-mounted device. 21 MB15E05SR s ORDERING INFORMATION Part number MB15E05SRPFT MB15E05SRPV1 Package 16-pin, Plastic TSSOP (FPT-16P-M07) 16-pad, Plastic BCC (LCC-16P-M06) Remarks 22 MB15E05SR s PACKAGE DIMENSIONS 16-pin, Plastic TSSOP (FPT-16P-M07) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17±0.05 (.007±.002) 9 *1 5.00±0.10(.197±.004) 16 INDEX *2 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) Details of "A" part 1.05±0.05 (Mounting height) (.041±.002) LEAD No. 1 8 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8˚ +0.03 +.001 (0.50(.020)) 0.60±0.15 (.024±.006) 0.07 –0.07 .003 –.003 (Stand off) 0.25(.010) 0.10(.004) C 2003 FUJITSU LIMITED F16020S-c-3-3 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 23 MB15E05SR (Continued) 16-pad plastic BCC (LCC-16P-M06) 4.55±0.10 (.179±.004) 14 9 0.80(.031)MAX Mounting height 0.40±0.10 (.016±.004) 0.80(.031) REF 0.65(.026) TYP 9 3.40(.134)TYP 0.325±0.10 (.013±.004) 14 INDEX AREA 3.40±0.10 (.134±.004) 2.45(.096) TYP "A" "B" 1.15(.045) REF 1 6 0.075±0.025 (.003±.001) (Stand off) 6 1.725(.068) REF 1 Details of "A" part 0.75±0.10 (.030±.004) 0.05(.002) Details of "B" part 0.60±0.10 (.024±.004) 0.40±0.10 (.016±.004) 0.60±0.10 (.024±.004) C 1999 FUJITSU LIMITED C16017S-1C-1 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 24 MB15E05SR FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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