MB96F378TSBPMC1-GSE2

FUJITSU SEMICONDUCTOR DATA SHEET FME-MB96370 rev 5 16-bit Proprietary Microcontroller CMOS F2MC-16FX MB96370 Series MB96F378*1/F379*1 ■ DESCRIPTION MB96370 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. PR Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.6 EL http://edevice.fujitsu.com/micom/en-support/ IM IN For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. AR Y MB96370 Series ■ FEATURES Feature Technology • 0.18µm CMOS • F2MC-16FX CPU • Up to 56 MHz internal, 17.8 ns instruction cycle time CPU • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) • 8-byte instruction execution queue • Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available • On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) • 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). • Up to 56 MHz external clock • 32-100 kHz subsystem quartz clock System clock Description • Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. • Clock modulator On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI tor and low power consumption figures Low voltage reset Code Security Memory Patch Function DMA Interrupts • Reset is generated when supply voltage is below minimum. • Protects ROM content from unintended read-out • Replaces ROM content • Can also be used to implement embedded debug support Timers 2 PR • Automatic transfer function independent of CPU, can be assigned freely to resources • Fast Interrupt processing • 8 programmable priority levels • Non-Maskable Interrupt (NMI) • Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) • Watchdog Timer EL IM • Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) IN • 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog AR Y FME-MB96370 rev 5 MB96370 Series Feature • ISO16845 certified • Bit rates up to 1 Mbit/s • 32 message objects CAN • Each message object has its own identifier mask • Programmable FIFO mode (concatenation of message objects) • Maskable interrupt • Disabled Automatic Retransmission mode for Time Triggered CAN applications • Full duplex USARTs (SCI/LIN) USART Description • Supports CAN protocol version 2.0 part A and B • Wide range of baud rate settings using a dedicated reload timer • Special synchronous options for adapting to different synchronous serial protocols • LIN functionality working either as master or slave LIN device • Master and Slave functionality, 7-bit and 10-bit addressing • SAR-type • 10-bit resolution • Up to 400 kbps A/D converter • 16-bit wide Reload Timers • Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency • Event count function • Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency • 16-bit wide • Signals an interrupt upon external event • Rising edge, falling edge or rising & falling edge sensitive • 16-bit wide • A pair of compare registers can be used to generate an output signal. • 16-bit down counter, cycle and duty setting registers • Interrupt at trigger, counter borrow and/or duty match • PWM operation and one-shot operation • Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer underflow as clock input • Can be triggered by software or reload timer Free Running Timers Input Capture Units Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs Programmable Pulse Generator FME-MB96370 rev 5 PR EL IM • Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer IN I2C AR • Programmable loop-back mode for self-test operation Y 3 MB96370 Series Feature Description • Stepper Motor Controller with integrated high current output drivers • Four high current outputs for each channel Stepper Motor Control- • Two synchronized 8/10-bit PWMs per channel ler • Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock • Separate power supply for high current output drivers • Internal or external voltage generation • Fixed 1/3 bias • Programmable frame period • LCD controller with up to 4 COM × 72 SEG • Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 • Clock source selectable from three options (peripheral clock, subclock or RC oscillator clock) LCD Controller • On-chip drivers for internal divider resistors or external divider resistors • LCD display can be operated in Timer Mode • Blank display: selectable • All SEG, COM and V pins can be switched between general and specialized purposes • External divided resistors can be also used to shut off the current when LCD is deactivated Sound Generator • 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter • Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator Real Time Clock • Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) • PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock • On-chip data memory for display External Interrupts Non Maskable Interrupt 4 PR • Read/write accessible second/minute/hour registers • Can signal interrupts every half second/second/minute/hour/day • Internal clock divider and prescaler provide exact 1s clock • Edge sensitive or level sensitive • Interrupt mask and pending bit per channel • Each available CAN channel RX has an external interrupt for wake-up • Selected USART channels SIN have an external interrupt for wake-up • Disabled after reset • Once enabled, can not be disabled other than by reset. • Level high or level low sensitive • Pin shared with external interrupt 0. EL IM IN AR Y FME-MB96370 rev 5 MB96370 Series Feature • 8-bit or 16-bit bidirectional data • Up to 24-bit addresses • 6 chip select signals External bus interface • Multiplexed address/data lines • Non-multiplexed address/data lines • Wait state request • External bus master possible • Timing programmable Description Alarm comparator • Threshold voltages defined externally or generated internally • Status is readable, interrupts can be masked separately • Virtually all external pins can be used as general purpose I/O • All push-pull outputs (except when used as I2C SDA/SCL line) • Bit-wise programmable as input/output or peripheral signal I/O Ports • Bit-wise programmable input enable • Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL • Bit-wise programmable pull-up resistor • Bit-wise programmable output driving strength for EMI optimization Packages • 144-pin plastic LQFP M08/12 • Supports automatic programming, Embedded Algorithm • Write/Erase/Erase-Suspend/Resume commands • A flag indicating completion of the algorithm • Number of erase cycles: 10,000 times Flash Memory • Data retention time: 20 years • Erase can be performed on each sector individually • Sector protection FME-MB96370 rev 5 PR • Flash Security feature to protect the content of the Flash • Low voltage detection during Flash erase EL IM IN AR • Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds Y 5 MB96370 Series ■ PRODUCT LINEUP Features Product type Product options MB96V300 Evaluation sample MB96(F)37x Flash product: MB96F37x Mask ROM product: MB9637x RS YW RW TS HS TW HW Flash/ROM 576KB [Flash A: 544KB, Flash B : 32KB] 832KB [Flash A: 544KB Flash B: 288KB] Package DMA USART I2C A/D Converter RAM 28KB Low voltage reset can be disabled / Single clock devices Low voltage reset persistently on / Dual clock devices Low voltage reset can be disabled / Dual clock devices indep. 32KB Flash / Low voltage reset persistently on / Single clock devices indep. 32KB Flash / Low voltage reset can be disabled / Single clock devices NA 32KB EL BGA416 16 channels 10 channels 2 channels 40 channels 6 channels + 1 channel (for PPG) 4 channels 12 channels 12 channels 20 channels ROM/Flash memory emulation by external RAM, 92KB internal RAM IM IN indep. 32KB Flash / Low voltage reset persistently on / Dual clock devices indep. 32KB Flash / Low voltage reset can be disabled / Dual clock devices PR 16-bit Reload Timer 16-bit Free-Running Timer 16-bit Output Compare 16-bit Input Capture 16-bit Programmable Pulse Generator 6 AR MB96F378T*1, MB96F378H*1 MB96F379Y*1, MB96F379R*1, FPT-144P-M08, FPT-144P-M12 7 channels 6 channels 2 channel 22 channels 4 channels + 1 channel (for PPG) 2 channels 6 channels 8 channels 12 channels Y YS Low voltage reset persistently on / Single clock devices FME-MB96370 rev 5 MB96370 Series Features CAN Interface Stepper Motor Controller External Interrupts Non-Maskable Interrupt Sound generator LCD Controller Real Time Clock I/O Ports Alarm comparator External bus interface Chip select Clock output function Low voltage reset On-chip RC-oscillator 136 2 channels MB96V300 5 channels 6 channels 16 channels MB96(F)37x 2 channels 6 channels 8 channels 1 channel 2 channels 4 COM x 72 SEG 1 IN FME-MB96370 rev 5 PR EL IM *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. AR Yes 6 signal Yes Yes 118 for part number with suffix "W", 120 for part number with suffix "S" Other the below: 2 channels 2 channels Y 7 MB96370 Series ■ BLOCK DIAGRAM Block diagram of MB96(F)37x AD00 ... AD15 A00 ... A23 ALE RDX WR(L)X, WRHX HRQ HAKX NMI RDY ECLK LBX, UBX CS0 ... CS5, CS3_R External Bus Interface 16FX CPU Interrupt Controller Flash Memory A CKOT0, CKOT1, CKOT0_R, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A *1 RSTX MD0...MD2 Y Flash Memory B Memory Patch Unit Clock & Mode Controller 16FX Core Bus (CLKB) AR RAM DMA Controller Watchdog Peripheral Bus Bridge Peripheral Bus Bridge Boot ROM Voltage Regulator SDA0, SDA1 SCL0, SCL1 AVCC AVSS AVRH AVRL AN0 ... AN21 ADTG TIN0 ... TIN3 TIN1_R, TIN2_R TOT0 ... TOT3 TOT1_R, TOT2_R FRCK0 FRCK0_R IN0 ... IN3 IN0_R ... IN3_R OUT0 ... OUT3 OUT0_R...OUT3_R I2C 2 ch. Peripheral Bus 2 (CLKP2) IN IM Peripheral Bus 1 (CLKP1) VCC VSS C TX0 ,TX1 RX0 , RX1 SGO0, SGO1, SGO0_R, SGO1_R SGA0, SGA1, SGA0_R, SGA1_R 10-bit ADC 22 ch. CAN Interface 2 ch. 16-bit Reload Timer 4 ch. Sound Generator 2 ch. SIN0...SIN5 SOT0...SOT5 SCK0...SCK5 ALARM0 ALARM1 TTG0 ... TTG11 PPG0 ... PPG11 I/O Timer 0 ICU 01/2/3 OCU 0/1/2/3 PR External Interrupt FRCK1 IN4 ... IN7 IN4_R ... IN7_R OUT4, OUT5 INT0 ... INT7 INT1_R ... INT7_R V0 ... V3 COM0 ... COM3 SEG0 ... SEG71 I/O Timer 1 ICU 4/5/6/7 OCU 4/5 EL RLT6 USART 6 ch. Alarm Comparator 2 ch.*2 16-bit PPG 12 ch. PPG0_R ... PPG5_R PWM1M0 ... PWM1M5 PWM1P0 ... PWM1P5 PWM2M0 ... PWM2M5 PWM2P0 ... PWM2P5 DVDD DVSS WOT LCD controller/ driver Stepper Motor Controller 6 ch. Real Time Clock *1: X0A, X1A only available on devices with suffix “W” 8 FME-MB96370 rev 5 MB96370 Series ■ PIN ASSIGNMENTS Pin assignment of MB96(F)37x 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 IM EL 2 3 4 5 6 7 8 Vss P00_3/INT6_R/A00/CS3_R/SEG15 P00_4/INT7_R/ALE/SEG16 P00_5/TTG2/TTG6/IN6/RDX/SEG17 P00_6/TTG3/TTG7/IN7/WRLX/WRX/SEG18 P00_7/SGO0/ECLK/SEG19 P01_0/SGA0/AD00/SEG20 P01_1/OUT0/CKOT1/AD01/SEG21 P01_2/OUT1/CKOTX1/AD02/SEG22 P01_3/PPG5/AD03/SEG23 P01_4/AD04/SIN4/SEG24 P01_5/AD05/SOT4/SEG25 P01_6/AD06/SCK4/SEG26 P01_7/CKOTX1_R/AD07/SEG27 P02_0/CKOT1_R/AD08/SEG28 P02_1/IN6_R/AD09/SEG29 P02_2/CKOT0_R/IN7_R/AD10/SEG30 P02_3/SGO0_R/AD11/SEG31 P02_4/SGA0_R/AD12/SEG32 P02_5/OUT0_R/AD13/SEG33 P02_6/OUT1_R/AD14/SEG34 P02_7/PPG5_R/AD15/SEG35 P16_0/PPG8/IN4 P16_1/PPG9/IN5 P03_0/V0/A16/SEG36 P03_1/V1/A17/SEG37 P03_2/V2/A18/SEG38 P03_3/V3/A19/SEG39 P03_4/INT4/RX0 P03_5/TX0 P03_6/NMI/INT0 P04_6/SDA1 P04_7/SCL1 P07_6/SEG71 P07_7 Vcc 108 106 104 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 107 105 103 101 109 72 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Y Vcc P16_7/OUT5/TTG11 P16_6/OUT4/TTG10 P16_5/IN3/TTG9 P16_4/IN2/TTG8 P00_2/INT5_R/RDY/SEG14 P00_1/INT4_R/WRHX/SEG13 P00_0/INT3_R/HAKX/SEG12 P12_7/INT1_R/HRQ/SEG11 P12_6/TOT2_R/A15/SEG10 P12_5/TIN2_R/A14/SEG9 P12_4/OUT3_R/A13/SEG8 P12_3/OUT2_R/A12/SEG7 P12_2/TOT1_R/A11/SEG6 P12_1/TIN1_R/A10/SEG5 P12_0/IN1_R/A09/SEG4 P11_7/IN0_R/A08/SEG3 P11_6/FRCK0_R/A07/SEG2 P11_5/PPG4_R/A06/SEG1 P11_4/PPG3_R/A05/SEG0 P11_3/PPG2_R/A04/COM3 P11_2/PPG1_R/A03/COM2 P11_1/PPG0_R/A02/COM1 P11_0/A01/COM0/CS5 P16_3/PPG11 P16_2/PPG10 RSTX X1A/P04_1 *1 X0A/P04_0 *1 Vss X1 X0 MD2 MD1 MD0 Vss 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Package code (mold) FPT-144P-M08/FPT-144P-M12 IN LQFP - 144 Vcc P10_3/PWM2M4/PPG7 P10_2/PWM2P4/SCK2/PPG6 P10_1/PWM1M4/SOT2/TOT3 P10_0/PWM1P4/SIN2/TIN3 P09_7/PWM2M3 DVss DVcc P10_7/PWM2M5 P10_6/PWM2P5 P09_6/PWM2P3 P09_5/PWM1M3 P09_4/PWM1P3 P09_3/PWM2M2 P09_2/PWM2P2 DVss DVcc P09_1/PWM1M2 P09_0/PWM1P2 P08_7/PWM2M1 P08_6/PWM2P1 P08_5/PWM1M1 P10_5/PWM1M5 P10_4/PWM1P5 DVss DVcc P08_4/PWM1P1 P08_3/PWM2M0 P08_2/PWM2P0 P08_1/PWM1M0 P08_0/PWM1P0 P05_7/AN15/TOT2/SGA1_R/SEG64 P05_6/AN14/TIN2/SGO1_R/SEG63 P05_5/AN13/TX1/SEG62 P05_4/AN12/RX1/INT2_R/SEG61 Vss 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Vss C P03_7/INT1/SIN1/CS0/A20/SEG40 P13_0/INT2/SOT1/CS1/A21/SEG41 P13_1/INT3/SCK1/CS2/A22/SEG42 P13_2/PPG0/TIN0/FRCK1/CS3/A23/SEG43 P13_3/PPG1/TOT0/WOT/UBX/SEG44 P13_4/SIN0/INT6/SEG45 P13_5/SOT0/ADTG/INT7/SEG46 P13_6/SCK0/CKOTX0/LBX/SEG47 P13_7/PPG2/CKOT0/CS4/SEG48 P04_4/PPG3/SDA0 P04_5/PPG4/SCL0 P07_4/AN20/SEG69 P07_5/AN21/SEG70 P06_0/AN0/SCK5/IN2_R/SEG49 P06_1/AN1/SOT5/IN3_R/SEG50 P06_2/AN2/INT5/SIN5/SEG51 P06_3/AN3/FRCK0/SEG52 P06_4/AN4/IN0/TTG0/TTG4/SEG53 P06_5/AN5/IN1/TTG1/TTG5/SEG54 P06_6/AN6/TIN1/IN4_R/SEG55 P06_7/AN7/TOT1//IN5_R/SEG56 AVcc AVRH AVRL AVss P05_0/AN8/ALARM0/SEG57 P05_1/AN9/ALARM1/SEG58 P05_2/AN10/OUT2/SGO1/SEG59 P05_3/AN11/OUT3/SGA1/SEG60 P07_0/SEG65/SIN3/AN16 P07_1/SEG66/SOT3/AN17 AR *1: Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1 PR (FPT-144P-M08/FPT-144P-M12) FME-MB96370 rev 5 P07_2/SEG67/SCK3/AN18 P07_3/SEG68/AN19 Vcc 9 MB96370 Series ■ PIN FUNCTION DESCRIPTION Pin Function description (1 of 3) Pin name ADn ADTG ALARMn ALE An ANn AVCC AVRH AVRL AVSS C CKOTn CKOTn_R CKOTXn CKOTXn_R COMn ECLK CSn CSn_R DVCC FRCKn FRCKn_R HAKX HRQ INn INn_R INTn INTn_R Feature External bus ADC Alarm comparator External bus External bus ADC Supply ADC ADC Supply Voltage regulator Clock output function Clock output function Clock output function Clock output function LCD Description External bus interface (non multiplexed mode) data input/ output. External bus interface (multiplexed mode) address output and data input/output Alarm Comparator n input External bus Address Latch Enable output External bus non-multiplexed address output A/D converter channel n input Analog circuits power supply A/D converter high reference voltage input Internally regulated power supply stabilization capacitor pin EL IM Relocated Clock Output function n inverted output LCD COM pins External bus clock output External bus chip select n output Relocated External bus chip select n output SMC pins power supply Free Running Timer n input Relocated Free Running Timer n input External bus Hold Acknowledge External bus Hold Request Input Capture Unit n input Relocated Input Capture Unit n input External Interrupt n input Relocated External Interrupt n input External bus External bus External bus Supply Free Running Timer Free Running Timer External bus External Interrupt External Interrupt 10 PR External bus ICU ICU IN A/D converter low reference voltage input Analog circuits power supply Relocated Clock Output function n output Clock Output function n inverted output AR Clock Output function n output Y A/D converter trigger input FME-MB96370 rev 5 MB96370 Series Pin Function description (2 of 3) Pin name LBX MDn NMI OUTn OUTn_R Pxx_n PPGn PPGn_R PWMn RDX RDY RSTX RXn SCKn SCLn SDAn SEGn SGA SGO SGA_R SGO_R SINn SOTn TINn TINn_R TOTn TOTn_R TTGn TXn UBX Feature External bus Core External Interrupt OCU OCU GPIO PPG PPG SMC External bus External bus Core CAN USART I2C I2C LCD Description External Bus Interface Lower Byte select strobe output Input pins for specifying the operating mode. Non-Maskable Interrupt input Output Compare Unit n waveform output Relocated Output Compare Unit n waveform output General purpose IO Relocated Programmable Pulse Generator n output SMC PWM high current IN IM External bus interface external wait state request input Reset input CAN interface n RX input Sound Generator EL Sound Generator Sound Generator Sound Generator PR USART USART Reload Timer Reload Timer Reload Timer Reload Timer PPG CAN External bus Programmable Pulse Generator n trigger input CAN interface n TX output External Bus Interface Upper Byte select strobe output FME-MB96370 rev 5 AR Programmable Pulse Generator n output External bus interface read strobe output USART n serial clock input/output I2C interface n clock I/O input/output I2C interface n serial data I/O input/output LCD segment n SG amplitude output SG sound/tone output Relocated SG amplitude output Relocated SG sound/tone output USART n serial data input USART n serial data output Reload Timer n event input Relocated Reload Timer n event input Reload Timer n output Relocated Reload Timer n output Y 11 MB96370 Series Pin Function description (3 of 3) Pin name Vn VCC VSS WOT WRHX WRLX/WRX X0 X0A X1 X1A Feature LCD Supply Supply RTC External bus External bus Clock Clock Clock Clock Description LCD voltage references Power supply Power supply Real Timer clock output External bus High byte write strobe output External bus Low byte / Word write strobe output Subclock Oscillator input (only for devices with suffix "W") Oscillator output Subclock Oscillator output (only for devices with suffix "W") 12 PR EL FME-MB96370 rev 5 IM IN AR Oscillator input Y MB96370 Series ■ PIN CIRCUIT TYPE Pin circuit types (1 of 2) FPT-144P-M08 or M12 Pin no. 1 2 3 to 11 12, 13 14 to 23 24 25 26, 27 28 to 35 36,37 38 to 41 42 to 46 47, 48 49 to 55 56, 57 58 to 64 65, 66 67 to 71 72, 73 74 to 76 77, 78 79 80, 81 80, 81 82 83, 84 85 to 103 104 to 107 108, 109 Circuit type *1 Supply F J N K Supply G Supply K Supply K M Supply M Supply M Supply M Supply C A Supply B *2 H *3 E H J H Supply FME-MB96370 rev 5 PR EL IM IN AR 13 Y MB96370 Series Pin circuit types (2 of 2) FPT-144P-M08 or M12 Pin no. 110 to 130 131, 132 133 to 136 137 to 139 140, 141 142 143 144 Circuit type *1 J H H N J H Supply 14 PR EL FME-MB96370 rev 5 IM IN *1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types *2: Devices with suffix ”W” *3: Devices without suffix ”W” AR Y L MB96370 Series ■ I/O CIRCUIT TYPE Type A X1 R Circuit Remarks High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Programmable feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode 0 MRFBE 1 Xout R FCI X0 FCI or osc disable B X1A R SRFBE R X0A C R EL osc disable Hysteresis inputs Pull-up Resistor R Hysteresis inputs IM • Mask ROM and EVA device: CMOS Hysteresis input pin • Flash device: CMOS input pin • CMOS Hysteresis input pin • Pull-up resistor value: approx. 50 kΩ E FME-MB96370 rev 5 PR IN Xout AR Low-speed oscillation circuit: • Programmable feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled Y 15 MB96370 Series Type F Circuit Remarks • Power supply input protection circuit G ANE AVR ANE H pull-up control Pout Nout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown 16 PR EL TTL input IM Hysteresis input Hysteresis input Automotive input IN AR • A/D converter ref+ (AVRH/AVRH2) power supply input pin with protection circuit • Flash devices do not have a protection circuit against VCC for pins AVRH/AVRH2 • Devices without AVRH reference switch do not have an analog switch for the AVRL pin • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. Y FME-MB96370 rev 5 MB96370 Series Type J pull-up control Circuit Remarks • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. • SEG or COM output Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Hysteresis input Automotive input TTL input SEG, COM output R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown PR FME-MB96370 rev 5 EL Nout IM pull-up control Pout Hysteresis input Hysteresis input Automotive input TTL input Analog input SEG output K IN AR • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function. • Programmable pull-up resistor: 50kΩ approx. • Analog input • SEG output 17 Y Nout MB96370 Series Type L pull-up control Circuit Remarks • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. • Analog input • Vx input • SEG output Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Hysteresis input Automotive input TTL input Analog input SEG output Vx input IM Hysteresis input Hysteresis input Automotive input TTL input M pull-up control R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown 18 PR EL Nout Pout IN • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL = 30mA, IOH = -30mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. FME-MB96370 rev 5 AR Y Nout MB96370 Series Type N pull-up control Circuit Remarks • CMOS level output (IOL = 3mA, IOH = -3mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. *1: N-channel transistor has slew rate control according to I2C spec, irrespective of usage Hysteresis input Pout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Automotive input TTL input FME-MB96370 rev 5 PR EL IM IN AR 19 Y Nout *1 MB96370 Series ■ MEMORY MAP MB96V300B FF:FFFFH MB96(F)37x Emulation ROM DE:0000H USER ROM / External Bus*4 External Bus External Bus 10:0000H 0F:E000H Boot-ROM Reserved 0E:0000H 02:0000H Internal RAM bank 1 01:0000H RAMEND1*2 IN *2 External RAM RAMSTART12 ROM/RAM MIRROR 00:8000H IM RAMSTART0 EL Internal RAM bank 0 RAMSTART0*3 00:0C00H External Bus Peripherals PR GPR*1 DMA External Bus Peripheral 00:0380H 00:0180H 00:0100H 00:00F0H 00:0000H *1: Unused GPR banks can be used as RAM area *2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the configuration of the emulated device. *4: For details about USER ROM area, see the ■ USER ROM MEMORY MAP FOR FLASH DEVICES on the following pages. The External Bus area and DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. 20 AR Boot-ROM Reserved Reserved Internal RAM bank 1 Reserved RAM availability depending on the device ROM/RAM MIRROR Internal RAM bank 0 Reserved External Bus end address*2 External Bus Peripherals GPR*1 DMA External Bus Peripheral Y FME-MB96370 rev 5 MB96370 Series ■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES Devices MB96F378 MB96F379 Bank 0 Bank 1 External Bus RAM size RAM size end address 28KByte 28KByte 4KByte 00:11FFH 00:11FFH RAMSTART0 00:1240H 00:1240H RAMSTART1 RAMEND1 01:8000H 01:8FFFH FME-MB96370 rev 5 PR EL IM IN AR 21 Y MB96370 Series ■ USER ROM MEMORY MAP FOR FLASH DEVICES MB96F378T MB96F378H Alternative mode CPU address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH MB96F379R MB96F379Y Flash size 832kByte Flash memory mode address 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H Flash size 576kByte AR External bus Reserved SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved SB3 - 8K SB2 - 8K SB1 - 8K SB0 - 8K *2 S39 - 64K S38 - 64K S37 - 64K S36 - 64K S35 - 64K S34 - 64K S33 - 64K S32 - 64K S39 - 64K S38 - 64K S37 - 64K S36 - 64K S35 - 64K S34 - 64K S33 - 64K S32 - 64K S31 - 64K S30 - 64K S29 - 64K S28 - 64K External bus E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:8000H DE:7FFFH DE:6000H DE:5FFFH DE:4000H DE:3FFFH DE:2000H DE:1FFFH DE:0000H *1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH *2: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH 22 PR 1E:7FFFH 1E:6000H 1E:5FFFH 1E:4000H 1E:3FFFH 1E:2000H 1E:1FFFH 1E:0000H EL 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H IM Reserved SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved SB3 - 8K SB2 - 8K SB1 - 8K SB0 - 8K *2 IN Y Flash A Flash B Flash A Flash B FME-MB96370 rev 5 MB96370 Series ■ SERIAL PROGRAMMING COMMUNICATION INTERFACE USART pins for Flash serial programming (MD[2:0] = 010) MB96F37x Pin number USART Number LQFP-144 8 9 10 3 4 5 68 69 70 32 33 34 USART3 USART2 USART1 USART0 Normal function SOT0 SCK0 SIN1 SOT1 SCK1 SIN2 SOT2 SCK2 SIN3 FME-MB96370 rev 5 PR EL Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor to support at least port P00_1 on pin 102. If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. IM SOT3 SCK3 IN AR 23 Y SIN0 MB96370 Series ■ I/O MAP I/O map MB96(F)37x (1 of 34) Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH00000FH 000010H 000011H000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H Register I/O Port P00 - Port Data Register I/O Port P01 - Port Data Register I/O Port P02 - Port Data Register I/O Port P03 - Port Data Register I/O Port P04 - Port Data Register I/O Port P05 - Port Data Register I/O Port P06 - Port Data Register I/O Port P07 - Port Data Register I/O Port P08 - Port Data Register I/O Port P09 - Port Data Register I/O Port P10 - Port Data Register I/O Port P11 - Port Data Register I/O Port P12 - Port Data Register I/O Port P13 - Port Data Register Reserved Abbreviation 8-bit access PDR00 PDR01 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PDR16 R/W ADCSL ADCSH ADCRL ADCRH ADSR ADCR ADCS R/W R/W R R R/W R/W ADECR R/W TCDT0 R/W R/W PDR03 PDR04 PDR05 PDR06 PDR07 PDR08 PDR09 PDR10 PDR11 PDR12 PDR13 I/O Port P16 - Port Data Register Reserved ADC0 - Control Status register Low ADC0 - Data Register Low ADC0 - Data Register High ADC0 - Setting Register ADC0 - Setting Register ADC0 - Extended Configuration Register Reserved FRT0 - Data register of free-running timer FRT0 - Data register of free-running timer 24 PR ADC0 - Control Status register High EL IM IN AR Y PDR02 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (2 of 34) Address 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH00003FH 000040H 000041H Register FRT0 - Control status register of free-running timer Low FRT0 - Control status register of free-running timer High FRT1 - Data register of free-running timer FRT1 - Data register of free-running timer FRT1 - Control status register of free-running timer Low FRT1 - Control status register of free-running timer High OCU0 - Output Compare Control Status OCU1 - Output Compare Control Status OCU0 - Compare Register OCU0 - Compare Register OCU1 - Compare Register OCU1 - Compare Register Abbreviation 8-bit access TCCSL0 TCCSH0 Abbreviation 16-bit access TCCS0 Access R/W R/W TCDT1 R/W R/W TCCS1 R/W R/W R/W R/W OCCP0 R/W R/W OCCP1 R/W R/W OCS2 OCS3 OCCP2 R/W R/W R/W R/W OCCP3 R/W R/W OCS4 OCS5 OCCP4 R/W R/W R/W R/W OCCP5 R/W R/W ICS01 ICE01 R/W R/W OCU2 - Output Compare Control Status OCU3 - Output Compare Control Status OCU2 - Compare Register OCU3 - Compare Register OCU3 - Compare Register OCU5 - Output Compare Control Status OCU4 - Compare Register OCU4 - Compare Register OCU5 - Compare Register OCU5 - Compare Register Reserved ICU0/ICU1 - Control Status Register ICU0/ICU1 - Edge register FME-MB96370 rev 5 PR OCU4 - Output Compare Control Status EL OCU2 - Compare Register IM IN AR OCS0 OCS1 Y TCCSL1 TCCSH1 25 MB96370 Series I/O map MB96(F)37x (3 of 34) Address 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH00005FH 000060H 000061H Register ICU0 - Capture Register Low ICU0 - Capture Register High ICU1 - Capture Register Low ICU1 - Capture Register High ICU2/ICU3 - Control Status Register ICU2/ICU3 - Edge register ICU2 - Capture Register Low ICU2 - Capture Register High ICU3 - Capture Register Low ICU3 - Capture Register High ICU4/ICU5 - Control Status Register ICU4/ICU5 - Edge register ICU4 - Capture Register Low ICU4 - Capture Register High ICU5 - Capture Register Low ICU5 - Capture Register High Abbreviation 8-bit access IPCPL0 IPCPH0 IPCPL1 IPCPH1 ICS23 ICE23 IPCP1 Abbreviation 16-bit access IPCP0 Access R R R R R/W R/W R R IPCP3 R R R/W R/W IPCP4 R R IPCP5 R R R/W R/W IPCP6 R R IPCP7 R R R/W R/W ELVR0 R/W R/W TMCSRL0 TMCSRH0 TMCSR0 R/W R/W AR IPCPL2 IPCPH2 IPCPL3 IPCPH3 ICS45 IM ICU6/ICU7 - Control Status Register ICU6/ICU7 - Edge register EL ICU6 - Capture Register Low ICU6 - Capture Register High ICU7 - Capture Register Low ICU7 - Capture Register High PR EXTINT0 - External Interrupt Enable Register EXTINT0 - External Interrupt Interrupt request Register EXTINT0 - External Interrupt Level Select Low EXTINT0 - External Interrupt Level Select High Reserved RLT0 - Timer Control Status Register Low RLT0 - Timer Control Status Register High 26 IN ICE45 IPCPL4 IPCPH4 IPCPL5 IPCPH5 ICS67 ICE67 IPCPL6 IPCPH6 IPCPL7 IPCPH7 ENIR0 EIRR0 ELVRL0 ELVRH0 Y IPCP2 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (4 of 34) Address 000062H 000062H 000063H 000063H 000064H 000065H 000066H 000066H 000067H 000067H 000068H 000069H 00006AH 00006AH 00006BH 00006BH 00006CH 00006DH 00006EH 00006EH 00006FH 00006FH 000070H 000071H 000072H 000072H 000073H Register RLT0 - Reload Register - for writing RLT0 - Reload Register - for reading RLT0 - Reload Register - for writing RLT0 - Reload Register - for reading RLT1 - Timer Control Status Register Low RLT1 - Timer Control Status Register High RLT1 - Reload Register - for writing RLT1 - Reload Register - for reading RLT1 - Reload Register - for writing RLT1 - Reload Register - for reading RLT2 - Timer Control Status Register Low TMCSRL1 Abbreviation 8-bit access Abbreviation 16-bit access TMRLR0 TMR0 Access W R W R Y TMCSR1 R/W R/W TMCSRH1 AR TMRLR1 TMR1 W R W R RLT2 - Timer Control Status Register High RLT2 - Reload Register - for writing IN TMCSRL2 TMCSR2 R/W R/W TMCSRH2 TMRLR2 TMR2 W R W R RLT2 - Reload Register - for writing RLT2 - Reload Register - for reading RLT3 - Timer Control Status Register Low IM RLT2 - Reload Register - for reading TMCSRL3 TMCSRH3 TMCSR3 R/W R/W RLT3 - Timer Control Status Register High RLT3 - Reload Register - for writing RLT3 - Reload Register - for reading RLT3 - Reload Register - for writing RLT3 - Reload Register - for reading RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) RLT6 - Timer Control Status Register High (dedic. RLT for PPG) RLT6 - Reload Register (dedic. RLT for PPG) - for writing RLT6 - Reload Register (dedic. RLT for PPG) - for reading RLT6 - Reload Register (dedic. RLT for PPG) - for writing EL TMRLR3 TMR3 W R W R PR TMCSRL6 TMCSRH6 TMCSR6 R/W R/W TMRLR6 TMR6 W R W FME-MB96370 rev 5 27 MB96370 Series I/O map MB96(F)37x (5 of 34) Address 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register RLT6 - Reload Register (dedic. RLT for PPG) - for reading PPG3-PPG0 - General Control register 1 Low PPG3-PPG0 - General Control register 1 High PPG3-PPG0 - General Control register 2 Low PPG3-PPG0 - General Control register 2 High PPG0 - Timer register PPG0 - Timer register PPG0 - Period setting register PPG0 - Period setting register PPG0 - Duty cycle register PPG0 - Duty cycle register PPG0 - Control status register Low PPG0 - Control status register High PPG1 - Timer register PPG1 - Timer register PPG1 - Period setting register PPG1 - Period setting register PPG1 - Duty cycle register PPG1 - Duty cycle register GCN1L0 GCN1H0 GCN2L0 GCN10 Abbreviation 8-bit access Abbreviation 16-bit access Access R R/W R/W GCN20 R/W R/W R R PCSR0 W W PDUT0 W W PCN0 R/W R/W PTMR1 R R PCSR1 W W PDUT1 W W PCNL1 PCNH1 PTMR2 PCN1 R/W R/W R R PCSR2 W W PDUT2 W W PCNL2 PCNH2 PCN2 R/W R/W GCN2H0 AR IM IN PCNL0 PCNH0 PPG1 - Control status register Low PPG2 - Timer register PPG2 - Timer register PPG2 - Period setting register PPG2 - Period setting register PPG2 - Duty cycle register PPG2 - Duty cycle register PPG2 - Control status register Low PPG2 - Control status register High 28 PR PPG1 - Control status register High EL Y PTMR0 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (6 of 34) Address 000090H 000091H 000092H 000093H 000094H 000095H 000096H 000097H 000098H 000099H 00009AH 00009BH 00009CH 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H 0000A3H 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH Register PPG3 - Timer register PPG3 - Timer register PPG3 - Period setting register PPG3 - Period setting register PPG3 - Duty cycle register PPG3 - Duty cycle register PPG3 - Control status register Low PPG3 - Control status register High PCSR3 Abbreviation 8-bit access Abbreviation 16-bit access PTMR3 Access R R W W Y AR PCNL3 PCNH3 PCNL4 PCNH4 PCNL5 PCNH5 IBSR0 IBCR0 GCN1L1 GCN1H1 GCN2L1 PDUT3 W W PCN3 R/W R/W PPG7-PPG4 - General Control register 1 Low GCN11 R/W R/W PPG7-PPG4 - General Control register 1 High PPG7-PPG4 - General Control register 2 Low PPG7-PPG4 - General Control register 2 High PPG4 - Timer register PPG4 - Timer register IN GCN21 R/W R/W GCN2H1 PTMR4 R R PPG4 - Period setting register PPG4 - Period setting register PPG4 - Duty cycle register PPG4 - Duty cycle register IM PCSR4 W W PDUT4 W W PPG4 - Control status register Low PPG4 - Control status register High PPG5 - Timer register PPG5 - Timer register EL PCN4 R/W R/W PTMR5 R R PPG5 - Period setting register PPG5 - Period setting register PPG5 - Duty cycle register PPG5 - Duty cycle register PPG5 - Control status register Low PPG5 - Control status register High I2C0 - Bus Status Register I2C0 - Bus Control Register PR PCSR5 W W PDUT5 W W PCN5 R/W R/W R R/W FME-MB96370 rev 5 29 MB96370 Series I/O map MB96(F)37x (7 of 34) Address 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH Register I2C0 - Ten bit Slave address Register Low I2C0 - Ten bit Slave address Register High I2C0 - Ten bit Address mask Register Low I2C0 - Ten bit Address mask Register High I2C0 - Seven bit Slave address Register I2C0 - Seven bit Address mask Register I2C0 - Data Register I2C0 - Clock Control Register I2C1 - Bus Status Register I2C1 - Bus Control Register I2C1 - Ten bit Slave address Register Low Abbreviation 8-bit access ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ITMK0 Abbreviation 16-bit access ITBA0 Access R/W R/W R/W R/W R/W R/W R/W R/W R R/W ITBA1 R/W R/W ITMK1 R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R/W R/W BGR0 R/W R/W R/W SMR1 R/W ISMK0 IDAR0 I2C1 - Ten bit Slave address Register High I2C1 - Ten bit Address mask Register Low I2C1 - Seven bit Slave address Register IM I2C1 - Ten bit Address mask Register High I2C1 - Seven bit Address mask Register I2C1 - Data Register I2C1 - Clock Control Register EL USART0 - Serial Mode Register USART0 - Serial Control Register USART0 - TX Register USART0 - RX Register PR USART0 - Serial Status USART0 - Control/Com. Register USART0 - Ext. Status Register USART0 - Baud Rate Generator Register Low USART0 - Baud Rate Generator Register High USART0 - Extended Serial Interrupt Register Reserved USART1 - Serial Mode Register 30 IN AR ICCR0 IBSR1 IBCR1 ITBAL1 ITBAH1 ITMKL1 ITMKH1 ISBA1 ISMK1 IDAR1 ICCR1 SMR0 SCR0 TDR0 RDR0 SSR0 ECCR0 ESCR0 BGRL0 BGRH0 ESIR0 Y FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (8 of 34) Address 0000CBH 0000CCH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H Register USART1 - Serial Control Register USART1 - TX Register USART1 - RX Register USART1 - Serial Status USART1 - Control/Com. Register USART1 - Ext. Status Register USART1 - Baud Rate Generator Register Low Abbreviation 8-bit access SCR1 TDR1 RDR1 SSR1 Abbreviation 16-bit access Access R/W W R R/W R/W R/W BGR1 R/W R/W R/W R/W R/W W R R/W R/W R/W BGR2 R/W R/W R/W SMR3 SCR3 TDR3 RDR3 SSR3 ECCR3 ESCR3 BGRL3 BGRH3 BGR3 R/W R/W W R R/W R/W R/W R/W R/W USART1 - Baud Rate Generator Register High USART1 - Extended Serial Interrupt Register Reserved USART2 - Serial Mode Register USART2 - Serial Control Register USART2 - TX Register USART2 - RX Register USART2 - Serial Status IN IM USART2 - Control/Com. Register USART2 - Ext. Status Register USART2 - Baud Rate Generator Register Low USART2 - Baud Rate Generator Register High USART2 - Extended Serial Interrupt Register Reserved EL USART3 - Serial Mode Register USART3 - Serial Control Register USART3 - TX Register USART3 - RX Register USART3 - Serial Status USART3 - Control/Com. Register USART3 - Ext. Status Register USART3 - Baud Rate Generator Register Low USART3 - Baud Rate Generator Register High FME-MB96370 rev 5 PR AR BGRL1 BGRH1 ESIR1 SMR2 SCR2 TDR2 RDR2 SSR2 ECCR2 ESCR2 BGRL2 BGRH2 ESIR2 Y ECCR1 ESCR1 31 MB96370 Series I/O map MB96(F)37x (9 of 34) Address 0000E6H 0000E7H0000EFH 0000F0H0000FFH 000100H 000101H 000102H 000103H 000104H 000105H 000106H 000107H 000108H 000109H 00010AH 00010BH 00010CH 00010DH 00010EH 00010FH 000110H 000111H 000112H 000113H 000114H 000115H 000116H 000117H 000118H 000119H Register USART3 - Extended Serial Interrupt Register Reserved External Bus area DMA0 - Buffer address pointer low byte DMA0 - Buffer address pointer middle byte DMA0 - Buffer address pointer high byte DMA0 - DMA control register DMA0 - I/O register address pointer low byte DMA0 - I/O register address pointer high byte DMA0 - Data counter low byte DMA0 - Data counter high byte DMA1 - Buffer address pointer low byte EXTBUS0 BAPL0 Abbreviation 8-bit access ESIR3 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W IOA0 R/W R/W DCT0 R/W R/W R/W R/W R/W R/W IOA1 R/W R/W DCT1 R/W R/W R/W R/W R/W R/W IOA2 R/W R/W DCT2 R/W R/W R/W R/W DMA1 - Buffer address pointer middle byte DMA1 - Buffer address pointer high byte DMA1 - DMA control register IM DMA1 - I/O register address pointer high byte DMA1 - Data counter low byte EL DMA1 - I/O register address pointer low byte DMA1 - Data counter high byte DMA2 - Buffer address pointer middle byte DMA2 - Buffer address pointer high byte DMA2 - DMA control register PR DMA2 - Buffer address pointer low byte DMA2 - I/O register address pointer low byte DMA2 - I/O register address pointer high byte DMA2 - Data counter low byte DMA2 - Data counter high byte DMA3 - Buffer address pointer low byte DMA3 - Buffer address pointer middle byte 32 IN AR BAPH0 DMACS0 IOAL0 IOAH0 DCTL0 DCTH0 BAPL1 BAPM1 BAPH1 DMACS1 IOAL1 IOAH1 DCTL1 DCTH1 BAPL2 BAPM2 BAPH2 DMACS2 IOAL2 IOAH2 DCTL2 DCTH2 BAPL3 BAPM3 BAPM0 Y FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (10 of 34) Address 00011AH 00011BH 00011CH 00011DH 00011EH 00011FH 000120H 000121H 000122H 000123H 000124H 000125H 000126H 000127H 000128H 000129H 00012AH 00012BH 00012CH 00012DH 00012EH 00012FH 000130H 000131H 000132H 000133H 000134H 000135H 000136H 000137H Register DMA3 - Buffer address pointer high byte DMA3 - DMA control register DMA3 - I/O register address pointer low byte DMA3 - I/O register address pointer high byte DMA3 - Data counter low byte DMA3 - Data counter high byte DMA4 - Buffer address pointer low byte Abbreviation 8-bit access BAPH3 DMACS3 IOAL3 IOAH3 IOA3 Abbreviation 16-bit access Access R/W R/W R/W R/W DCT3 R/W R/W R/W R/W R/W R/W IOA4 R/W R/W DCT4 R/W R/W R/W R/W R/W R/W IOA5 R/W R/W DCT5 R/W R/W R/W R/W R/W R/W IOA6 R/W R/W DCT6 R/W R/W DMA4 - Buffer address pointer middle byte DMA4 - Buffer address pointer high byte DMA4 - DMA control register DMA4 - I/O register address pointer high byte DMA4 - Data counter low byte DMA4 - Data counter high byte IN DMA4 - I/O register address pointer low byte DMA5 - Buffer address pointer low byte IM DMA5 - Buffer address pointer middle byte DMA5 - Buffer address pointer high byte DMA5 - DMA control register EL DMA5 - I/O register address pointer low byte DMA5 - I/O register address pointer high byte DMA5 - Data counter low byte DMA5 - Data counter high byte DMA6 - Buffer address pointer low byte DMA6 - Buffer address pointer middle byte DMA6 - Buffer address pointer high byte DMA6 - DMA control register DMA6 - I/O register address pointer low byte DMA6 - I/O register address pointer high byte DMA6 - Data counter low byte DMA6 - Data counter high byte PR FME-MB96370 rev 5 AR BAPL4 BAPM4 BAPH4 IOAL4 IOAH4 DCTL4 DCTH4 BAPL5 BAPM5 BAPH5 IOAL5 IOAH5 DCTL5 DCTH5 BAPL6 BAPM6 BAPH6 IOAL6 IOAH6 DCTL6 DCTH6 Y DCTL3 DCTH3 DMACS4 DMACS5 DMACS6 33 MB96370 Series I/O map MB96(F)37x (11 of 34) Address 000138H00017FH 000180H00037FH 000380H 000381H 000382H 000383H 000384H 000385H 000386H 000387H00038FH 000390H 000391H 000392H 000393H 000394H 000395H 000396H00039FH 0003A0H 0003A1H 0003A2H 0003A3H 0003A4H 0003A5H 0003A6H0003ABH 0003ACH 0003ADH 0003AEH Reserved CPU - General Purpose registers (RAM access) DMA0 - Interrupt select DMA1 - Interrupt select DMA2 - Interrupt select DMA3 - Interrupt select DMA4 - Interrupt select DMA5 - Interrupt select DMA6 - Interrupt select Reserved DMA - Status register low byte DMA - Status register high byte GPR_RAM Register Abbreviation 8-bit access Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W DSR R/W R/W DSSR R/W R/W DER R/W R/W ILR IDX TBRL TBRH DIRR NMI TBR ICR R/W R/W R/W R/W R/W R/W EDSU2L EDSU2H ROMM EDSU2 R/W R/W R/W DISEL1 DISEL2 DISEL3 DISEL4 DISEL5 DISEL6 DMA - Stop status register low byte IM DMA - Stop status register high byte DMA - Enable register low byte DMA - Enable register high byte Reserved EL Interrupt level register Interrupt vector table base register Low Interrupt vector table base register High Delayed Interrupt register Non Maskable Interrupt register Reserved EDSU communication interrupt selection Low EDSU communication interrupt selection High ROM mirror control register 34 PR Interrupt index register IN AR DSRL DSRH DSSRL DSSRH DERL DERH Y DISEL0 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (12 of 34) Address 0003AFH 0003B0H 0003B1H 0003B2H 0003B3H 0003B4H 0003B5H 0003B6H 0003B7H 0003B8H 0003B9H 0003BAH 0003BBH 0003BCH 0003BDH 0003BEH 0003BFH 0003C0H 0003C1H 0003C2H 0003C3H 0003C4H 0003C5H 0003C6H 0003C7H 0003C8H 0003C9H 0003CAH 0003CBH 0003CCH Register EDSU configuration register Memory patch control/status register ch 0/1 Memory patch control/status register ch 0/1 Memory patch control/status register ch 2/3 Memory patch control/status register ch 2/3 Memory patch control/status register ch 4/5 Memory patch control/status register ch 4/5 Memory patch control/status register ch 6/7 Memory patch control/status register ch 6/7 PFCS1 Abbreviation 8-bit access EDSU PFCS0 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W PFCS2 R/W R/W PFCS3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Memory Patch function - Patch address 0 low Memory Patch function - Patch address 0 high Memory Patch function - Patch address 1 low IN Memory Patch function - Patch address 0 middle Memory Patch function - Patch address 1 high Memory Patch function - Patch address 2 low Memory Patch function - Patch address 2 middle Memory Patch function - Patch address 2 high Memory Patch function - Patch address 3 low Memory Patch function - Patch address 3 middle Memory Patch function - Patch address 3 high Memory Patch function - Patch address 4 low Memory Patch function - Patch address 4 middle Memory Patch function - Patch address 4 high Memory Patch function - Patch address 5 low Memory Patch function - Patch address 5 middle Memory Patch function - Patch address 5 high Memory Patch function - Patch address 6 low Memory Patch function - Patch address 6 middle Memory Patch function - Patch address 6 high IM Memory Patch function - Patch address 1 middle EL PR FME-MB96370 rev 5 AR PFAL0 PFAM0 PFAH0 PFAL1 PFAM1 PFAH1 PFAL2 PFAM2 PFAH2 PFAL3 PFAM3 PFAH3 PFAL4 PFAM4 PFAH4 PFAL5 PFAM5 PFAH5 PFAL6 PFAM6 PFAH6 Y 35 MB96370 Series I/O map MB96(F)37x (13 of 34) Address 0003CDH 0003CEH 0003CFH 0003D0H 0003D1H 0003D2H 0003D3H 0003D4H 0003D5H 0003D6H 0003D7H 0003D8H 0003D9H 0003DAH 0003DBH 0003DCH 0003DDH 0003DEH 0003DFH 0003E0H0003F0H 0003F1H 0003F2H 0003F3H 0003F4H 0003F5H 0003F6H 0003F7H 0003F8H 0003F9H Register Memory Patch function - Patch address 7 low Memory Patch function - Patch address 7 middle Memory Patch function - Patch address 7 high Memory Patch function - Patch data 0 Low Memory Patch function - Patch data 0 High Memory Patch function - Patch data 1 Low Memory Patch function - Patch data 1 High Memory Patch function - Patch data 2 Low Memory Patch function - Patch data 2 High Memory Patch function - Patch data 3 Low Memory Patch function - Patch data 3 High Memory Patch function - Patch data 4 Low Abbreviation 8-bit access PFAL7 PFAM7 PFAH7 PFDL0 PFDH0 PFDL1 PFD0 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W PFD2 R/W R/W PFD3 R/W R/W PFD4 R/W R/W PFD5 R/W R/W PFD6 R/W R/W PFD7 R/W R/W MCSRA MTCRAL MTCRAH MTCRA R/W R/W R/W MCSRB MTCRBL MTCRBH FMWC0 FMWC1 MTCRB R/W R/W R/W R/W R/W Memory Patch function - Patch data 4 High Memory Patch function - Patch data 5 Low Memory Patch function - Patch data 5 High Memory Patch function - Patch data 6 Low IM Memory Patch function - Patch data 6 High Memory Patch function - Patch data 7 Low Memory Patch function - Patch data 7 High Reserved EL Memory Timing Configuration Register A Low Memory Timing Configuration Register A High Reserved Memory Control Status Register B Memory Timing Configuration Register B Low Memory Timing Configuration Register B High Flash Memory Write Control register 0 Flash Memory Write Control register 1 36 PR Memory Control Status Register A IN AR PFDH1 PFDL2 PFDH2 PFDL3 PFDH3 PFDL4 PFDH4 PFDL5 PFDH5 PFDL6 PFDH6 PFDL7 PFDH7 Y PFD1 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (14 of 34) Address 0003FAH 0003FBH 0003FCH 0003FDH 0003FEH0003FFH 000400H 000401H 000402H 000403H 000404H 000405H 000406H 000407H 000408H 000409H 00040AH 00040BH 00040CH 00040DH 00040EH 00040FH 000410H000414H 000415H 000416H 000417H 000418H 000419H 00041AH Register Flash Memory Write Control register 2 Flash Memory Write Control register 3 Flash Memory Write Control register 4 Flash Memory Write Control register 5 Reserved Standby Mode control register Clock select register Clock Stabilization select register Clock monitor register Clock Frequency control register Low Clock Frequency control register High PLL Control register Low PLL Control register High RC clock timer control register Abbreviation 8-bit access FMWC2 FMWC3 FMWC4 FMWC5 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R CKFCR R/W R/W PLLCR R/W R/W R/W R/W R/W R R/W R R/W W COAR COCR0 COCR1 CMCR R/W R/W R/W R/W CMPRL CMPR R/W IN IM Main clock timer control register Sub clock timer control register EL Reset cause and clock status register with clear function Reset configuration register Reset cause and clock status register Watch dog timer clear pattern register Reserved PR Watch dog timer configuration register Clock output activation register Clock output configuration register 0 Clock output configuration register 1 Clock Modulator control register Reserved Clock Modulator Parameter register Low FME-MB96370 rev 5 AR SMCR CKSR CKSSR CKMR PLLCRL RCTCR MCTCR SCTCR RCR RCCSR WDTC WDTCP Y CKFCRL CKFCRH PLLCRH RCCSRC 37 MB96370 Series I/O map MB96(F)37x (15 of 34) Address 00041BH 00041CH00042BH 00042CH 00042DH 00042EH00042FH 000430H 000431H 000432H 000433H 000434H 000435H 000436H 000437H 000438H 000439H 00043AH 00043BH 00043CH 00043DH 00043EH00043FH 000440H 000441H000443H 000444H 000445H 000446H 000447H 000448H Register Clock Modulator Parameter register High Reserved Voltage Regulator Control register Clock Input and LVD Control Register Reserved I/O Port P00 - Data Direction Register I/O Port P01 - Data Direction Register I/O Port P02 - Data Direction Register I/O Port P03 - Data Direction Register I/O Port P04 - Data Direction Register I/O Port P05 - Data Direction Register I/O Port P06 - Data Direction Register I/O Port P07 - Data Direction Register I/O Port P08 - Data Direction Register I/O Port P09 - Data Direction Register I/O Port P10 - Data Direction Register I/O Port P11 - Data Direction Register I/O Port P12 - Data Direction Register I/O Port P13 - Data Direction Register VRCR CILCR Abbreviation 8-bit access CMPRH Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DDR16 R/W PIER00 PIER01 PIER02 PIER03 PIER04 R/W R/W R/W R/W R/W IM EL I/O Port P16 - Data Direction Register Reserved I/O Port P00 - Port Input Enable Register I/O Port P01 - Port Input Enable Register I/O Port P02 - Port Input Enable Register I/O Port P03 - Port Input Enable Register I/O Port P04 - Port Input Enable Register 38 PR Reserved IN AR DDR00 DDR01 DDR02 DDR03 DDR04 DDR05 DDR06 DDR07 DDR08 DDR09 DDR10 DDR11 DDR12 DDR13 Y FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (16 of 34) Address 000449H 00044AH 00044BH 00044CH 00044DH 00044EH 00044FH 000450H 000451H 000452H000453H 000454H 000455H000457H 000458H 000459H 00045AH 00045BH 00045CH 00045DH 00045EH 00045FH 000460H 000461H 000462H 000463H 000464H 000465H 000466H000467H 000468H Register I/O Port P05 - Port Input Enable Register I/O Port P06 - Port Input Enable Register I/O Port P07 - Port Input Enable Register I/O Port P08 - Port Input Enable Register I/O Port P09 - Port Input Enable Register I/O Port P10 - Port Input Enable Register I/O Port P11 - Port Input Enable Register I/O Port P12 - Port Input Enable Register I/O Port P13 - Port Input Enable Register Reserved I/O Port P16 - Port Input Enable Register Reserved Abbreviation 8-bit access PIER05 PIER06 PIER07 PIER08 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PILR00 PILR01 PILR02 PILR03 PILR04 PILR05 PILR06 PILR07 PILR08 PILR09 PILR10 PILR11 PILR12 PILR13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PILR16 R/W IN I/O Port P00 - Port Input Level Register I/O Port P01 - Port Input Level Register I/O Port P02 - Port Input Level Register I/O Port P04 - Port Input Level Register I/O Port P05 - Port Input Level Register I/O Port P06 - Port Input Level Register I/O Port P08 - Port Input Level Register I/O Port P09 - Port Input Level Register I/O Port P10 - Port Input Level Register I/O Port P11 - Port Input Level Register I/O Port P12 - Port Input Level Register I/O Port P13 - Port Input Level Register Reserved I/O Port P16 - Port Input Level Register FME-MB96370 rev 5 PR I/O Port P07 - Port Input Level Register EL I/O Port P03 - Port Input Level Register IM AR PIER11 PIER12 PIER13 PIER16 Y PIER09 PIER10 39 MB96370 Series I/O map MB96(F)37x (17 of 34) Address 000469H00046BH 00046CH 00046DH 00046EH 00046FH 000470H 000471H 000472H 000473H 000474H 000475H 000476H 000477H 000478H 000479H 00047AH00047BH 00047CH 00047DH00047FH 000480H 000481H 000482H 000483H 000484H 000485H 000486H 000487H 000488H 000489H Reserved I/O Port P00 - Extended Port Input Level Register I/O Port P01 - Extended Port Input Level Register I/O Port P02 - Extended Port Input Level Register I/O Port P03 - Extended Port Input Level Register I/O Port P04 - Extended Port Input Level Register I/O Port P05 - Extended Port Input Level Register I/O Port P06 - Extended Port Input Level Register I/O Port P07 - Extended Port Input Level Register I/O Port P08 - Extended Port Input Level Register I/O Port P09 - Extended Port Input Level Register I/O Port P10 - Extended Port Input Level Register I/O Port P11 - Extended Port Input Level Register I/O Port P12 - Extended Port Input Level Register I/O Port P13 - Extended Port Input Level Register Reserved EPILR00 EPILR01 EPILR02 EPILR03 EPILR04 EPILR05 EPILR06 EPILR07 EPILR08 EPILR09 EPILR10 EPILR11 EPILR12 EPILR13 Register Abbreviation 8-bit access Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W EPILR16 R/W PODR00 PODR01 PODR02 PODR03 PODR04 PODR05 PODR06 PODR07 PODR08 PODR09 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Port P16 - Extended Port Input Level Register Reserved I/O Port P00 - Port Output Drive Register I/O Port P01 - Port Output Drive Register I/O Port P02 - Port Output Drive Register I/O Port P03 - Port Output Drive Register I/O Port P04 - Port Output Drive Register I/O Port P05 - Port Output Drive Register I/O Port P06 - Port Output Drive Register I/O Port P07 - Port Output Drive Register I/O Port P08 - Port Output Drive Register I/O Port P09 - Port Output Drive Register 40 PR EL IM IN AR Y FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (18 of 34) Address 00048AH 00048BH 00048CH 00048DH 00048EH00048FH 000490H 000491H00049BH 00049CH 00049DH 00049EH 00049FH0004A7H 0004A8H 0004A9H 0004AAH 0004ABH 0004ACH 0004ADH 0004AEH 0004AFH 0004B0H 0004B1H 0004B2H 0004B3H 0004B4H 0004B5H 0004B6H0004B7H 0004B8H Register I/O Port P10 - Port Output Drive Register I/O Port P11 - Port Output Drive Register I/O Port P12 - Port Output Drive Register I/O Port P13 - Port Output Drive Register Reserved I/O Port P16 - Port Output Drive Register Reserved I/O Port P08 - Port High Drive Register I/O Port P09 - Port High Drive Register I/O Port P10 - Port High Drive Register Reserved Abbreviation 8-bit access PODR10 PODR11 PODR12 PODR13 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W PUCR00 PUCR01 PUCR02 PUCR03 PUCR04 PUCR05 PUCR06 PUCR07 PUCR08 PUCR09 PUCR10 PUCR11 PUCR12 PUCR13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PUCR16 R/W IN I/O Port P01 - Pull-Up resistor Control Register I/O Port P02 - Pull-Up resistor Control Register I/O Port P03 - Pull-Up resistor Control Register I/O Port P04 - Pull-Up resistor Control Register I/O Port P05 - Pull-Up resistor Control Register I/O Port P06 - Pull-Up resistor Control Register I/O Port P07 - Pull-Up resistor Control Register I/O Port P08 - Pull-Up resistor Control Register I/O Port P09 - Pull-Up resistor Control Register I/O Port P10 - Pull-Up resistor Control Register I/O Port P11 - Pull-Up resistor Control Register I/O Port P12 - Pull-Up resistor Control Register I/O Port P13 - Pull-Up resistor Control Register Reserved I/O Port P16 - Pull-Up resistor Control Register FME-MB96370 rev 5 PR EL IM I/O Port P00 - Pull-Up resistor Control Register AR Y PODR16 PHDR08 PHDR09 PHDR10 41 MB96370 Series I/O map MB96(F)37x (19 of 34) Address 0004B9H0004BBH 0004BCH 0004BDH 0004BEH 0004BFH 0004C0H 0004C1H 0004C2H 0004C3H 0004C4H 0004C5H 0004C6H 0004C7H 0004C8H 0004C9H 0004CAH0004CBH 0004CCH 0004CDH0004CFH 0004D0H 0004D1H 0004D2H 0004D3H 0004D4H 0004D5H 0004D6H 0004D7H 0004D8H 0004D9H Reserved I/O Port P00 - External Pin State Register I/O Port P01 - External Pin State Register I/O Port P02 - External Pin State Register I/O Port P03 - External Pin State Register I/O Port P04 - External Pin State Register I/O Port P05 - External Pin State Register I/O Port P06 - External Pin State Register I/O Port P07 - External Pin State Register I/O Port P08 - External Pin State Register I/O Port P09 - External Pin State Register I/O Port P10 - External Pin State Register I/O Port P11 - External Pin State Register I/O Port P12 - External Pin State Register I/O Port P13 - External Pin State Register Reserved EPSR00 EPSR01 EPSR02 EPSR03 EPSR04 EPSR05 EPSR06 EPSR07 EPSR08 EPSR09 EPSR10 EPSR11 EPSR12 EPSR13 Register Abbreviation 8-bit access Abbreviation 16-bit access Access R R R R R R R R R R R R R R EPSR16 R ADER0 ADER1 ADER2 ADER3 ADER4 R/W R/W R/W R/W R/W PRRR0 PRRR1 PRRR2 PRRR3 R/W R/W R/W R/W I/O Port P16 - External Pin State Register Reserved ADC analog input enable register 0 ADC analog input enable register 1 ADC analog input enable register 2 ADC analog input enable register 3 ADC analog input enable register 4 Reserved Peripheral Resource Relocation Register 0 Peripheral Resource Relocation Register 1 Peripheral Resource Relocation Register 2 Peripheral Resource Relocation Register 3 42 PR EL IM IN AR Y FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (20 of 34) Address 0004DAH 0004DBH 0004DCH 0004DDH 0004DEH 0004DFH 0004E0H 0004E1H 0004E2H 0004E3H 0004E4H 0004E5H 0004E6H 0004E7H 0004E8H 0004E9H 0004EAH 0004EBH 0004ECH 0004EDH 0004EEH 0004EFH 0004F0H 0004F1H 0004F2H0004F9H 0004FAH 0004FBH00051FH 000520H 000521H Register Peripheral Resource Relocation Register 4 Peripheral Resource Relocation Register 5 Peripheral Resource Relocation Register 6 Peripheral Resource Relocation Register 7 Peripheral Resource Relocation Register 8 Peripheral Resource Relocation Register 9 RTC - Sub Second Register L RTC - Sub Second Register M RTC - Sub-Second Register H RTC - Second Register RTC - Minutes RTC - Hour Abbreviation 8-bit access PRRR4 PRRR5 PRRR6 PRRR7 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W WTBR0 R/W R/W R/W R/W R/W R/W R/W R/W WTCR R/W R/W R/W CUTDL CUTDH CUTR2L CUTR2H CUTR1L CUTR1H CUTR1 CUTR2 CUTD R/W R/W R R R R TMISR R/W SMR4 SCR4 R/W R/W IN RTC - Timer Control Extended Register RTC - Clock select register RTC - Timer Control Register Low IM RTC - Timer Control Register High CAL - Calibration unit Control register Reserved CAL - Duration Timer Data Register Low CAL - Duration Timer Data Register High CAL - Calibration Timer Register 2 Low CAL - Calibration Timer Register 2 High CAL - Calibration Timer Register 1 Low CAL - Calibration Timer Register 1 High Reserved RLT - Timer input select (for Cascading) Reserved USART4 - Serial Mode Register USART4 - Serial Control Register FME-MB96370 rev 5 PR EL AR WTBR1 WTSR WTMR WTHR WTCER WTCRL WTCRH CUCR Y PRRR8 PRRR9 WTBRL0 WTBRH0 WTCKSR 43 MB96370 Series I/O map MB96(F)37x (21 of 34) Address 000522H 000522H 000523H 000524H 000525H 000526H 000527H 000528H 000529H 00052AH 00052BH 00052CH 00052CH 00052DH 00052EH 00052FH 000530H 000531H 000532H 000533H00055FH 000560H 000561H 000562H 000563H 000564H 000565H 000566H 000567H 000568H Register USART4 - TX Register USART4 - RX Register USART4 - Serial Status USART4 - Control/Com. Register (internal) USART4 - Ext. Status Register USART4 - Baud Rate Generator Register Low USART4 - Baud Rate Generator Register High USART4 - Extended Serial Interrupt Register Reserved USART5 - Serial Mode Register USART5 - Serial Control Register USART5 - RX Register USART5 - TX Register USART5 - Serial Status Abbreviation 8-bit access TDR4 RDR4 SSR4 ECCR4 ESCR4 BGRL4 Abbreviation 16-bit access Access W R R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R/W R/W BGR5 R/W R/W R/W ACSR0 AECSR0 ACSR1 AECSR1 PTMR6 R/W R/W R/W R/W R R PCSR6 W W PDUT6 W USART5 - Control/Com. Register USART5 - Ext. Status Register IM USART5 - Baud Rate Generator Register Low USART5 - Baud Rate Generator Register High USART5 - Extended Serial Interrupt Register Reserved EL ALARM0 - Extended Control Status Register ALARM1 - Control Status Register ALARM1 - Extended Control Status Register PPG6 - Timer register PPG6 - Timer register PPG6 - Period setting register PPG6 - Period setting register PPG6 - Duty cycle register 44 PR ALARM0 - Control Status Register IN AR BGRH4 ESIR4 SMR5 SCR5 TDR5 RDR5 SSR5 ECCR5 ESCR5 BGRL5 BGRH5 ESIR5 Y BGR4 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (22 of 34) Address 000569H 00056AH 00056BH 00056CH 00056DH 00056EH 00056FH 000570H 000571H 000572H 000573H 000574H 000575H 000576H 000577H 000578H 000579H 00057AH 00057BH 00057CH 00057DH 00057EH 00057FH 000580H 000581H 000582H 000583H 000584H 000585H 000586H Register PPG6 - Duty cycle register PPG6 - Control status register Low PPG6 - Control status register High PPG7 - Timer register PPG7 - Timer register PPG7 - Period setting register PPG7 - Period setting register PPG7 - Duty cycle register PPG7 - Duty cycle register PPG7 - Control status register Low PPG7 - Control status register High PCNL6 PCNH6 PTMR7 PCN6 Abbreviation 8-bit access Abbreviation 16-bit access Access W R/W R/W R R PCSR7 W W PDUT7 W W PCN7 R/W R/W GCN12 R/W R/W GCN22 R/W R/W PTMR8 R R PCSR8 W W PDUT8 W W PCNL8 PCNH8 PTMR9 PCN8 R/W R/W R R PCSR9 W W PDUT9 W W PCNL9 PCN9 R/W PPG11-PPG8 - General Control register 1 Low IN PPG11-PPG8 - General Control register 1 High PPG11-PPG8 - General Control register 2 High PPG8 - Timer register PPG8 - Timer register IM PPG11-PPG8 - General Control register 2 Low PPG8 - Period setting register PPG8 - Period setting register PPG8 - Duty cycle register PPG8 - Duty cycle register PPG8 - Control status register Low PPG8 - Control status register High PPG9 - Timer register PPG9 - Timer register PPG9 - Period setting register PPG9 - Period setting register PPG9 - Duty cycle register PPG9 - Duty cycle register PPG9 - Control status register Low FME-MB96370 rev 5 PR EL AR PCNL7 PCNH7 GCN1L2 GCN1H2 GCN2L2 GCN2H2 Y 45 MB96370 Series I/O map MB96(F)37x (23 of 34) Address 000587H 000588H 000589H 00058AH 00058BH 00058CH 00058DH 00058EH 00058FH 000590H 000591H 000592H 000593H 000594H 000595H 000596H 000597H 000598H0005DFH 0005E0H 0005E1H 0005E2H 0005E3H 0005E4H 0005E5H 0005E6H 0005E7H 0005E8H0005E9H 0005EAH Register PPG9 - Control status register High PPG10 - Timer register PPG10 - Timer register PPG10 - Period setting register PPG10 - Period setting register PPG10 - Duty cycle register PPG10 - Duty cycle register PPG10 - Control status register Low PPG10 - Control status register High PPG11 - Timer register PPG11 - Timer register PPG11 - Period setting register PPG11 - Period setting register PPG11 - Duty cycle register PPG11 - Duty cycle register PCSR10 Abbreviation 8-bit access PCNH9 PTMR10 Abbreviation 16-bit access Access R/W R R W W W W PCN10 R/W R/W PTMR11 R R PCSR11 W W PDUT11 W W PCNL11 PCNH11 PCN11 R/W R/W PWC0 PWEC0 PWC10 R/W R/W R/W R/W PWC20 R/W R/W PWS10 PWS20 R/W R/W PWC1 R/W PPG11 - Control status register Low PPG11 - Control status register High Reserved SMC0 - PWM control register SMC0 - PWM compare register PWM 1 SMC0 - PWM compare register PWM 1 SMC0 - PWM compare register PWM 2 SMC0 - PWM compare register PWM 2 SMC0 - PWM Select register SMC0 - PWM Select register Reserved SMC1 - PWM control register 46 PR SMC0 - Extended control register (Output enable) EL IM IN AR PCNL10 PCNH10 Y PDUT10 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (24 of 34) Address 0005EBH 0005ECH 0005EDH 0005EEH 0005EFH 0005F0H 0005F1H 0005F2H0005F3H 0005F4H 0005F5H 0005F6H 0005F7H 0005F8H 0005F9H 0005FAH 0005FBH 0005FCH0005FDH 0005FEH 0005FFH 000600H 000601H 000602H 000603H 000604H 000605H 000606H000607H Register SMC1 - Extended control register (Output enable) SMC1 - PWM compare register PWM 1 SMC1 - PWM compare register PWM 1 SMC1 - PWM compare register PWM 2 SMC1 - PWM compare register PWM 2 SMC1 - PWM Select register SMC1 - PWM Select register Reserved SMC2 - PWM control register Abbreviation 8-bit access PWEC1 PWC11 Abbreviation 16-bit access Access R/W R/W R/W Y AR PWS11 PWS21 PWC2 PWEC2 PWS12 PWS22 PWC3 PWEC3 PWS13 PWS23 PWC21 R/W R/W R/W R/W R/W R/W SMC2 - Extended control register (Output enable) SMC2 - PWM compare register PWM 1 SMC2 - PWM compare register PWM 1 SMC2 - PWM compare register PWM 2 SMC2 - PWM compare register PWM 2 SMC2 - PWM Select register SMC2 - PWM Select register Reserved IN PWC12 R/W R/W IM PWC22 R/W R/W R/W R/W R/W R/W SMC3 - PWM control register SMC3 - PWM compare register PWM 1 SMC3 - PWM compare register PWM 1 SMC3 - PWM compare register PWM 2 SMC3 - PWM compare register PWM 2 SMC3 - PWM Select register SMC3 - PWM Select register Reserved PR SMC3 - Extended control register (Output enable) EL PWC13 R/W R/W PWC23 R/W R/W R/W R/W - FME-MB96370 rev 5 47 MB96370 Series I/O map MB96(F)37x (25 of 34) Address 000608H 000609H 00060AH 00060BH 00060CH 00060DH 00060EH 00060FH 000610H000611H 000612H 000613H 000614H 000615H 000616H 000617H 000618H 000619H 00061AH00061BH 00061CH 00061DH 00061EH 00061FH 000620H 000621H 000622H 000623H 000624H Register SMC4 - PWM control register SMC4 - Extended control register (Output enable) SMC4 - PWM compare register PWM 1 SMC4 - PWM compare register PWM 1 SMC4 - PWM compare register PWM 2 SMC4 - PWM compare register PWM 2 SMC4 - PWM Select register SMC4 - PWM Select register Reserved SMC5 - PWM control register Abbreviation 8-bit access PWC4 PWEC4 PWC14 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PWC15 R/W R/W PWC25 R/W R/W PWS15 PWS25 R/W R/W LCDER0 LCDER1 LCDER2 LCDER3 LCDER4 LCDER5 LCDER6 LCDER7 LCDER8 R/W R/W R/W R/W R/W R/W R/W R/W R/W SMC5 - Extended control register (Output enable) SMC5 - PWM compare register PWM 1 SMC5 - PWM compare register PWM 1 SMC5 - PWM compare register PWM 2 SMC5 - PWM compare register PWM 2 SMC5 - PWM Select register SMC5 - PWM Select register Reserved LCD - Output Enable Register 1 (Seg 15-8) LCD - Output Enable Register 2 (Seg 23-16) LCD - Output Enable Register 3 (Seg 31-24) LCD - Output Enable Register 4 (Seg 39-32) LCD - Output Enable Register 5 (Seg 47-40) LCD - Output Enable Register 6 (Seg 55-48) LCD - Output Enable Register 7 (Seg 63-56) LCD - Output Enable Register 8 (Seg 71-64) 48 PR LCD - Output Enable Register 0 (Seg 7-0) EL IM IN AR PWS14 PWS24 PWC5 PWEC5 Y PWC24 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (26 of 34) Address 000625H 000626H 000627H 000628H 000629H 00062AH 00062BH 00062CH 00062DH 00062EH 00062FH 000630H 000631H 000632H 000633H 000634H 000635H 000636H 000637H 000638H 000639H 00063AH 00063BH 00063CH 00063DH 00063EH 00063FH 000640H 000641H 000642H Reserved LCD - Output Enable Register V (Vx) LCD - Extended Control Register LCD - Common pin switching register LCD - Control Register LCD - Data register for Segment 1-0 LCD - Data register for Segment 3-2 LCD - Data register for Segment 5-4 LCD - Data register for Segment 7-6 LCD - Data register for Segment 9-8 LCD - Data register for Segment 11-10 LCD - Data register for Segment 13-12 LCD - Data register for Segment 15-14 LCD - Data register for Segment 17-16 LCD - Data register for Segment 19-18 LCD - Data register for Segment 21-20 LCD - Data register for Segment 23-22 LCD - Data register for Segment 25-24 LCD - Data register for Segment 27-26 LCD - Data register for Segment 29-28 LCD - Data register for Segment 31-30 LCD - Data register for Segment 33-32 LCD - Data register for Segment 35-34 LCD - Data register for Segment 37-36 LCD - Data register for Segment 39-38 LCD - Data register for Segment 41-40 LCD - Data register for Segment 43-42 LCD - Data register for Segment 45-44 LCD - Data register for Segment 47-46 LCD - Data register for Segment 49-48 LCDVER LECR LCDCMR Register Abbreviation 8-bit access Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IN IM EL PR FME-MB96370 rev 5 AR VRAM1 VRAM2 VRAM3 VRAM4 VRAM5 VRAM6 VRAM7 VRAM8 VRAM9 VRAM10 VRAM11 VRAM12 VRAM13 VRAM14 VRAM15 VRAM16 VRAM17 VRAM18 VRAM19 VRAM20 VRAM21 VRAM22 VRAM23 VRAM24 Y LCR VRAM0 49 MB96370 Series I/O map MB96(F)37x (27 of 34) Address 000643H 000644H 000645H 000646H 000647H 000648H 000649H 00064AH 00064BH 00064CH 00064DH 00064EH00065FH 000660H 000661H 000662H 000663H 000664H0006DFH 0006E0H 0006E1H 0006E2H 0006E3H 0006E4H 0006E5H 0006E6H 0006E7H 0006E8H 0006E9H 0006EAH 0006EBH Register LCD - Data register for Segment 51-50 LCD - Data register for Segment 53-52 LCD - Data register for Segment 55-54 LCD - Data register for Segment 57-56 LCD - Data register for Segment 59-58 LCD - Data register for Segment 61-60 LCD - Data register for Segment 63-62 LCD - Data register for Segment 65-64 LCD - Data register for Segment 67-66 LCD - Data register for Segment 69-68 LCD - Data register for Segment 71-70 Reserved Abbreviation 8-bit access VRAM25 VRAM26 VRAM27 VRAM28 VRAM29 VRAM30 VRAM31 VRAM32 VRAM33 VRAM34 VRAM35 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W EACL0 EACH0 EACL1 EACH1 EACL2 EACH2 EACL3 EACH3 EACL4 EACH4 EACL5 EACH5 EAC5 EAC4 EAC3 EAC2 EAC1 EAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Peripheral Resource Relocation Register 10 Peripheral Resource Relocation Register 11 Peripheral Resource Relocation Register 12 Peripheral Resource Relocation Register 13 Reserved IM External Bus - Area configuration register 0 Low External Bus - Area configuration register 0 High External Bus - Area configuration register 1 High External Bus - Area configuration register 2 Low External Bus - Area configuration register 2 High External Bus - Area configuration register 3 Low External Bus - Area configuration register 3 High External Bus - Area configuration register 4 Low External Bus - Area configuration register 4 High External Bus - Area configuration register 5 Low External Bus - Area configuration register 5 High 50 PR External Bus - Area configuration register 1 Low EL IN AR PRRR10 PRRR11 PRRR12 PRRR13 Y FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (28 of 34) Address 0006ECH 0006EDH 0006EEH 0006EFH 0006F0H 0006F1H 0006F2H 0006F3H 0006F4H 0006F5H 0006F6H0006FFH 000700H 000701H 000702H 000703H 000704H 000705H 000706H 000707H 000708H 000709H 00070AH 00070BH 00070CH 00070DH 00070EH00070FH 000710H 000711H 000712H Register External Bus - Area select register 2 External Bus - Area select register 3 External Bus - Area select register 4 External Bus - Area select register 5 External Bus - Mode register External Bus - Clock and Function register External Bus - Address output enable register 0 External Bus - Address output enable register 1 External Bus - Address output enable register 2 External Bus - Control signal register Reserved CAN0 - Control register Low Abbreviation 8-bit access EAS2 EAS3 EAS4 EAS5 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CTRLRL0 CTRLRH0 STATRL0 STATRH0 ERRCNTL0 ERRCNTH0 BTRL0 BTRH0 INTRL0 INTRH0 TESTRL0 TESTRH0 BRPERL0 BRPERH0 BRPER0 TESTR0 INTR0 BTR0 ERRCNT0 STATR0 CTRLR0 R/W R R/W R R R R/W R/W R R R/W R R/W R IF1CREQL0 IF1CREQH0 IF1CMSKL0 IF1CMSK0 IF1CREQ0 R/W R/W R/W CAN0 - Control register High (reserved) CAN0 - Status register Low CAN0 - Status register High (reserved) CAN0 - Error Counter Low (Transmit) CAN0 - Bit Timing Register Low CAN0 - Bit Timing Register High CAN0 - Interrupt Register Low CAN0 - Test Register Low CAN0 - Test Register High (reserved) CAN0 - BRP Extension register Low CAN0 - BRP Extension register High (reserved) Reserved CAN0 - IF1 Command request register Low CAN0 - IF1 Command request register High CAN0 - IF1 Command Mask register Low FME-MB96370 rev 5 PR CAN0 - Interrupt Register High EL CAN0 - Error Counter High (Receive) IM IN AR EBAE0 EBAE1 EBAE2 EBCS Y EBM EBCF 51 MB96370 Series I/O map MB96(F)37x (29 of 34) Address 000713H 000714H 000715H 000716H 000717H 000718H 000719H 00071AH 00071BH 00071CH 00071DH 00071EH 00071FH 000720H 000721H 000722H 000723H 000724H 000725H 000726H00073FH 000740H 000741H 000742H 000743H 000744H 000745H 000746H 000747H Register CAN0 - IF1 Command Mask register High (reserved) CAN0 - IF1 Mask 1 Register Low CAN0 - IF1 Mask 1 Register High CAN0 - IF1 Mask 2 Register Low CAN0 - IF1 Mask 2 Register High CAN0 - IF1 Arbitration 1 Register Low CAN0 - IF1 Arbitration 1 Register High CAN0 - IF1 Arbitration 2 Register Low CAN0 - IF1 Arbitration 2 Register High CAN0 - IF1 Message Control Register Low CAN0 - IF1 Message Control Register High CAN0 - IF1 Data A1 Low CAN0 - IF1 Data A1 High CAN0 - IF1 Data A2 Low CAN0 - IF1 Data A2 High CAN0 - IF1 Data B1 Low CAN0 - IF1 Data B1 High CAN0 - IF1 Data B2 Low Abbreviation 8-bit access IF1CMSKH0 IF1MSK1L0 IF1MSK1H0 IF1MSK2L0 IF1MSK10 Abbreviation 16-bit access Access R R/W R/W IF1MSK20 R/W R/W R/W R/W IF1ARB20 R/W R/W IF1MCTR0 R/W R/W IF1DTA10 R/W R/W IF1DTA20 R/W R/W IF1DTB10 R/W R/W IF1DTB20 R/W R/W IF2CREQL0 IF2CREQH0 IF2CMSKL0 IF2CMSKH0 IF2MSK1L0 IF2MSK1H0 IF2MSK2L0 IF2MSK2H0 IF2MSK20 IF2MSK10 IF2CMSK0 IF2CREQ0 R/W R/W R/W R R/W R/W R/W R/W IF1MSK2H0 IF1ARB1L0 AR IF1ARB1H0 IF1ARB2L0 IF1ARB2H0 IF1MCTRL0 IF1MCTRH0 IF1DTA1L0 IF1DTA1H0 IF1DTA2L0 IF1DTA2H0 IF1DTB1L0 IF1DTB1H0 IF1DTB2L0 IF1DTB2H0 CAN0 - IF1 Data B2 High Reserved CAN0 - IF2 Command request register Low CAN0 - IF2 Command request register High CAN0 - IF2 Command Mask register Low CAN0 - IF2 Command Mask register High (reserved) CAN0 - IF2 Mask 1 Register Low CAN0 - IF2 Mask 1 Register High CAN0 - IF2 Mask 2 Register Low CAN0 - IF2 Mask 2 Register High 52 PR EL IM IN Y IF1ARB10 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (30 of 34) Address 000748H 000749H 00074AH 00074BH 00074CH 00074DH 00074EH 00074FH 000750H 000751H 000752H 000753H 000754H 000755H 000756H00077FH 000780H 000781H 000782H 000783H 000784H00078FH 000790H 000791H 000792H 000793H 000794H00079FH 0007A0H 0007A1H 0007A2H Register CAN0 - IF2 Arbitration 1 Register Low CAN0 - IF2 Arbitration 1 Register High CAN0 - IF2 Arbitration 2 Register Low CAN0 - IF2 Arbitration 2 Register High CAN0 - IF2 Message Control Register Low CAN0 - IF2 Message Control Register High CAN0 - IF2 Data A1 Low CAN0 - IF2 Data A1 High CAN0 - IF2 Data A2 Low CAN0 - IF2 Data A2 High CAN0 - IF2 Data B1 Low CAN0 - IF2 Data B1 High CAN0 - IF2 Data B2 Low CAN0 - IF2 Data B2 High Reserved Abbreviation 8-bit access IF2ARB1L0 IF2ARB1H0 IF2ARB2L0 IF2ARB2H0 IF2MCTRL0 IF2ARB20 Abbreviation 16-bit access IF2ARB10 Access R/W R/W R/W R/W IF2MCTR0 R/W R/W IF2DTA10 R/W R/W IF2DTA20 R/W R/W IF2DTB10 R/W R/W IF2DTB20 R/W R/W TREQR1L0 TREQR1H0 TREQR2L0 TREQR2H0 TREQR20 TREQR10 R R R R NEWDT1L0 NEWDT1H0 NEWDT2L0 NEWDT2H0 NEWDT20 NEWDT10 R R R R INTPND1L0 INTPND1H0 INTPND2L0 INTPND20 INTPND10 R R R IF2MCTRH0 IF2DTA1L0 IN CAN0 - Transmission Request 1 Register Low CAN0 - Transmission Request 2 Register Low CAN0 - Transmission Request 2 Register High Reserved CAN0 - New Data 1 Register Low CAN0 - New Data 1 Register High CAN0 - New Data 2 Register Low CAN0 - New Data 2 Register High Reserved CAN0 - Interrupt Pending 1 Register Low CAN0 - Interrupt Pending 1 Register High CAN0 - Interrupt Pending 2 Register Low FME-MB96370 rev 5 PR EL CAN0 - Transmission Request 1 Register High IM AR IF2DTA1H0 IF2DTA2L0 IF2DTA2H0 IF2DTB1L0 IF2DTB1H0 IF2DTB2L0 IF2DTB2H0 Y 53 MB96370 Series I/O map MB96(F)37x (31 of 34) Address 0007A3H 0007A4H0007AFH 0007B0H 0007B1H 0007B2H 0007B3H 0007B4H0007CDH 0007CEH 0007CFH 0007D0H 0007D1H 0007D2H 0007D3H 0007D4H 0007D5H 0007D6H 0007D7H 0007D8H 0007D9H 0007DAH 0007DBH 0007DCH0007FFH 000800H 000801H 000802H 000803H 000804H 000805H Register CAN0 - Interrupt Pending 2 Register High Reserved CAN0 - Message Valid 1 Register Low CAN0 - Message Valid 1 Register High CAN0 - Message Valid 2 Register Low CAN0 - Message Valid 2 Register High Reserved CAN0 - Output enable register Reserved SG0 - Sound Generator Control Register Low MSGVAL1L0 MSGVAL1H0 MSGVAL2L0 MSGVAL10 Abbreviation 8-bit access INTPND2H0 Abbreviation 16-bit access Access R R R R R R/W SGCR0 R/W R/W R/W R/W R/W R/W SGCR1 R/W R/W R/W R/W R/W R/W CTRLRL1 CTRLRH1 STATRL1 STATRH1 ERRCNTL1 ERRCNTH1 ERRCNT1 STATR1 CTRLR1 R/W R R/W R R R SG0 - Sound Generator Control Register High SG0 - Sound Generator Frequency Register SG0 - Sound Generator Amplitude Register IM SG0 - Sound Generator Decrement Register SG0 - Sound Generator Tone Register SG1 - Sound Generator Control Register High SG1 - Sound Generator Frequency Register SG1 - Sound Generator Amplitude Register EL SG1 - Sound Generator Control Register Low SG1 - Sound Generator Tone Register Reserved PR SG1 - Sound Generator Decrement Register CAN1 - Control register Low CAN1 - Control register High (reserved) CAN1 - Status register Low CAN1 - Status register High (reserved) CAN1 - Error Counter Low (Transmit) CAN1 - Error Counter High (Receive) 54 IN AR MSGVAL2H0 COER0 SGCRL0 SGCRH0 SGFR0 SGAR0 SGDR0 SGTR0 SGCRL1 SGCRH1 SGFR1 SGAR1 SGDR1 SGTR1 Y MSGVAL20 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (32 of 34) Address 000806H 000807H 000808H 000809H 00080AH 00080BH 00080CH 00080DH 00080EH00080FH 000810H 000811H 000812H 000813H 000814H 000815H 000816H 000817H 000818H 000819H 00081AH 00081BH 00081CH 00081DH 00081EH 00081FH 000820H 000821H 000822H 000823H Register CAN1 - Bit Timing Register Low CAN1 - Bit Timing Register High CAN1 - Interrupt Register Low CAN1 - Interrupt Register High CAN1 - Test Register Low CAN1 - Test Register High (reserved) CAN1 - BRP Extension register Low Abbreviation 8-bit access BTRL1 BTRH1 INTRL1 INTRH1 TESTRL1 INTR1 Abbreviation 16-bit access BTR1 Access R/W R/W R R TESTR1 R/W R BRPER1 R/W R IF1CREQ1 R/W R/W IF1CMSK1 R/W R IF1MSK11 R/W R/W IF1MSK21 R/W R/W IF1ARB11 R/W R/W IF1ARB21 R/W R/W IF1MCTR1 R/W R/W IF1DTA11 R/W R/W IF1DTA21 R/W R/W IF1DTB11 R/W R/W TESTRH1 CAN1 - BRP Extension register High (reserved) Reserved CAN1 - IF1 Command request register Low CAN1 - IF1 Command request register High CAN1 - IF1 Command Mask register Low IN CAN1 - IF1 Mask 1 Register Low IM CAN1 - IF1 Command Mask register High (reserved) CAN1 - IF1 Mask 1 Register High CAN1 - IF1 Mask 2 Register Low CAN1 - IF1 Mask 2 Register High EL CAN1 - IF1 Arbitration 1 Register Low CAN1 - IF1 Arbitration 1 Register High CAN1 - IF1 Arbitration 2 Register High CAN1 - IF1 Message Control Register Low CAN1 - IF1 Message Control Register High CAN1 - IF1 Data A1 Low CAN1 - IF1 Data A1 High CAN1 - IF1 Data A2 Low CAN1 - IF1 Data A2 High CAN1 - IF1 Data B1 Low CAN1 - IF1 Data B1 High PR CAN1 - IF1 Arbitration 2 Register Low FME-MB96370 rev 5 AR BRPERL1 BRPERH1 IF1CREQL1 IF1CREQH1 IF1CMSKL1 IF1CMSKH1 IF1MSK1L1 IF1MSK1H1 IF1MSK2L1 IF1MSK2H1 IF1ARB1L1 IF1ARB1H1 IF1ARB2L1 IF1ARB2H1 IF1MCTRL1 IF1MCTRH1 IF1DTA1L1 IF1DTA1H1 IF1DTA2L1 IF1DTA2H1 IF1DTB1L1 IF1DTB1H1 Y 55 MB96370 Series I/O map MB96(F)37x (33 of 34) Address 000824H 000825H 000826H00083FH 000840H 000841H 000842H 000843H 000844H 000845H 000846H 000847H 000848H 000849H 00084AH 00084BH 00084CH 00084DH 00084EH 00084FH 000850H 000851H 000852H 000853H 000854H 000855H 000856H00087FH 000880H 000881H Register CAN1 - IF1 Data B2 Low CAN1 - IF1 Data B2 High Reserved CAN1 - IF2 Command request register Low CAN1 - IF2 Command request register High CAN1 - IF2 Command Mask register Low CAN1 - IF2 Command Mask register High (reserved) CAN1 - IF2 Mask 1 Register Low CAN1 - IF2 Mask 1 Register High CAN1 - IF2 Mask 2 Register Low CAN1 - IF2 Mask 2 Register High CAN1 - IF2 Arbitration 1 Register Low CAN1 - IF2 Arbitration 1 Register High CAN1 - IF2 Arbitration 2 Register Low IF2CREQL1 Abbreviation 8-bit access IF1DTB2L1 IF1DTB2H1 Abbreviation 16-bit access IF1DTB21 Access R/W R/W - Y IF2CREQ1 R/W R/W R/W R IF2CREQH1 IF2CMSKL1 AR IF2CMSKH1 IF2MSK1L1 IF2MSK1H1 IF2MSK2L1 IF2MSK2H1 IF2ARB1L1 IF2ARB1H1 IF2ARB2L1 IF2ARB2H1 IF2MCTRL1 IF2MCTRH1 IF2DTA1L1 IF2DTA1H1 IF2DTA2L1 IF2DTA2H1 IF2DTB1L1 IF2DTB1H1 IF2DTB2L1 IF2DTB2H1 TREQR1L1 TREQR1H1 IF2CMSK1 IF2MSK11 R/W R/W IN IF2MSK21 R/W R/W IF2ARB11 R/W R/W IM IF2ARB21 R/W R/W CAN1 - IF2 Arbitration 2 Register High CAN1 - IF2 Message Control Register High CAN1 - IF2 Data A1 Low EL CAN1 - IF2 Message Control Register Low IF2MCTR1 R/W R/W IF2DTA11 R/W R/W CAN1 - IF2 Data A1 High CAN1 - IF2 Data A2 Low CAN1 - IF2 Data A2 High CAN1 - IF2 Data B1 Low PR IF2DTA21 R/W R/W IF2DTB11 R/W R/W CAN1 - IF2 Data B1 High CAN1 - IF2 Data B2 Low IF2DTB21 R/W R/W - CAN1 - IF2 Data B2 High Reserved CAN1 - Transmission Request 1 Register Low CAN1 - Transmission Request 1 Register High TREQR11 R R 56 FME-MB96370 rev 5 MB96370 Series I/O map MB96(F)37x (34 of 34) Address 000882H 000883H 000884H00088FH 000890H 000891H 000892H 000893H 000894H00089FH 0008A0H 0008A1H 0008A2H 0008A3H 0008A4H0008AFH 0008B0H 0008B1H 0008B2H 0008B3H 0008B4H0008CDH 0008CEH 0008CFH000BFFH Register CAN1 - Transmission Request 2 Register Low CAN1 - Transmission Request 2 Register High Reserved CAN1 - New Data 1 Register Low CAN1 - New Data 1 Register High CAN1 - New Data 2 Register Low CAN1 - New Data 2 Register High Reserved CAN1 - Interrupt Pending 1 Register Low CAN1 - Interrupt Pending 1 Register High CAN1 - Interrupt Pending 2 Register Low NEWDT1L1 Abbreviation 8-bit access TREQR2L1 TREQR2H1 Abbreviation 16-bit access TREQR21 Access R R - Y COER1 NEWDT11 R R NEWDT1H1 AR NEWDT2L1 NEWDT21 R R - NEWDT2H1 INTPND1L1 INTPND11 R R IN INTPND1H1 INTPND2L1 INTPND2H1 INTPND21 R R - CAN1 - Interrupt Pending 2 Register High Reserved CAN1 - Message Valid 1 Register Low IM MSGVAL1L1 MSGVAL1H1 MSGVAL2L1 MSGVAL2H1 MSGVAL11 R R CAN1 - Message Valid 1 Register High CAN1 - Message Valid 2 Register Low CAN1 - Message Valid 2 Register High Reserved EL MSGVAL21 R R R/W - Reserved Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. FME-MB96370 rev 5 PR CAN1 - Output enable register 57 MB96370 Series ■ INTERRUPT VECTOR TABLE Interrupt vector table MB96(F)37x (1 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380 37CH CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER RESERVED EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7 CAN0 CAN1 No No No No No No No No No No No No No No No No - Description IM 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 No 16 Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes EL PR PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 58 IN 12 13 AR Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 CAN Controller 0 CAN Controller 1 Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5 FME-MB96370 rev 5 Y MB96370 Series Interrupt vector table MB96(F)37x (2 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 308H 304H 300H 2FCH 2F8H 2F4H 2F0H PPG6 PPG7 RLT0 RLT1 RLT2 RLT3 PPGRLT ICU0 ICU1 ICU2 ICU3 ICU4 ICU5 ICU6 ICU7 OCU0 OCU1 OCU2 OCU3 FRT0 FRT1 RTC0 CAL0 SG0 SG1 IIC0 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Description Programmable Pulse Generator 6 Programmable Pulse Generator 7 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1 Input Capture Unit 2 Input Capture Unit 3 Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7 Output Compare Unit 0 Output Compare Unit 1 Output Compare Unit 2 Output Compare Unit 3 Free Running Timer 0 Free Running Timer 1 Real Timer Clock Clock Calibration Unit Sound Generator 0 Sound Generator 1 I2C interface 0 A/D Converter Alarm Comparator 0 Alarm Comparator 1 LIN USART 0 RX LIN USART 0 TX LIN USART 1 RX LIN USART 1 TX LIN USART 2 RX LIN USART 2 TX PR ADC0 ALARM0 ALARM1 LINR0 LINT0 LINR1 LINT1 LINR2 LINT2 30CH FME-MB96370 rev 5 EL IM Yes Yes No No Yes Yes Yes Yes Yes Yes IN AR Y 59 MB96370 Series Interrupt vector table MB96(F)37x (3 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 2B8H 2B4H LINR4 LINT4 LINR5 LINT5 FLASH_A FLASH_B PPG8 PPG9 PPG10 PPG11 OCU4 OCU5 IIC1 LINR3 LINT3 Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Description LIN USART 4 RX LIN USART 4 TX LIN USART 5 RX LIN USART 5 TX Flash memory B (only Flash devices with Flash B) Flash memory A (only Flash devices) 60 PR EL FME-MB96370 rev 5 IM IN AR I2C Interface 1 Programmable Pulse Generator 8 Programmable Pulse Generator 9 Programmable Pulse Generator 10 Programmable Pulse Generator 11 Output Compare Unit 4 Output Compare Unit 5 LIN USART 3 RX LIN USART 3 TX Y MB96370 Series ■ HANDLING DEVICES Special care is required for the following when handling the device: • • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Unused sub clock signal Notes on PLL clock mode operation Power supply pins (VCC/VSS) Crystal oscillator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on energization Stabilization of power supply voltage SMC power supply pins Serial communication 1. Latch-up prevention Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. External clock usage 1. Single phase external clock • When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open. PR The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: EL Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 kΩ. IM IN CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC pins and VSS pins. • The AVCC power supply is applied before the VCC voltage. FME-MB96370 rev 5 AR X0 X1 Y 61 MB96370 Series 2. Opposite phase external clock • When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 X1 4. Unused sub clock signal 5. Notes on PLL clock mode operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between VCC and VSS as close as possible to VCC and VSS pins. 7. Crystal oscillator and ceramic resonator circuit It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 8. Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. Pin handling when not using the A/D converter It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50µs from 0.2 V to 2.7 V. 62 PR EL Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. IM VCC and VSS must be connected to the device from the power supply with lowest possible impedance. IN 6. Power supply pins (VCC/VSS) AR If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. Y FME-MB96370 rev 5 MB96370 Series 11. Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching. 12. SMC power supply pins All DVSS pins must be set to the same level as the VSS pins. The DVCC power supply level can be set independently of the VCC power supply level. However note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to always power VCC before DVCC. There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. FME-MB96370 rev 5 PR EL IM IN AR 13. Serial communication Y 63 MB96370 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage AD Converter voltage references SMC Power supply LCD power supply voltage Input voltage Output voltage Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current Symbol VCC AVCC AVRH, AVRL DVCC VI VO ICLAMP Σ|ICLAMP| IOL1 IOLSMC “L” level average output current IOLAV1 Rating Min Max VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 -4.0 +4.0 40 15 40 5 30 100 330 50 250 -15 -40 -5 -30 -100 -330 -50 -250 Unit V V V V V V V VCC = AVCC *1 AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS See *7 V0 to V3 must not exceed VCC *2 Remarks V0 to V3 VSS - 0.3 VSS + 6.0 IN IM IOLAVSMC “L” level maximum overall output current “L” level average overall output current ”H” level maximum output current ΣIOL1 EL ΣIOLSMC ΣIOLAV1 IOH1 ΣIOLAVSMC IOHSMC IOHAV1 IOHAVSMC ΣIOH1 ΣIOHSMC ΣIOHAV1 ΣIOHASMC PR ”H” level average output current ”H” level maximum overall output current ”H” level average overall output current 64 AR mA mA mA mA Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs mA High current outputs mA Normal outputs mA High current outputs Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs with driving strength set to 5mA mA High current outputs with driving strength set to 30mA mA Normal outputs mA High current outputs mA Normal outputs mA High current outputs Y VI ≤ (D)VCC + 0.3V VO ≤ (D)VCC + 0.3V *2 Applicable to general purpose I/O pins *3 Applicable to general purpose I/O pins *3 FME-MB96370 rev 5 MB96370 Series Rating Min Permitted Power dissipation (Flash devices) *4 PD 0 Operating ambient temperature TA 430*5 780*5 +70 mW mW Max TBD*5 350*5 700*5 960*5 Parameter Permitted Power dissipation(Mask ROM devices) *4 Symbol PD Unit mW mW TA=105oC mW TA=85oC mW TA=70oC Remarks AR +105 +125 +150 o -40 -40 Storage temperature TSTG -55 *1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. *2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of high current ports depend on DVCC. Input/output voltages of standard ports depend on VCC. *3: • Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality. • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). • No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins). FME-MB96370 rev 5 PR EL IM IN Y C *6 o TA=125oC, no Flash program/ erase *6 TA=105oC, no Flash program/ erase *6 MB96V300B C 65 MB96370 Series • Sample recommended circuits: Protective Diode VCC Limiting resistance +B input (0V to 16V) P-ch N-ch R *5: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *6: Please contact Fujitsu for reliability limitations when using under these conditions. *7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 66 PR EL IM IN *4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. AR Y FME-MB96370 rev 5 MB96370 Series 2. Recommended Operating Conditions Value Min 3.0 3.5 Typ 4.7 Max 5.5 15 Parameter Power supply voltage Smoothing capacitor at C pin Symbol VCC, DVCC CS Unit V µF Remarks FME-MB96370 rev 5 PR EL IM IN AR WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Y Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics 67 MB96370 Series 3. DC characteristics (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Input H voltage Symbol Pin Condition CMOS Hysteresis 0.8/0.2 input selected CMOS Hysteresis Port inputs 0.7/0.3 input selected Pnn_m AUTOMOTIVE Hysteresis input selected TTL input selected VIHX0F VIHX0S VIHR VIHM Input L voltage X0 X0,X1, X0A,X1A RSTX MD2-MD0 External clock in “Fast Clock Input mode” Value Min 0.8 VCC 0.7 VCC 0.74 VCC 0.8 VCC 2.0 Typ - Max (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 VCC + 0.3 Unit Remarks V V V V V V V V V V CMOS Hysteresis input (D)VCC ≥ 4.5V (D)VCC < 4.5V - VIH External clock in “oscillation mode” - IN 2.5 0.8 VCC VCC 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 IM - VIL CMOS Hysteresis 0.7/0.3 input sePort inputs lected Pnn_m AUTOMOTIVE Hysteresis input selected TTL input selected External clock in “Fast Clock Input mode” EL CMOS Hysteresis 0.8/0.2 input selected AR 0.8 VCC VCC + 0.3 VCC + 0.3 VCC + 0.3 0.8 0.4 VSS + 0.3 Y 0.2 (D)VCC 0.3 (D)VCC 0.5 (D)VCC 0.46 (D)VCC V V (D)VCC ≥ 4.5V (D)VCC < 4.5V V V V V V CMOS Hysteresis input VILX0F PR X0 X0,X1, X0A,X1A RSTX MD2-MD0 0.2 VCC VILX0S VILR VILM External clock in “oscillation mode” 0.2 VCC 68 FME-MB96370 rev 5 MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Output H voltage VOH2 Normal and High Current outputs Symbol Pin Condition 4.5V ≤ (D)VCC ≤ 5.5V IOH = -2mA 3.0V ≤ (D)VCC < 4.5V IOH = -1.6mA 4.5V ≤ (D)VCC ≤ 5.5V IOH = -5mA 3.0V ≤ (D)VCC < 4.5V IOH = -3mA (D)VCC - 0.5 (D)VCC - 0.5 - Value Min Typ Max Unit Remarks V Driving strength set to 2mA (PODR:OD=1, PHDR:HD=0) VOH5 AR VCC 0.5 -1 - Normal and High Current outputs Y - V Driving strength set to 5mA (PODR:OD=0, PHDR:HD=0) 4.5V ≤ DVCC ≤ 5.5V VOH30 IOH = -20mA 4.5V ≤ VCC ≤ 5.5V VOH3 3mA outputs IOH = -3mA IN High current outputs DVCC 0.5 3.0V ≤ DVCC < 4.5V IOH = -30mA - V Driving strength set to 30mA (PHDR:HD=1) Output L voltage VOL2 EL Normal and High Current outputs IM IOH = -2mA 3.0V ≤ VCC < 4.5V 4.5V ≤ (D)VCC ≤ 5.5V IOL = +2mA 3.0V ≤ (D)VCC < 4.5V IOL = +1.6mA 4.5V ≤ (D)VCC ≤ 5.5V IOL = +5mA 3.0V ≤ (D)VCC < 4.5V IOL = +3mA - V I/O circuit type “N” 0.4 V Driving strength set to 2mA (PODR:OD=1, PHDR:HD=0) VOL5 PR Normal and High Current outputs 0.4 V Driving strength set to 5mA (PODR:OD=0, PHDR:HD=0) 4.5V ≤ DVCC ≤ 5.5V IOL = +30mA 3.0V ≤ DVCC < 4.5V IOL = +20mA 3.0V ≤ VCC ≤ 5.5V IOL = +3mA 0.4 0.5 VOL30 High current outputs 3mA outputs Pnn_m V Driving strength set to 30mA (PHDR:HD=1) VOL3 V I/O circuit type “N” VSS < VI < VCC Input leak current IIL AVSS, AVRL < VI < AVCC, AVRH +1 µA Single port pin FME-MB96370 rev 5 69 MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Total LCD leak current Internal LCD divide resistance Pull-up resistance Symbol Σ|IILCD| RLCD RUP Pin all SEG/ COM pins Between V3 and VSS Pnn_m, RSTX Condition Value Min 25 40 25 Typ 0.5 40 100 50 Max 10 65 160 100 Unit Remarks VCC = 5.0V VCC = 5.0V VCC = 3.3V ± 10% VCC = 5.0V ± 10% Maximum leakage µA current of all LCD pins kΩ kΩ kΩ 70 PR EL FME-MB96370 rev 5 IM IN AR Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC. Y MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) PLL Run mode with CLKS1/2 = CLKB = CLKP1 = 16MHz, CLKP2 = 8MHz 1 Flash/ROM wait state (CLKRC and CLKSC stopped) PLL Run mode with CLKS1/2 = CLKB = CLKP1 = 32MHz, CLKP2 = 16MHz (CLKRC and CLKSC stopped) ICCPLL PLL Run mode with CLKS1/2 = 48MHz, CLKB = CLKP1/2 = 24MHz +25˚C +25˚C Value Typ 17.5 Max 23 Unit Remarks mA AR +125˚C 30 +25˚C 32 +125˚C 34 +25˚C 44 +125˚C 46 +25˚C 4.8 +125˚C 5.5 +25˚C 3 +125˚C 3.7 Y 28 34 mA 37.5 44 mA 47.5 58 mA 61.5 5.8 mA 8.2 4.1 mA 6.5 71 +125˚C 19 26 2 Flash/ROM wait states 0 Flash/ROM wait states Power supply current in Run modes* PLL Run mode with CLKS1/2 = 80MHz, CLKB = CLKP1 = 40MHz, CLKP2 = 20MHz FME-MB96370 rev 5 PR ICCMAIN ICCRCH EL 1 Flash wait state (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz 1 Flash/ROM wait state (CLKPLL, CLKSC and CLKRC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2MHz 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped) IM (CLKRC and CLKSC stopped) IN MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 0 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) ICCRCL RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 1 1 Flash/ROM wait state +125˚C 0.95 2.8 +25˚C Value Typ 0.4 Max 0.6 Unit Remarks mA +25˚C Power supply current in Run modes* AR 0.15 0.25 0.7 2.45 0.1 0.2 0.65 2.4 ICCSUB 1 Flash/ROM wait state IM Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz IN +25˚C (CLKMC, CLKPLL and +125˚C CLKSC stopped. Voltage regulator in low power mode, no Flash programming/erasing allowed) 72 PR EL (CLKMC, CLKPLL and +125˚C CLKRC stopped, no Flash programming/erasing allowed) Y mA mA FME-MB96370 rev 5 MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) PLL Sleep mode with CLKS1/2 = CLKP1 = 16MHz, CLKP2 = 8MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = CLKP1 = 32MHz, CLKP2 = 16MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz Power supply current in Sleep modes* (CLKRC and CLKSC stopped) +25˚C Value Typ 5 Max 7 mA +125˚C 5.7 9.5 Unit Remarks +25˚C AR +125˚C 10 +25˚C 9 +125˚C +25˚C 10 13 +125˚C 14 +25˚C +125˚C +25˚C +125˚C 1.5 2.1 0.9 1.5 Y 9 11.5 mA 14 11 mA 13.5 15.5 mA 18 2 mA 4.2 1.5 mA 3.7 73 ICCSPLL (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz (CLKPLL, CLKSC and CLKRC stopped) ICCSMAIN FME-MB96370 rev 5 PR ICCSRCH EL RC Sleep mode with CLKS1/2 = CLKP1/2 = 2MHz (CLKMC, CLKPLL and CLKSC stopped) IM PLL Sleep mode with CLKS1/2 = 80MHz, CLKP1 = 40MHz, CLKP2 = 20MHz IN MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz +25˚C Value Typ 0.3 Max 0.5 Unit Remarks mA +125˚C 0.8 2.7 ICCSRCL Power supply current in Sleep modes* AR 0.56 2.3 0.04 0.54 1.5 0.12 2.3 2 2.1 4.4 0.35 0.5 0.85 2.7 0.08 0.15 0.6 2.3 +25˚C 0.05 +125˚C IN +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C ICCSSUB (CLKMC, CLKPLL and CLKRC stopped) ICCTPLL PLL Timer mode with CLKMC = 4MHz, CLKPLL = 48MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 IM Power supply current in Timer modes* ICCTMAIN EL PR (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode) Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 1 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) 74 Y 0.15 mA mA mA mA mA FME-MB96370 rev 5 MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Condition (at TA) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 1 +25˚C Value Typ 0.35 Max 0.5 mA +125˚C 0.85 2.7 Unit Remarks ICCTRCH +25˚C AR +125˚C 0.6 +25˚C 0.3 +125˚C 0.8 +25˚C 0.03 +125˚C 0.53 +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C +25˚C +125˚C 0.035 0.53 0.02 0.52 0.015 0.4 90 100 3 Y 0.07 0.15 mA 2.3 0.45 mA 2.6 0.1 mA 2.25 0.1 mA 2.25 0.08 mA 2.2 0.06 mA 1.65 140 150 4.5 mA µA This current must be added to all Power supply currents above Must be added to all current above 75 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Power supply current in Timer modes* RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 1 ICCTSUB Power supply current in Stop Mode Power supply current for active Low Voltage detector Power supply current for active Clock modulator FME-MB96370 rev 5 PR ICCH ICCLVD ICCCLOMO EL (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) VRCR:LPMB[2:0] = 110B (Core voltage at 1.8V) VRCR:LPMB[2:0] = 000B (Core voltage at 1.2V) Low voltage detector enabled (RCR:LVDE = 1) Clock modulator enabled (CMCR:PDX = 1) IM ICCTRCL (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) IN MB96370 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Flash Write/Erase current Input capacitance Symbol ICCFLASH CIN Condition (at TA) Current for one Flash module Value Typ 15 15 Max 40 30 Unit mA pF Remarks Must be added to all current above High current outputs Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, High current outputs 76 PR EL FME-MB96370 rev 5 IM IN AR * The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Y Input capacitance CIN - - 5 15 pF MB96370 Series 4. AC Characteristics Source Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Value Min 3 Clock frequency fC X0, X1 0 3.5 0 Clock frequency fFCI X0 3.5 32 X0A, X1A Clock frequency fCL X0A 0 0 50 1 Typ Max 16 16 16 56 Unit Remarks MHz When using a crystal oscillator, PLL off MHz MHz 32.768 - IN 50 100 2 200 4 64 RC clock cycles 200 ±5 - Clock frequency fCR - IM 64 8 5 RC clock stabilization time PLL Clock frequency PLL Phase Jitter Input clock pulse width Input clock pulse width tRCSTAB fCLKVCO TPSKEW PWH, PWL - EL X0,X1 PR PWHL, PWLL X0A,X1A FME-MB96370 rev 5 AR MHz 56 MHz 100 100 kHz kHz kHz MHz MHz ns ns µs kHz When using an oscillation circuit When using an opposite phase external clock When using a single phase external clock When using slow frequency of RC oscillator When using fast frequency of RC oscillator Applied after any reset and when activating the RC oscillator. Permitted VCO output frequency of PLL (CLKVCO) For CLKMC (PLL input clock) ≥ 4MHz, jitter coming from external oscillator, crystal or resonator is not covered Duty ratio is about 30% to 70% Y When using an opposite phase external clock, PLL off When using a crystal oscillator or opposite phase external clock, PLL on When using a single phase external clock in “Fast Clock Input mode” , PLL off When using a single phase external clock in “Fast Clock Input mode” , PLL on 77 MB96370 Series tCYL VIH X0 PWH PWL VIL tCYLL X0A PWHL AR PWLL 78 PR EL FME-MB96370 rev 5 IM IN Y VIH VIL MB96370 Series Internal Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Core Voltage Settings Parameter Internal System clock frequency (CLKS1 and CLKS2) Symbol Min fCLKS1, fCLKS2 0 0 Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) 1.8V Max 92 72 Min 0 0 1.9V Max 96 80 MHz MHz Others than below MB96F378/ MB96F379 Others than below MB96F378/ MB96F379 Unit Remarks fCLKB, fCLKP1 0 52 AR 0 56 0 0 40 32 0 Internal peripheral clock frequency (CLKP2) fCLKP2 0 36 28 FME-MB96370 rev 5 PR EL IM IN Y MHz MHz MHz 79 MB96370 Series External Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Reset input time Symbol tRSTL Pin RSTX Value Min 500 Typ Max Unit ns Remarks tRSTL RSTX 0.2 VCC 80 PR EL FME-MB96370 rev 5 IM IN AR 0.2 VCC Y MB96370 Series Power On Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Power on rise time Power off time Symbol tR tOFF Pin Vcc Vcc Value Min 0.05 1 Typ Max 30 Unit ms ms Remarks tR VCC 0.2 V 2.7V AR 0.2 V tOFF If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. VCC 3V IM EL IN FME-MB96370 rev 5 PR Y 0.2 V Rising edge of 50 mV/ms maximum is allowed 81 MB96370 Series External Input timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin INTn(_R) NMI(_R) Pnn_m Input pulse width tINH tINL TINn(_R) TTGn(_R) ADTG(_R) FRCKn(_R) INn(_R) Note : Relocated Resource Inputs have same characteristics ⎯ 2*tCLKP1 + 200 (tCLKP1=1/ fCLKP1) Condition Value Min 200 Max ⎯ Unit ns Used Pin input function External Interrupt NMI General Purpose IO Reload Timer PPG Trigger input AR VIL tINL Y ⎯ ns VIL AD Converter Trigger Free Running Timer external clock Input Capture External Pin input VIH 82 PR EL FME-MB96370 rev 5 IM tINH IN VIH MB96370 Series Slew Rate High Current Outputs (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition Output driving strength set to “30mA” Value Min Max Unit Remarks Note : Relocated Resource Inputs have same characteristics • Slew rate output timing VH VL tR30 FME-MB96370 rev 5 PR EL IM IN AR VH VL tF30 Y VH = VOL30 + 0.9 × (VOH30 - VOL30) VL = VOL30 + 0.1 × (VOH30 - VOL30) Output rise/fall time tR30 tF30 I/O circuit type M 15 ⎯ ns 83 MB96370 Series External Bus timing Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. Basic Timing Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) tCYC ECLK tCHCL tCLCH tCHCBH ECLK → UBX/ LBX / CSn time tCHCBL tCLCBH tCLCBL tCHLH ECLK → ALE time tCHLL tCLLH tCLLL ECLK → address valid time (non-multiplexed) tCHAV tCLAV tCHAV ECLK → address valid time (multiplexed) tCLAV tCLADV ALE, ECLK CSn, UBX, LBX, ECLK ECLK ⎯ AR tCYC/2-5 -20 -20 -20 -20 -10 -10 -10 -10 -15 -15 -15 -15 -15 -15 -10 -10 -10 -10 tCYC/2-5 Y Min 25 ⎯ 20 20 20 20 10 10 10 10 15 15 15 15 15 15 10 10 10 10 Symbol Pin Condition Value Max Unit Remarks tCYC/2+5 tCYC/2+5 ns ⎯ ns IN ⎯ EBM:NMS=1 EBM:NMS=0 EBM:NMS=0 ns A[23:0], ECLK A[23:16], ECLK IM ns ns ns tCHADV ECLK → RDX /WRX time tCHRWH tCHRWL tCLRWH tCLRWL EL AD[15:0], ECLK RDX, WRX, WRLX,WRHX, ECLK 84 PR ⎯ ns FME-MB96370 rev 5 MB96370 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol tCYC ECLK tCHCL tCLCH tCHCBH ECLK → UBX/ LBX / CSn time tCHCBL tCLCBH tCLCBL tCHLH ECLK → ALE time tCHLL tCLLH tCLLL ECLK → address valid time (non-multiplexed) tCHAV tCLAV tCHAV ECLK → address valid time (multiplexed) tCLAV tCLADV tCHADV tCHRWH ECLK → RDX /WRX time tCHRWL tCLRWH tCLRWL ALE, ECLK CSn, UBX, LBX, ECLK ⎯ ECLK ⎯ Pin Condition Value Min 30 tCYC/2-8 tCYC/2-8 -25 Max ⎯ tCYC/2+8 tCYC/2+8 25 25 25 25 15 15 15 15 20 20 20 20 20 20 15 15 15 15 ns ns ns ns ns ns ns Unit Remarks A[23:0], ECLK EBM:NMS=1 A[23:16], ECLK IN ⎯ IM AD[15:0], ECLK RDX, WRX, WRLX, WRHX, ECLK EL FME-MB96370 rev 5 PR AR ⎯ EBM:NMS=0 EBM:NMS=0 Y -25 -25 -25 -15 -15 -15 -15 -20 -20 -20 -20 -20 -20 -15 -15 -15 -15 85 MB96370 Series tCYC tCHCL ECLK 0.8*Vcc 0.2*Vcc tCHAV A[23:0] tCLAV tCLCH CSn LBX UBX tCHRWL RDX WRX (WRLX, WRHX) AR tCHLH Y tCLRWL tCHLL tCHCBL tCLCBH tCLCBL tCHCBH tCLRWH tCHRWH tCLLH ALE tCLLL IN Address tCLADV tCHADV AD[15:0] Refer to the Hardware Manual for detailed Timing Charts 86 PR EL FME-MB96370 rev 5 IM MB96370 Series Bus Timing (Read) Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Conditions EACL:STS=0 and EACL:ACE=0 Value Min tCYC/2 − 5 tCYC − 5 Max ⎯ ⎯ ⎯ ⎯ ⎯ Unit Remarks ALE pulse width (multiplexed) tLHLL ALE EACL:STS=1 EACL:STS=0 and EACL:ACE=1 EACL:STS=0 and EACL:ACE=0 ns tAVLL ALE, A[23:16], AR -15 ⎯ EACL:STS=1 and 3tCYC/2 − 15 EACL:ACE=0 EACL:STS=0 and EACL:ACE=1 Y tCYC − 15 2tCYC − 15 tCYC/2 − 15 tCYC − 15 2tCYC − 15 tCYC/2 − 15 tCYC/2 − 15 3tCYC/2 − 15 5tCYC/2 − 15 tCYC − 15 2tCYC − 15 3tCYC/2 − 5 ns ⎯ ⎯ ⎯ ⎯ ns ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ⎯ ⎯ ns ⎯ 2tCYC − 55 ns w/o cycle extension EBM:NMS = 0 Valid address ⇒ ALE ↓ time (multiplexed) EACL:STS=1 and 5tCYC/2 − 15 EACL:ACE=1 EACL:STS=0 and EACL:ACE=0 EACL:STS=1 and EACL:ACE=0 tADVLL ALE,AD[15:0] ALE ↓ ⇒ Address valid time (multiplexed) Valid address ⇒ RDX ↓ time (non-multiplexed) tLLAX ALE, AD[15:0] IM IN EACL:STS=0 EACL:STS=1 EBM:NMS= 1 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EBM:NMS= 1 EACL:STS=0 and 3tCYC/2 − 15 EACL:ACE=1 EACL:STS=1 and EACL:ACE=1 ns tAVRL RDX, A[23:0] EL ns tAVRL Valid address ⇒ RDX ↓ time (multiplexed) RDX, A[23:16] Valid address ⇒ Valid data input (non-multiplexed) FME-MB96370 rev 5 PR tAVDV tADVRL RDX, AD[15:0] A[23:0], AD[15:0] 87 MB96370 Series (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 Value Min ⎯ ⎯ ⎯ ⎯ Max 3tCYC − 55 Unit Remarks tAVDV Valid address ⇒ Valid data input (multiplexed) A[23:16], AD[15:0] ns 4tCYC − 55 5tCYC/2 − 55 ns 7tCYC/2 − 55 ⎯ ns w/o cycle extension Y ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ tADVDV AD[15:0] w/o cycle extension AR ⎯ 0 0 tCYC − 15 tCYC/2 − 15 tCYC/2 − 10 tCYC/2 − 10 − 10 ⎯ RDX pulse width RDX ↓ ⇒ Valid data input RDX ↑ ⇒ Data hold time Address valid ⇒ Data hold time RDX ↑ ⇒ ALE ↑ time tRLRH RDX tRLDV RDX, AD[15:0] tRHDX RDX, AD[15:0] tAXDX A[23:0], AD[15:0] ⎯ ⎯ ⎯ ⎯ 3 tCYC/2 − 5 w/o cycle extension w/o cycle extension 3 tCYC/2 − 50 ns ns ns tRHLH RDX, ALE tAVCH A[23:0], ECLK tADVCH AD[15:0], ECLK tRLCH RDX, ECLK tLLRL ALE, RDX IN ⎯ ⎯ ⎯ EACL:STS=1 and 3tCYC/2 − 10 EACL:ACE=1 other ECL:STS, tCYC/2 − 10 EACL:ACE setting ns RDX ↓ ⇒ ECLK ↑ time ALE ↓ ⇒ RDX ↓ time ECLK↑ ⇒ Valid data input IM Valid address ⇒ ECLK ↑ time ns ns ns ns EACL:STS=0 EACL:STS=1 88 PR EL tCHDV AD[15:0], ECLK tCYC − 50 FME-MB96370 rev 5 MB96370 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions EACL:STS=0 and EACL:ACE=0 Value Min tCYC/2 − 8 tCYC − 8 3tCYC/2 − 8 Max ⎯ ⎯ ⎯ ⎯ ⎯ Unit Remarks ALE pulse width (multiplexed) tLHLL ALE EACL:STS=1 EACL:STS=0 and EACL:ACE=1 EACL:STS=0 and EACL:ACE=0 ns tAVLL ALE, A[23:16], AR -20 ⎯ EACL:STS=1 and 3tCYC/2 − 20 EACL:ACE=0 EACL:STS=0 and EACL:ACE=1 Y tCYC − 20 2tCYC − 20 tCYC/2 − 20 tCYC − 20 2tCYC − 20 tCYC/2 − 20 tCYC/2 − 20 3tCYC/2 − 20 5tCYC/2 − 20 tCYC − 20 2tCYC − 20 ns ⎯ ⎯ ⎯ ⎯ ns ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ⎯ ⎯ ns ⎯ 2tCYC − 60 ns w/o cycle extension EBM:NMS =0 Valid address ⇒ ALE ↓ time (multiplexed) EACL:STS=1 and 5tCYC/2 − 20 EACL:ACE=1 EACL:STS=0 and EACL:ACE=0 tADVLL ALE, AD[15:0] ALE ↓ ⇒ Address valid time (multiplexed) Valid address ⇒ RDX ↓ time (non-multiplexed) tLLAX ALE, AD[15:0] IM IN EACL:STS=0 EACL:STS=1 EBM:NMS= 1 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EBM:NMS= 1 EACL:STS=1 and EACL:ACE=0 EACL:STS=0 and 3tCYC/2 − 20 EACL:ACE=1 EACL:STS=1 and EACL:ACE=1 ns tAVRL RDX, A[23:0] EL ns tAVRL Valid address ⇒ RDX ↓ time (multiplexed) RDX, A[23:16] Valid address ⇒ Valid data input (non-multiplexed) FME-MB96370 rev 5 PR tAVDV tADVRL RDX, AD[15:0] A[23:0], AD[15:0] 89 MB96370 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 Value Min ⎯ ⎯ ⎯ ⎯ Max 3tCYC − 60 Unit Remarks tAVDV Valid address ⇒ Valid data input (multiplexed) A[23:16], AD[15:0] ns 4tCYC − 60 5tCYC/2 − 60 ns 7tCYC/2 − 60 ⎯ ns w/o cycle extension Y ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ tADVDV AD[15:0] w/o cycle extension AR ⎯ 0 0 tCYC − 20 tCYC/2 − 20 tCYC/2 − 15 tCYC/2 − 15 − 15 ⎯ RDX pulse width RDX ↓ ⇒ Valid data input RDX ↑ ⇒ Data hold time Address valid ⇒ Data hold time RDX ↑ ⇒ ALE ↑ time tRLRH RDX tRLDV RDX, AD[15:0] tRHDX RDX, AD[15:0] tAXDX A[23:0] ⎯ ⎯ ⎯ ⎯ 3tCYC/2 − 8 w/o cycle extension w/o cycle extension 3tCYC/2 − 55 ns ns ns tRHLH RDX, ALE tAVCH A[23:0], ECLK tADVCH AD[15:0], ECLK tRLCH RDX, ECLK tLLRL ALE, RDX IN ⎯ ⎯ ⎯ EACL:STS=1 and 3tCYC/2 − 15 EACL:ACE=1 other ECL:STS, tCYC/2 − 15 EACL:ACE setting ns RDX ↓ ⇒ ECLK ↑ time ALE ↓ ⇒ RDX ↓ time ECLK↑ ⇒ Valid data input IM Valid address ⇒ ECLK ↑ time ns ns ns ns EACL:STS=0 EACL:STS=1 90 PR EL tCHDV AD[15:0], ECLK tCYC − 55 FME-MB96370 rev 5 MB96370 Series tAVCH tADVCH ECLK 0.8*Vcc tRLCH tCHDV tAVLL tADVLL ALE tLHLL tAVRL tADVRL RDX tLLAX tRHLH tLLRL A[23:0] IN tADVDV AR tRLDV tRHDX VIH VIL VIH Read data VIL tAXDX . tAVDV AD[15:0] Address Refer to the Hardware Manual for detailed Timing Charts Bus Timing (Write) Parameter Valid address ⇒ WRX ↓ time (non-multiplexed) EL Pin (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Condition Value Min tCYC/2 − 15 tCYC − 15 3tCYC/2 − 15 5tCYC/2 − 15 tCYC − 15 2tCYC − 15 tCYC − 5 Max ⎯ ns ⎯ ⎯ ns ⎯ ⎯ ns ⎯ ⎯ ns w/o cycle extension Symbol IM Y tRLRH 0.2*VCC Unit Remarks PR tAVWL tAVWL tADVWL tWLWH WRX, WRLX, WRHX, A[23:0] WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] WRX, WRXL, WRHX EACL:STS=0 EBM:NMS=1 EACL:STS=1 EBM:NMS=1 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 Valid address ⇒ WRX ↓ time (multiplexed) WRX pulse width ⎯ FME-MB96370 rev 5 91 MB96370 Series (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Valid data output ⇒ WRX ↑ time WRX ↑ ⇒ Data hold time WRX ↑ ⇒ Address valid time (non-multiplexed) WRX ↑ ⇒ Address valid time (multiplexed) WRX ↑ ⇒ ALE ↑ time (multiplexed) WRX ↓ ⇒ ECLK ↑ time CSn ⇒ WRX time (non-multiplexed) Symbol Pin WRX, WRLX, WRHX, AD[15:0] WRX, WRLX, WRHX, AD[15:0] Condition Value Min tCYC − 20 Max ⎯ Unit Remarks tDVWH ⎯ ns w/o cycle extension tWHDX ⎯ EACL:STS=1 tCYC/2 − 15 − 15 ⎯ ⎯ ns ns ns ns tWHAX EBM:NMS=1 tWHAX WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, ALE WRX, WRLX, WRHX, ECLK WRX, WRLX, WRHX, CSn AR tCYC/2 − 15 2tCYC − 10 tCYC − 10 tCYC/2 − 10 ⎯ ⎯ ⎯ ⎯ − 15 tCYC/2 − 15 tCYC/2 − 15 Value Min tCYC/2 − 20 tCYC − 20 WRX, WRLX, EBM:NMS=1 WRHX, A[23:0] EACL:STS=0 tCYC/2 − 15 EBM:NMS=0 tWHLH IN ⎯ EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting Y ⎯ ⎯ ⎯ ⎯ ⎯ tCYC/2 − 15 tCYC − 15 3tCYC/2 − 15 5tCYC/2 − 15 ⎯ ⎯ ⎯ Max ⎯ ⎯ ns EBM:NMS=0 tWLCH ns tCSLWL IM EACL:STS=1 EBM:NMS=1 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:STS=1 EBM:NMS=1 EACL:STS=0 EBM:NMS=1 EBM:NMS=0 EACL:STS=0 EBM:NMS=1 ns EL Pin CSn ⇒ WRX time (multiplexed) tCSLWL WRX, WRLX, WRHX, CSn ns WRX ⇒ CSn time (non-multiplexed) WRX ⇒ CSn time (multiplexed) tWHCSH WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn ns ns ns Parameter Valid address ⇒ WRX ↓ time (non-multiplexed) Symbol PR tWHCSH (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Condition EACL:STS=0 EBM:NMS=1 EACL:STS=1 EBM:NMS=1 Unit Remarks tAVWL WRX, WRLX, WRHX, A[23:0] ns 92 FME-MB96370 rev 5 MB96370 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] WRX, WRXL, WRHX WRX, WRLX, WRHX, AD[15:0] WRX, WRLX, WRHX, AD[15:0] Condition EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 Value Min 3tCYC/2 − 20 5tCYC/2 − 20 Max ⎯ Unit Remarks tAVWL Valid address ⇒ WRX ↓ time (multiplexed) tADVWL ns ⎯ ⎯ ns ⎯ ⎯ ⎯ ns w/o cycle extension w/o cycle extension 2tCYC − 20 tCYC − 8 WRX pulse width Valid data output ⇒ WRX ↑ time WRX ↑ ⇒ Data hold time WRX ↑ ⇒ Address valid time (non-multiplexed) WRX ↑ ⇒ Address valid time (multiplexed) WRX ↑ ⇒ ALE ↑ time (multiplexed) WRX ↓ ⇒ ECLK ↑ time CSn ⇒ WRX time (non-multiplexed) tWLWH ⎯ ⎯ tDVWH AR tCYC − 25 − 20 tCYC − 15 ⎯ Y ⎯ ⎯ ⎯ ⎯ − 20 tCYC − 20 ns IN EACL:STS=1 EBM:NMS=1 EBM:NMS=0 EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting EACL:STS=0 EBM:NMS=1 EACL:STS=1 EBM:NMS=1 EACL:ACE=0 EBM:NMS=0 EACL:ACE=1 EBM:NMS=0 EACL:STS=1 EBM:NMS=1 EACL:STS=0 EBM:NMS=1 EBM:NMS=0 tWHDX ⎯ tCYC/2 − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ tCYC/2 − 20 ns ns ns ns tWHAX WRX, WRLX, EBM:NMS=1 WRHX, A[23:0] EACL:STS=0 WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, ALE tCYC/2 − 20 tCYC/2 − 20 2tCYC − 15 tWHAX EL tWHLH IM ns EBM:NMS=0 tWLCH WRX, WRLX, WRHX, ECLK WRX, WRLX, WRHX, CSn tCYC/2 − 15 ns PR tCSLWL ns tCYC − 20 3tCYC/2 − 20 5tCYC/2 − 20 ⎯ ⎯ ⎯ CSn ⇒ WRX time (multiplexed) tCSLWL WRX, WRLX, WRHX, CSn ns WRX ⇒ CSn time (non-multiplexed) WRX ⇒ CSn time (multiplexed) tWHCSH WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn ns ns ns tCYC/2 − 20 tCYC/2 − 20 tWHCSH FME-MB96370 rev 5 93 MB96370 Series tWLCH 0.8*VCC ECLK tWHLH ALE Y tWHCSH tWHAX tWHDX Write data tAVWL tADVWL WRX (WRLX, WRHX) tWLWH . 0.2*VCC tCSLWL CSn A[23:0] AD[15:0] Address Refer to the Hardware Manual for detailed Timing Charts Ready Input Timing Parameter RDY setup time RDY hold time (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Pin Test Condition ⎯ Rated Value Min 35 0 Max ⎯ ⎯ Units ns ns Remarks Symbol tRYHS PR tRYHH Symbol tRYHS tRYHH (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Pin Test Condition ⎯ Rated Value Min 45 0 Max ⎯ ⎯ Units ns ns Remarks Parameter RDY setup time RDY hold time Note : If the RDY setup time is insufficient, use the auto-ready function. 94 EL RDY RDY RDY RDY IM IN tDVWH AR FME-MB96370 rev 5 MB96370 Series ECLK 0.8*VCC tRYHS RDY When WAIT is not used. VIH tRYHH VIH RDY When WAIT is used. VIL Refer to the Hardware Manual for detailed Timing Charts Hold Timing Parameter Pin floating ⇒ HAKX ↓ time (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) IN Pin ⎯ Pin ⎯ tXHAL AR Condition Condition 0.2*VCC High-Z Symbol tXHAL tHAHV Y Value Min Max tCYC − 20 tCYC + 20 tCYC − 20 tCYC + 20 Units ns ns Remarks Value Min Max tCYC − 25 tCYC + 25 tCYC − 25 tCYC + 25 Units ns ns Remarks 0.8*VCC tHAHV HAKX HAKX (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Pin floating ⇒ HAKX ↓ time Symbol tXHAL HAKX ↑ time ⇒ Pin valid time HAKX PR Each pin Refer to the Hardware Manual for detailed Timing Charts FME-MB96370 rev 5 EL tHAHV IM HAKX HAKX 0.8*VCC 0.2*VCC HAKX ↑ time ⇒ Pin valid time 95 MB96370 Series USART timing WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. (TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) VCC = AVCC= 4.5V VCC = AVCC= 3.0V to 5.5V to 4.5V Unit Min Max Min Max Parameter Serial clock cycle time SCK ↓ → SOT delay time SOT → SCK ↑ delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time SCK fall time SCK rise time Symbol tSCYCI tSLOVI tOVSHI tIVSHI tSHIXI tSLSHE tSHSLE tSLOVE tIVSHE tSHIXE tFE tRE Pin SCKn SCKn, SOTn SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn Condition Y ⎯ +20 ⎯ ⎯ ⎯ ⎯ ⎯ 2 tCLKP1 + 45 ⎯ ⎯ 20 20 4 tCLKP1 -20 4 tCLKP1 -30 ⎯ +30 ⎯ ⎯ ⎯ ⎯ ⎯ 2 tCLKP1 + 55 ⎯ ⎯ 20 20 ns ns ns ns ns ns ns ns ns ns ns ns AR N*tCLKP1 - 20 *1 tCLKP1 + 45 0 tCLKP1 + 10 tCLKP1 + 10 ⎯ tCLKP1/2 + 10 tCLKP1 + 10 ⎯ ⎯ Internal Shift Clock Mode N*tCLKP1 30 *1 tCLKP1 + 55 0 tCLKP1 + 10 tCLKP1 + 10 ⎯ tCLKP1/2 + 10 tCLKP1 + 10 ⎯ ⎯ *1: Parameter N depends on tSCYCI and can be calculated as follows: • if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 • if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N 4*tCLKP1 5*tCLKP1, 6*tCLKP1 7*tCLKP1, 8*tCLKP1 ... 96 2 3 4 ... FME-MB96370 rev 5 PR Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL” • tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns EL IM External Shift Clock Mode IN MB96370 Series tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC 0.2*VCC tSLOVI tOVSHI 0.8*VCC 0.2*VCC SOT tIVSHI VIH VIL SIN Internal Shift Clock Mode IM tSLSHE VIH VIL IN VIL VIH tRE 0.8*VCC 0.2*VCC tIVSHE VIH VIL SCK for ESCR:SCES = 0 AR tSHIXI VIH VIL tSHSLE VIH VIH VIL VIL tSHIXE VIH VIL SCK for ESCR:SCES = 1 PR SOT SIN FME-MB96370 rev 5 EL VIH VIL tFE tSLOVE External Shift Clock Mode Y 97 SCK for ESCR:SCES = 1 0.8*VCC 0.8*VCC MB96370 Series I2C Timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter SCL clock frequency Hold time (repeated) START condition SDA↓→SCL↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL↑→SDA↓ Data hold time SCL↓→SDA↓↑ Data set-up time SDA↓↑→SCL↑ Set-up time for STOP condition SCL↑→SDA↑ Bus free time between a STOP and START condition Output fall time from 0.7*Vcc to 0.3*Vcc with a bus capacitance from 10 pF to 400 pF Capacitive load for each bus line Pulse width of spikes which will be suppressed by input noise filter Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS tof Standard-mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ Fast-mode*1 Min 0 0.6 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9 ⎯ ⎯ ⎯ 250 400 1*tCLKP1*3 Unit kHz µs µs µs µs µs ns µs µs ns pF ns AR 3.45 ⎯ ⎯ ⎯ 250 400 n/a IN ⎯ n/a tHDSTA IM Cb tSP tSUSTA 20 + 0.1*Cb *2 *2 : Cb = capacitance of one bus line in pF. *3 : tCLKP1 is the cycle time of the periperal clock CLKP1. SDA PR EL *1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. Y 1.3 0.6 0.6 0 100 0.6 1.3 20 + 0.1*Cb *2 ⎯ 0 tSUSTO tLOW SCL tSUDAT tBUS tHDSTA tHDDAT tHIGH • VOH = 0.7 * VCC • VOL = 0.3 * VCC • CMOS Hysteresis 0.7/0.3 input selected 98 FME-MB96370 rev 5 MB96370 Series 5. Analog Digital Converter (TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero transition voltage Full scale transition voltage Compare time Sampling time Symbol VOT VFST Pin ANn ANn Value Min Typ Max 10 ±3 ± 2.5 Unit bit LSB LSB Remarks AVRL - AVRL+ AVRL + 1.5 LSB 0.5 LSB 2.5 LSB AVRH - AVRH - AVRH + 3.5 LSB 1.5 LSB 0.5 LSB 1.0 2.0 0.5 1.2 -1 16,500 +1 - AR 2.5 0.7 +1.2 AVRH AVcc 0.25 AVCC 5 5 1 5 4 Y ± 1.9 LSB V V µs µs µs µs 4.5V ≤ ΑVCC ≤ 5.5V 3.0V ≤ ΑVCC < 4.5V 4.5V ≤ ΑVCC ≤ 5.5V 3.0V ≤ ΑVCC < 4.5V TA ≤ 105 ˚C, µA AVSS, AVRL < VI < AVCC, AVRH 105 ˚C < TA ≤ 125 ˚C, µA AVSS, AVRL < VI < AVCC, AVRH V V V mA A/D Converter active µA A/D Converter not operated mA A/D Converter active µA LSB A/D Converter not operated 99 IAIN Reference voltage range AVRH AVRL IA EL AVRH AVRL AVcc AVcc AVRH/ AVRL AVRH/ AVRL ANn - Analog input voltage range VAIN Power supply current PR IAH IR IRH Reference voltage current Offset between input channels Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. FME-MB96370 rev 5 IM ANn -1.2 ANn AVRL 0.75 AVcc AVSS - Analog input leakage current (during conversion) IN MB96370 Series Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error : Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error 3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB × (N − 1) + 0.5 LSB} 004 003 002 001 0.5 LSB AVRL Actual conversion characteristics Ideal characteristics EL Analog input IM Total error of digital output “N” = N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. 100 PR VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL 1 LSB = (Ideal value) [V] 1024 IN AVRH VNT (Actually-measured value) AR 1.5 LSB Y [LSB] FME-MB96370 rev 5 MB96370 Series Nonlinearity error 3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Differential nonlinearity error Ideal characteristics Actual conversion characteristics Digital output N 004 003 002 Y [V] N−1 Ideal characteristics 001 VOT (actual measurement value) AVRL Analog input AVRH AR AVRL V (N + 1) T (actual measurement value) VNT (actual measurement value) N−2 Actual conversion characteristics AVRH Nonlinearity error of digital output N = IN Analog input VNT − {1 LSB × (N − 1) + VOT} 1 LSB −1 LSB [LSB] [LSB] Differential nonlinearity error of digital output N = 1 LSB = IM V (N+1) T − VNT 1 LSB VFST − VOT 1022 FME-MB96370 rev 5 PR EL N : A/D converter digital output value VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 101 MB96370 Series Accuracy and setting of the A/D Converter sampling time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVcc voltage level. The following replacement model can be used for the calculation: MCU Rext Source Cext CIN CADC RADC Sampling switch The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement model above can be used: Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC) • Do not select a sampling time below the absolute minimum permitted value (0.5µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V). • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. In this case the internal sampling capacitance CADC will be charged out of this external capacitance. • The accuracy gets worse as |AVRH - AVRL| becomes smaller. 102 PR • A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. EL IM IN Rext: external driving impedance Cext: capacitance of PCB at A/D converter input CIN: capacitance of MCU input pin: 15pF (max) RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V 12kΩ (max) for 3.0V ≤ AVcc < 4.5V CADC: sampling capacitance within MCU: 10pF (max) AR FME-MB96370 rev 5 Y Analog input Comparator MB96370 Series 6. Alarm Comparator (TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Value Min AVCC Typ 25 Max 45 Unit µA Remarks Alarm comparator enabled in fast mode (one channel) Alarm comparator enabled in slow mode (one channel) Alarm comparator disabled IA5ALMF Power supply current Y 13 5 +1 +3 AVCC 1.55 2.85 300 1 10 10 500 IA5ALMS IA5ALMH -1 -3 0 7 - µA µA AR 1.1 1.3 2.4 2.6 0.1 1 1 100 ALARM pin input current ALARM pin input voltage range External low threshold high->low transition External low threshold low->high transition External high threshold high->low transition External high threshold low->high transition Internal low threshold high->low transition Internal low threshold low->high transition Internal high threshold high->low transition Internal high threshold low->high transition Switching hysteresis Comparison time IALIN VALIN VEVTL(H->L) VEVTL(L->H) VEVTH(H->L) VEVTH(L->H) VIVTL(H->L) VIVTL(L->H) µA TA = 25 ˚C µA TA = 125 ˚C V V V INTREF = 0 V V V V INTREF = 1 V V mV µs µs ms µs CMD = 1 (fast) CMD = 0 (slow) Threshold levels specified above are not guaranteed within this time IM 0.9 2.2 50 - 0.78 * AVCC 0.78 * AVCC -0.25 -0.1 VIVTH(H->L) VIVTH(L->H) VHYS Power-up stabilization time after enabling alarm comparator Slow/Fast mode transition time FME-MB96370 rev 5 PR tCOMPF tCOMPS tPD tCMD EL ALARM0, ALARM1 IN - 0.36 * AVCC 0.36 * AVCC -0.25 -0.1 0.36 * AVCC 0.36 * AVCC +0.1 +0.25 0.78 * AVCC 0.78 * AVCC +0.1 +0.25 103 MB96370 Series Comparator Output H L VxVTx(H->L) VxVTx(L->H) VHYS 104 PR EL FME-MB96370 rev 5 IM IN AR Y VALIN MB96370 Series 7. Low Voltage Detector characteristics (TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Stabilization time Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 Level 13 Level 14 Level 15 Symbol TLVDSTAB VDL0 VDL1 VDL2 VDL3 VDL4 VDL5 VDL6 VDL7 VDL8 VDL9 VDL10 VDL11 VDL12 VDL13 VDL14 VDL15 Value Min 2.7 2.9 3.1 3.5 3.6 3.7 3.8 3.9 4.0 4.1 Max 75 2.9 3.1 3.3 3.75 3.85 3.95 4.05 4.15 4.25 4.35 Unit µs V V V V V V V V V V Remarks After power-up or change of detection level CILCR:LVL[3:0]=”0000” CILCR:LVL[3:0]=”0001” CILCR:LVL[3:0]=”0010” CILCR:LVL[3:0]=”0011” CILCR:LVL[3:0]=”0100” CILCR:LVL[3:0]=”0101” CILCR:LVL[3:0]=”0110” CILCR:LVL[3:0]=”0111” CILCR:LVL[3:0]=”1000” CILCR:LVL[3:0]=”1001” not used not used not used not used not used not used CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register. V For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ----- . EL IM dt µs Faster variations are regarded as noise and may not be detected. FME-MB96370 rev 5 PR The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of “Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to 3.0V). IN AR 105 Y MB96370 Series Low Voltage Detector Operation In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC VDLx, Min dt AR Y dV Time [s] Power Reset Extension Time VDLx, Max Normal Operation Low Voltage Reset Assertion 106 PR EL FME-MB96370 rev 5 IM IN MB96370 Series 8. FLASH memory program/erase characteristics (TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Sector erase time Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash data retention time Value Min 10 000 20 Typ 0.9 n*0.9 23 Max 3.6 n*3.6 370 Unit s s Remarks Without erasure pre-programming time Without erasure pre-programming time (n is the number of Flash sector of the device) AR cycle year - Y us Without overhead time for submitting write command *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) FME-MB96370 rev 5 PR EL IM IN 107 MB96370 Series ■ EXAMPLE CHARACTERISTICS 1. Temperature dependency of power supply currents The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes. Common condition for all operation modes: • VCC = AVCC = 5.0V • Main clock = 4MHz external clock • Sub clock = 32kHz external clock Operation mode details: Mode name PLL Run 40 Details Main Run RC Run 2M RC Run mode current ICCRCH with the following settings: • RC oscillator set to 2MHz (CKFCR:RCFS = 1) • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, Main oscillator and Sub oscillator stopped 108 PR Main Run mode current ICCMAIN with the following settings: • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, RC oscillator and Sub oscillator stopped EL IM PLL Run 24 PLL Run mode current ICCPLL with the following settings: • fCLKS1 = fCLKS2 = 48MHz • fCLKB = fCLKP1 = fCLKP2 = 24MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • 0 Flash/ROM wait states (MTCRA=2208H) • RC oscillator and Sub oscillator stopped IN PLL Run mode current ICCPLL with the following settings: • fCLKS1 = fCLKS2 = 80MHz • fCLKB = fCLKP1 = 40MHz • fCLKP2 = 20MHz • Regulator in High Power Mode • Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) • 1 Flash/ROM wait states (MTCRA=6B09H) • RC oscillator and Sub oscillator stopped AR FME-MB96370 rev 5 Y MB96370 Series Mode name RC Run 100k Details RC Run mode current ICCRCL with the following settings: • RC oscillator set to 100kHz (CKFCR:RCFS = 0) • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz • Regulator in Low Power Mode A (SMCR:LPMS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, Main oscillator and Sub oscillator stopped Sub Run mode current ICCSUB with the following settings: • fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz • Regulator in Low Power Mode A (by hardware) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • 1 Flash/ROM wait states (MTCRA=0239H) • PLL, RC oscillator and Main oscillator stopped PLL Sleep 40 PLL Sleep 24 Main Sleep Main Sleep mode current ICCSMAIN with the following settings: • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • PLL, RC oscillator and Sub oscillator stopped RC Sleep 100k RC Sleep mode current ICCSRCL with the following settings: • RC oscillator set to 100kHz (CKFCR:RCFS = 0) • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, Main oscillator and Sub oscillator stopped FME-MB96370 rev 5 PR RC Sleep 2M RC Sleep mode current ICCSRCH with the following settings: • RC oscillator set to 2MHz (CKFCR:RCFS = 1) • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • PLL, Main oscillator and Sub oscillator stopped EL IM PLL Sleep mode current ICCSPLL with the following settings: • fCLKS1 = fCLKS2 = 48MHz • fCLKP1 = fCLKP2 = 24MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • RC oscillator and Sub oscillator stopped IN PLL Sleep mode current ICCSPLL with the following settings: • fCLKS1 = fCLKS2 = 80MHz • fCLKP1 = 40MHz • fCLKP2 = 20MHz • Regulator in High Power Mode • Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) • RC oscillator and Sub oscillator stopped AR 109 Y Sub Run MB96370 Series Mode name Sub Sleep Details Sub Sleep mode current ICCSSUB with the following settings: • fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz • Regulator in Low Power Mode A (by hardware) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, RC oscillator and Main oscillator stopped PLL Timer mode current ICCTPLL with the following settings: • fCLKS1 = fCLKS2 = 48MHz • Regulator in High Power Mode • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) • RC oscillator and Sub oscillator stopped PLL Timer 48 Main Timer Main Timer mode current ICCTMAIN with the following settings: • fCLKS1 = fCLKS2 = 4MHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, RC oscillator and Sub oscillator stopped RC Timer mode current ICCTRCH with the following settings: • RC oscillator set to 2MHz (CKFCR:RCFS = 1) • fCLKS1 = fCLKS2 = 2MHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, Main oscillator and Sub oscillator stopped RC Timer mode current ICCTRCL with the following settings: • RC oscillator set to 100kHz (CKFCR:RCFS = 0) • fCLKS1 = fCLKS2 = 100kHz • Regulator in Low Power Mode A (SMCR:LPMSS = 1) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, Main oscillator and Sub oscillator stopped Sub Timer mode current ICCTSUB with the following settings: • fCLKS1 = fCLKS2 = 32kHz • Regulator in Low Power Mode A (by hardware) • Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) • PLL, RC oscillator and Main oscillator stopped Stop mode current ICCH with the following settings: • Regulator in Low Power Mode B (by hardware) • Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B) Stop mode current ICCH with the following settings: • Regulator in Low Power Mode B (by hardware) • Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B) RC Timer 2M RC Timer 100k Sub Timer Stop 1.8V Stop 1.2V 110 PR EL IM IN AR FME-MB96370 rev 5 Y MB96370 Series MB96F378/F379 PLL Run and Sleep mode currents PLL Run 40 40 PLL Run 24 30 Icc[mA] 20 PLL Sleep 40 10 PLL Sleep 24 0 -60 -40 -20 0 IN 20 40 AR 60 80 100 120 Ta [˚C] 5 Main Run 3 RC Run 2M 2 PLL Timer 48 Main Sleep 1 RC Sleep 2M 0 -60 -40 -20 0 20 40 60 80 100 120 PR Ta [˚C] FME-MB96370 rev 5 EL 4 Icc[mA] IM MB96F378/F379 operation modes with medium currents Y 111 MB96370 Series MB96F378/F379 Low power mode currents 1 0.1 RC Run 100k Main Timer Sub Run Icc[mA] RC Timer 2M 0.01 RC Timer 100k Stop 1.8V Stop 1.2V 0.001 -60 -40 -20 0 20 IN 40 60 AR 80 100 120 Sub Sleep RC Sleep 100k Sub Timer Ta [˚C] 112 PR EL FME-MB96370 rev 5 IM Y MB96370 Series 2. Frequency dependency of power supply currents in PLL Run mode The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different frequencies and Flash timing settings. Measurement conditions: • VCC = AVCC = 5.0V • Ta = 25˚C • fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram • fCLKS2 = fCLKS1 • fCLKP1 = fCLKB • fCLKP2 = fCLKB/2 • Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram • Main clock = 4MHz external clock • Flash memory timing settings: • MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB) • MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB) • MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB) • MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB) • Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit): • 0 Flash wait states: 0.5 • 1 Flash wait states: 0.33 • 2 Flash wait states: 0.25 MB96F378/F379 PLL Run mode currents 45 IM EL PR 0 Flash wait states (CLKS1=2*CLKB, 1.8V) 1 Flash wait state (CLKS1=CLKB, 1.8V) IN 20 CLKB/CLKP1 (MHz) AR 24 28 40 35 30 Y 1 Flash wait state (CLKS1=2*CLKB, 1.9V) 1 Flash wait state (CLKS1=2*CLKB, 1.8V) 2 Flash wait states (CLKS1=CLKB, 1.9V) ICCPLL (mA) 25 2 Flash wait states (CLKS1=CLKB, 1.8V) 20 15 10 : Specified in "DC characteristics" 5 0 0 4 8 12 16 32 36 40 FME-MB96370 rev 5 113 MB96370 Series ■ PACKAGE DIMENSION MB96(F)37x LQFP 144P 144-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 20.0 × 20.0 mm Gullwing Plastic mold AR Code (Reference) 0.145±0.055 (.006±.002) 0.08(.003) 1.50 –0.10 .059 –.004 +0.20 +.008 Y 0˚~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 1.70 mm MAX 1.20g (FPT-144P-M08) P-LFQFP144-20×20-0.50 144-pin plastic LQFP (FPT-144P-M08) 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 73 109 EL PR INDEX 144 37 IM 72 M IN "A" 36 Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Details of "A" part (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) LEAD No. 1 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) ©2003-2008 FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7 C 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 114 FME-MB96370 rev 5 MB96370 Series 144-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method 0.40 mm 16.0 × 16.0 mm Gullwing Plastic mold 1.70 mm MAX 0.88 g P-LFQFP144-16×16-0.40 Mounting height (FPT-144P-M12) 144-pin plastic LQFP (FPT-144P-M12) 18.00±0.20(.709±.008)SQ +0.40 +.016 *16.00 –0.10 .630 –.004 SQ 108 109 EL 37 IM 73 72 IN "A" 36 AR Weight Code (Reference) 0.08(.003) 0~8˚ Note 1) * : These dimensions include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Y Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 144 PR INDEX LEAD No. 1 0.60±0.15 (.024±.006) 0.07(.003) M 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) 0.40(.016) 0.18±0.035 .007±.001 0.145 –0.03 .006 +0.05 +.002 –.001 ©2003-2008 FUJITSU MICROELECTRONICS LIMITED F144024S-c-3-4 C 2003 FUJITSU LIMITED F144024S-c-3-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ FME-MB96370 rev 5 115 MB96370 Series ■ ORDERING INFORMATION Persistant Low Voltage Reset Yes No Yes No No No No No Yes No Yes No No 416 pin Plastic BGA (BGA-416P-M02) 144 Pin Plastic LQFP FPT-144P-M12 Yes 144 Pin Plastic LQFP FPT-144P-M08 Part number MB96F378TSB PMC-GSE2 *1 MB96F378HSB PMC-GSE2 MB96F378TWB PMC-GSE2 *1 *1 Flash/ROM Subclock Package No Yes Flash A (544KB) Flash B (32KB) No Yes No MB96F378HWB PMC-GSE2 *1 MB96F378TSB PMC1-GSE2 *1 MB96F378HSB PMC1-GSE2 MB96F378TWB PMC1-GSE2 MB96F379YSB PMC-GSE2 *1 MB96F379RSB PMC-GSE2 *1 *1 *1 *1 MB96F378HWB PMC1-GSE2 *1 AR Yes Yes Yes No MB96F379YWB PMC-GSE2 MB96F379RWB PMC-GSE2 *1 MB96F379YSB PMC1-GSE2 *1 MB96F379RSB PMC1-GSE2 *1 *1 Flash A (544KB) Flash B (288kB) MB96F379RWB PMC1-GSE2 *1 MB96V300CRB-ES (for evaluation) Emulated by ext. RAM 116 PR EL *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. IM MB96F379YWB PMC1-GSE2 IN Yes Yes Yes Y 144 Pin Plastic LQFP FPT-144P-M12 144 Pin Plastic LQFP FPT-144P-M08 FME-MB96370 rev 5 MB96370 Series This datasheet is also valid for the following outdated devices: MB96F378TSA, MB96F378HSA, MB96F378TWA, MB96F378HWA, MB96F379YSA, MB96F379RSA, MB96F379YWA, MB96F379RWA FME-MB96370 rev 5 PR EL IM IN AR 117 Y MB96370 Series ■ REVISION HISTORY Revision Prelim 1 Prelim 2 Date 2007-11-27 2007-12-19 Creation Modification 118 PR EL FME-MB96370 rev 5 IM IN AR Prelim 3 2008-04-14 • • • • • • • • • • • • • • • • Added note for devices under development Maximum CPU frequency corrected to 40MHz Product lineup: Product options added, reload timer for PPG added Block diagram: Flash B added, CKOT*_R added, IN*_R added Pin assignment: CKOT0_R added Pin function description corrected (all existing pin types included) Pin circuit types: Description improved Memory map: common 16FX memory map included External bus and RAM start/end addressed specified more precise Flash sector addresses: Start/end addresses corrected Serial programming interface: Note about handshaking pins improved I/O map newly generated (naming style update) Permitted power dissipation specified Ordering information updated Disclaimer added ICC spec corrected (wrong conditions were specified). However specification is still preliminary, especially regarding the leakage current. Y Add TTG3/TTG7 in pin assignment Some IO circuit drawings have been modified. Modification of the memory map and IO map Block diagram includes now the relocated pins Main Flash becomes Flash memory A, Satellite Flash becomes Flash memory B MB96370 Series Revision Prelim 4 Date 2009-01-09 Modification • Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes and official notes and disclaimer added) • specified AD converter channel offset to 4LSB • package code of MB96V300 corrected in ordering information • Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm, Max 50kOhm -> 65kOhm • Added voltage condition to pull-up resistance and LCD divide resistance spec • Lineup: Term “Data Flash” replaced by “independent 32KB Flash” • Ordering information: column “Satellite Flash” replaced by new column “Flash/ ROM”, column “Remarks” removed • Official package dimension drawing with additional notes added • Empty pages removed • DC values adjusted after evaluation (higher Run and Sleep mode currents, smaller standby current at high temp) • Alarm comparator: Power supply current max values increased, comparison time reduced, mode transition time and power-up stabilization time newly added • Handling devices: Notes added about Serial communication and about using ceramic resonators. • Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor • AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz • VOL3 spec improved: spec valid for 3mA load for full Vcc range • C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted FME-MB96370 rev 5 PR EL IM IN AR Y 119 MB96370 Series Revision Prelim 5 Date 2010-06-14 Modification • AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg • Note added that PLL phase jitter spec does not include jitter coming from Main clock • Alarm comparator: Maximum power-up stabilization time increased to 10ms • Note added in DC characteristics how to select driving strength of ports • I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and Condition removed • I/O Circuit type: Note added for type “N” (slew rate control according to I2C spec) • Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new spec items in PLL Run/Sleep mode, small adjustment of most other values) • Prepared Example characteristics • Package dimension: Added the following sentence under the figure: “Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/” • AD converter: Impact of input pin capacitance and external capacitance added to formula for calculation of the sampling time • Added specification of RC clock stabilization time • Ordering information updated: MB96F378/F379**A -> MB96F378/F379**B • Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’ • Feature description PPG: ‘Reload timer overflow as clock input’ corrected to ‘Reload timer underflow as clock input’ • Company name updated on the cover page: Fujitsu Microelectronics Limited -> Fujitsu Semiconductro Limited 120 PR EL FME-MB96370 rev 5 IM IN AR Y MB96370 Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department FME-MB96370 rev 5 PR EL IM IN FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ AR Y 121