GS9060-CFE3

GS9060 HD-LINX® II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver GS9060 Data Sheet Key Features • • • • • • • • • SMPTE 259M-C compliant descrambling and NRZI → NRZ decoding (with bypass) DVB-ASI sync word detection and 8b/10b decoding serial loop-through cable driver output selectable as reclocked or non-reclocked dual serial digital input buffers with 2 x 1 mux integrated serial digital signal termination integrated reclocker descrambler bypass option adjustable loop bandwidth user selectable additional processing features including: • • • • • • • • • • • • • TRS, ANC data checksum and EDH CRC error detection and correction programmable ANC data detection illegal code remapping received solution can be realized for SD-SDI and DVB-ASI applications. In addition to reclocking an deserializing the input data stream, the GS9060 performs NRZI-to-NRZ decoding, descrambling as per SMPTE 259M-C, and word alignment when operating in SMPTE mode. When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream. Two serial digital input buffers are provided with a 2x1 multiplexer to allow the device to select from one of two serial digital input signals. The integrated reclocker features a very wide Input Jitter Tolerance of ±0.3 UI (total 0.6 UI), a rapid asynchronous lock time, and full compliance with DVB-ASI data streams. An integrated cable driver is provided for serial input loop-through applications and can be selected to output either buffered or reclocked data. This cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing. The GS9060 also includes a range of data processing functions such as error detection and correction, automatic standards detection, and EDH support. The device can also detect and extract SMTPTE 352M payload identifier packets and independently identify the received video standard. This information is read from internal registers via the host interface port. TRS errors, EDH CRC errors and ancillary data checksum errors can all be detected. A single ‘DATA_ERROR’ pin is provided which is a logical ‘ORing’ of all detectable errors. Individual error status is stored in internal ‘ERROR_STATUS’ registers. Finally the device can correct detected errors and insert new TRS ID words, ancillary data checksum words, and EDH CRC words. Illegal code re-mapping is also available. All processing functions may be individually enabled or disabled via the host interface control. The GS9060 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS compliant). *For new designs use GO1555 internal flywheel for noise immune H, V, F extraction FIFO load Pulse 20-bit / 10-bit CMOS parallel output data bus 27MHz / 13.5MHz parallel digital output automatic standards detection and indication Pb-free and RoHS compliant 1.8V core power supply and 3.3V charge pump power supply 3.3V digital I/O supply JTAG test interface small footprint compatible with GS1560A, GS1561, GS1532, and GS9062 Applications • • SMPTE 259M-C Serial Digital Interfaces DVB-ASI Serial Digital Interfaces Description The GS9060 is a reclocking deserializer with a serial loop-through cable driver. When used in conjunction with any Gennum cable equalizer and the GO1555/GO1525* Voltage Controlled Oscillator, a 22208 - 8 January 2007 1 of 61 www.gennum.com GS9060 Data Sheet Functional Block Diagram IOPROC_EN/DIS SMPTE_BYPASS CP_CAP VCO VCO LB_CONT LF VCO_VCC VCO_GND FW_EN/DIS 20bit/10bit DVB_ASI LOCKED RC_BYP IP_SEL PCLK H V F CD1 CD2 carrier_detect rclk_ctrl pll_lock LOCK detect TERM 1 DDI_1 DDI_1 Reclocker TERM 2 DDI_2 DDI_2 S->P smpte_sync_det asi_sync_det SMPTE Descramble, Word alignment and flywheel TRS correct CSUM correct EDH check & correct Illegal code remap DATA_ERROR K28.5 sync detect, DVB-ASI word alignment and 8b/10b decode (o/p mute) pll_lock rclk_bypass TRS check CSUM check ANC data detection DOUT[19:0] I/O Buffer & mux FIFO_LD CANC YANC SDO_EN/DIS SDO SDO Reset RSET HOST Interface / JTAG test GS9060 Functional Block Diagram RESET_TRST CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG/HOST 22208 - 8 January 2007 2 of 61 GS9060 Data Sheet Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 Functional Block Diagram .............................................................................................2 1. Pin Out .....................................................................................................................5 1.1 Pin Assignment ...............................................................................................5 1.2 Pin Descriptions ..............................................................................................6 2. Electrical Characteristics ........................................................................................14 2.1 Absolute Maximum Ratings ..........................................................................14 2.2 DC Electrical Characteristics ........................................................................14 2.3 AC Electrical Characteristics.........................................................................16 2.4 Solder Reflow Profiles...................................................................................18 2.5 Input/Output Circuits .....................................................................................19 2.6 Host Interface Map........................................................................................21 2.6.1 Host Interface Map (R/W registers) ...................................................22 2.6.2 Host Interface Map (Read only registers) ..........................................23 3. Detailed Description ...............................................................................................24 3.1 Functional Overview .....................................................................................24 3.2 Serial Digital Input .........................................................................................24 3.2.1 Input Signal Selection .........................................................................24 3.2.2 Carrier Detect Input ............................................................................25 3.2.3 Single Input Configuration ..................................................................25 3.3 Serial Digital Reclocker .................................................................................25 3.3.1 External VCO......................................................................................26 3.3.2 Loop Bandwidth ..................................................................................26 3.4 Serial Digital Loop-Through Output ..............................................................26 3.4.1 Output Swing ......................................................................................26 3.4.2 Reclocker Bypass Control ..................................................................27 3.4.3 Serial Digital Output Mute...................................................................27 3.5 Serial-To-Parallel Conversion .......................................................................28 3.6 Lock Detect ...................................................................................................28 3.6.1 Input Control Signals ..........................................................................29 3.7 SMPTE Functionality ....................................................................................30 3.7.1 SMPTE Descrambling and Word Alignment .......................................30 3.7.2 Internal Flywheel.................................................................................30 3.7.3 Switch Line Lock Handling..................................................................31 3.7.4 HVF Timing Signal Generation ...........................................................33 3.8 DVB-ASI Functionality ..................................................................................34 3.8.1 Transport Packet Format ....................................................................35 3.8.2 DVB-ASI 8b/10b Decoding and Word Alignment................................35 22208 - 8 January 2007 3 of 61 GS9060 Data Sheet 3.8.3 Status Signal Outputs .........................................................................35 3.9 Data Through Mode ......................................................................................36 3.10 Additional Processing Functions.................................................................36 3.10.1 FIFO Load Pulse...............................................................................36 3.10.2 Ancillary Data Detection and Indication ............................................37 3.10.3 SMPTE 352M Payload Identifier.......................................................39 3.10.4 Automatic Video Standard and Data Format Detection ....................39 3.10.5 Error Detection and Indication ..........................................................42 3.10.6 Error Correction and Insertion ..........................................................46 3.10.7 EDH Flag Detection ..........................................................................48 3.11 Parallel Data Outputs ..................................................................................49 3.11.1 Parallel Data Bus Buffers..................................................................49 3.11.2 Parallel Output in SMPTE Mode .......................................................50 3.11.3 Parallel Output in DVB-ASI Mode.....................................................50 3.11.4 Parallel Output in Data-Through Mode .............................................50 3.11.5 Parallel Output Clock (PCLK) ...........................................................51 3.12 GSPI Host Interface ....................................................................................51 3.12.1 Command Word Description.............................................................52 3.12.2 Data Read and Write Timing ............................................................52 3.12.3 Configuration and Status Registers ..................................................53 3.13 JTAG...........................................................................................................54 3.14 Device Power Up ........................................................................................55 3.15 Device Reset...............................................................................................55 4. Application Reference Design ................................................................................56 4.1 Typical Application Circuit (Part A) ...............................................................56 4.2 Typical Application Circuit (Part B) ...............................................................57 5. References & Relevant Standards.........................................................................58 6. Package & Ordering Information............................................................................59 6.1 Package Dimensions ....................................................................................59 6.2 Packaging Data.............................................................................................60 6.3 Ordering Information .....................................................................................60 7. Revision History .....................................................................................................61 22208 - 8 January 2007 4 of 61 GS9060 Data Sheet 1. Pin Out 1.1 Pin Assignment DOUT11 DOUT17 DOUT16 DOUT14 DOUT13 DOUT15 DOUT12 DOUT10 IO_GND IO_GND IO_VDD IO_VDD 41 40 39 38 37 36 35 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 43 DOUT2 42 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 IO_VDD DOUT18 DOUT19 CORE_VDD YANC CANC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO_GND DOUT1 DOUT0 CORE_VDD H V F CORE_GND FIFO_LD DATA_ERROR FW_EN/DIS CORE_GND PCLK RC_BYP NC 9060 34 33 32 31 30 29 28 27 26 25 24 23 22 21 SCLK_TCK SDIN_TDI SDOUT_TDO CS_TMS JTAG/HOST RESET_TRST SDO SDO CD_GND SDO_EN/DIS LOCKED VCO VCO VCO_GND VCO_VCC LF CP_CAP LB_CONT CP_GND SMPTE_BYPASS PDBUFF_GND 20bit/10bit DVB_ASI 22208 - 8 January 2007 IOPROC_EN/DIS CP_VDD PD_VDD BUFF_VDD CD_VDD DDI1 CD1 TERM1 DDI1 TERM2 DDI2 IP_SEL RSET CD2 DDI2 NC 5 of 61 GS9060 Data Sheet 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1 2 3 4 5 Name CP_VDD PDBUFF_GND PD_VDD BUFF_VDD CD1 Timing – – – – Non Synchronous Type Power Power Power Power Input Description Power supply connection for the charge pump. Connect to +3.3V DC analog. Ground connection for the phase detector and serial digital input buffers. Connect to analog GND. Power supply connection for the phase detector. Connect to +1.8V DC analog. Power supply connection for the serial digital input buffers. Connect to +1.8V DC analog. STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI1 and DDI1 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid. In this case, the LOCKED signal is set LOW and all parallel outputs are muted. 6,8 7 9 DDI1, DDI1 TERM1 DVB_ASI Analog Analog Non Synchronous Input Input Input Differential input pair for serial digital input 1. Termination for serial digital input 1. AC couple to PDBUFF_GND. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the decoding or word alignment of received DVB-ASI data. 10 IP_SEL Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal, and CD1 or CD2 as the carrier detect input signal. When set HIGH, DDI1 / DDI1 is selected as the serial digital input and CD1 is selected as the carrier detect input signal. When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect input signal is selected. 11 12 NC 20bit/10bit – Non Synchronous – Input No Connect. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the output data bus width in SMPTE or Data-Through modes. This signal is ignored in DVB-ASI mode. When set HIGH, the parallel output will be 20-bit demultiplexed data. When set LOW, the parallel outputs will be 10-bit multiplexed data. 22208 - 8 January 2007 6 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 13 Name IOPROC_EN/DIS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • EDH CRC Error Correction • ANC Data Checksum Correction • TRS Error Correction • Illegal Code Remapping To enable a subset of these features, keep IOPROC_EN/DIS HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accesible via the host interface. When set LOW, the I/O processing features of the device are disabled, regardless of whether the features are enabled in the IOPROC_DISABLE register. 14 CD2 Non Synchronous Input STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI2 and DDI2 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid. In this case, the LOCKED signal is set LOW and all parallel outputs are muted. 15,17 16 18 DDI_2, DDI_2 TERM2 SMPTE_BYPASS Analog Analog Non Synchronous Input Input Input Differential input pair for serial digital input 2. Termination for serial digital input 2. AC couple to PDBUFF_GND. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When set LOW, the device will not support the descrambling, decoding or word alignment of received SMPTE data. No I/O processing features will be available. 19 RSET Analog Input Used to set the serial digital loop-through output signal amplitude. Connect to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended output swing. Power supply connection for the serial digital cable driver. Connect to +1.8V DC analog. 20 CD_VDD – Power 22208 - 8 January 2007 7 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 21 Name SDO_EN/DIS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the serial digital output loop-through stage. When set LOW, the serial digital output signals SDO and SDO are disabled and become high impedance. When set HIGH, the serial digital output signals SDO and SDO are enabled. 22 23, 24 CD_GND SDO, SDO – Analog Power Output Ground connection for the serial digital cable driver. Connect to analog GND. Serial digital loop-through output signal operating at 270Mb/s. The slew rate of these outputs is automatically controlled to meet SMPTE 259M specifications. 25 RESET_TRST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to reset the internal operating conditions to default settings and to reset the JTAG test sequence. Host Mode (JTAG/HOST = LOW) When asserted LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs SDO and SDO. Must be set HIGH for normal device operation. JTAG Test Mode (JTAG/HOST = HIGH) When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. 26 JTAG/HOST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured as GSPI pins for normal host interface operation. 27 CS_TMS Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Chip Select / Test Mode Select Host Mode (JTAG/HOST = LOW) CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH) CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. NOTE: If the host interface is not being used, tie this pin HIGH. 22208 - 8 January 2007 8 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 28 Name SDOUT_TDO Timing Synchronous with SCLK_TCK Type Output Description CONTROL SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG/HOST = LOW) SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) SDOUT_TDO operates as the JTAG test data output, TDO. 29 SDIN_TDI Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data In / Test Data Input Host Mode (JTAG/HOST = LOW) SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) SDIN_TDI operates as the JTAG test data input, TDI. NOTE: If the host interface is not being used, tie this pin HIGH. 30 SCLK_TCK Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Clock / Test Clock. Host Mode (JTAG/HOST = LOW) SCLK_TCK operates as the host interface burst clock, SCLK. Command and data read/write words are clocked into the device synchronously with this clock. JTAG Test Mode (JTAG/HOST = HIGH) SCLK_TCK operates as the JTAG test clock, TCK. NOTE: If the host interface is not being used, tie this pin HIGH. 31 DATA_ERROR Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. The DATA_ERROR signal will be LOW when an error within the received data stream has been detected by the device. This pin is a logical 'OR'ing of all detectable errors listed in the internal ERROR_STATUS register. Once an error is detected, DATA_ERROR will remain LOW until the start of the next video frame / field, or until the ERROR_STATUS register is read via the host interface. The DATA_ERROR signal will be HIGH when the received data stream has been detected without error. NOTE: It is possible to program which error conditions are monitored by the device by setting appropriate bits of the ERROR_MASK register HIGH. All error conditions are detected by default. 32 FIFO_LD Synchronous with PCLK Output CONTROL SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used as a control signal for external FIFO(s). Normally HIGH but will go LOW for one PCLK period at SAV. 22208 - 8 January 2007 9 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 33, 68 34 Name CORE_GND F Timing – Synchronous with PCLK Type Power Output Description Ground connection for the digital core logic. Connect to digital GND. STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the ODD / EVEN field of the video signal. The F signal will be HIGH for the entire period of field 2 as indicated by the F bit in the received TRS signals. The F signal will be LOW for all lines in field 1 and for all lines in progressive scan systems. 35 V Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video field / frame that is used for vertical blanking. The V signal will be HIGH for the entire vertical blanking period as indicated by the V bit in the received TRS signals. The V signal will be LOW for all lines outside of the vertical blanking interval. 36 H Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video line containing active video data. H signal timing is configurable via the H_CONFIG bit of the IOPROC_DISABLE register accessible via the host interface. Active Line Blanking (H_CONFIG = 0h) The H signal will be HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting. TRS Based Blanking (H_CONFIG = 1h) The H signal will be HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. 37, 64 38, 39, 42– 48, 50 CORE_VDD DOUT[0:9] – Synchronous with PCLK Power Output Power supply connection for the digital core logic. Connect to +1.8V DC digital. PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DOUT9 is the MSB and DOUT0 is the LSB. 20-bit mode 20bit/10bit = HIGH Chroma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW Forced LOW in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 10-bit mode 20bit/10bit = LOW Forced LOW in all modes. 22208 - 8 January 2007 10 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 40, 49, 60 41, 53, 61 Name IO_GND IO_VDD Timing – – Type Power Power Description Ground connection for digital I/O buffers. Connect to digital GND. Power supply connection for digital I/O buffers. Connect to +3.3V DC digital. 51, 52, 54– 59, 62, 63 DOUT[10:19] Synchronous with PCLK Output PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DOUT19 is the MSB and DOUT10 is the LSB. 20-bit mode 20bit/10bit = HIGH Luma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 10-bit mode 20bit/10bit = LOW Multiplexed Luma and Chroma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in data through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 65 YANC Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of ancillary data in the video stream. For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal will be HIGH when VANC or HANC data is detected in the luma video stream and LOW otherwise. For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will be HIGH when VANC or HANC data is detected anywhere in the data stream and LOW otherwise. 66 CANC Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of ancillary data in the video stream. For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal will be HIGH when VANC or HANC data is detected in the chroma video stream and LOW otherwise. For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will be HIGH when VANC or HANC data is detected anywhere in the data stream and LOW otherwise. 22208 - 8 January 2007 11 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 67 Name FW_EN/DIS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the noise immune flywheel of the device. When set HIGH, the internal flywheel is enabled. This flywheel is used in the extraction and generation of TRS timing signals, in automatic video standards detection, and in manual switch line lock handling. When set LOW, the internal flywheel is disabled and TRS correction and insertion is unavailable. 69 PCLK – Output PARALLEL DATA BUS CLOCK Signal levels are LVCMOS/LVTTL compatible. 20-bit mode 10-bit mode PCLK = 13.5MHz PCLK = 27MHz 70 RC_BYP Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH, the serial digital output will be a reclocked version of the input signal regardless of whether the device is in SMPTE, DVB-ASI or Data-Through mode. When set LOW, the serial digital output will be a buffered version of the input signal in all modes. 71 72 NC LOCKED – Synchronous with PCLK – Output No connect. STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. The LOCKED signal will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode. It will be LOW otherwise. 73, 74 VCO, VCO Analog Input Differential inputs for the external VCO reference signal. For single ended devices such as the GO1555/GO1525*, VCO should be AC coupled to VCO_GND. *For new designs use GO1555 75 VCO_GND – Output Power Ground reference for the external voltage controlled oscillator. Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other grounds. *For new designs use GO1555 22208 - 8 January 2007 12 of 61 GS9060 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 76 Name VCO_VCC Timing – Type Output Power Description Power supply for the external voltage controlled oscillator. Connect to pin 5 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other power supplies. *For new designs use GO1555 77 78 79 80 LF CP_CAP LB_CONT CP_GND Analog Analog Analog – Output Input Input Power Control voltage to external voltage controlled oscillator. Nominally +1.25V DC. PLL lock time constant capacitor connection. Normally connected to VCO_GND through 2.2nF. Control voltage to set the loop bandwidth of the integrated reclocker. Normally connected to VCO_GND through 40kΩ. Ground connection for the charge pump. Connect to analog GND. 22208 - 8 January 2007 13 of 61 GS9060 Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Core Supply Voltage I/O Input Voltage Range (any input) Ambient Operating Temperature Storage Temperature Lead Temperature (soldering, 10 sec) ESD Protection On All Pins NOTES: 1. See reflow solder profiles (Section 2.4 on page 18) 2. MIL STD 883 ESD protection applied to all pins on the device. Value/Units -0.3V to +2.1V -0.3V to +4.6V -2.0V to + 5.25V -20°C < TA < 85°C -40°C < TSTG < 125°C 230°C 1kV 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units Test Levels Notes System Operation Temperature Range Digital Core Supply Voltage Digital I/O Supply Voltage Charge Pump Supply Voltage Phase Detector Supply Voltage Input Buffer Supply Voltage Cable Driver Supply Voltage External VCO Supply Voltage Output +1.8V Supply Current +3.3V Supply Current Total Device Power TA CORE_VDD IO_VDD CP_VDD PD_VDD BUFF_VDD CD_VDD VCO_VCC I1V8 I3V3 PD – – – – – – – – – – – 0 1.65 3.0 3.0 1.65 1.65 1.71 2.25 – – – – 1.8 3.3 3.3 1.8 1.8 1.8 2.50 – – – 70 1.95 3.6 3.6 1.95 1.95 1.89 2.75 245 55 625 °C V V V V V V V mA mA mW – 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 – 4 – 4 22208 - 8 January 2007 14 of 61 GS9060 Data Sheet Table 2-1: DC Electrical Characteristics (Continued) TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units Test Levels Notes Digital I/O Input Logic LOW Input Logic HIGH Output Logic LOW Output Logic HIGH VIL VIH VOL VOH – – 8mA 8mA – 2.1 – IO_VDD - 0.4 – – 0.2 – 0.8 – 0.4 – V V V V 1 1 1 1 – – – – Input Input Bias Voltage RSET Voltage VB VRSET – RSET=281Ω – 0.54 1.45 0.6 – 0.66 V V 6 1 2 3 Output Output Common Mode Voltage TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. VCMOUT 75Ω load, RSET=281Ω 0.8 NOTES 1. 2. 3. 4. All DC and AC electrical parameters within specification. Input common mode is set by internal biasing resistors. Set by the value of the RSET resistor. Loop-through enabled. 1.0 1.2 V 1 – 22208 - 8 January 2007 15 of 61 GS9060 Data Sheet 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics TA = 0°C to 70°C, unless otherwise shown Parameter System Serial Digital Input Jitter Tolerance Slave Mode Asynchronous Lock Time Device Latency Symbol Conditions Min Typ Max Units Test Levels Notes IJT Nominal loop bandwidth No data to SD No data to DVB-ASI SMPTE and Data-Through modes DVB-ASI mode 0.6 – – – – 1 – – – 21 11 – – 197 68 – – – UI us us PCLK PCLK ms 1 6,7 6,7 6 6 7 1 2 2 – – 6 Reset Pulse Width treset – Serial Digital Differential Input Serial Input Data Rate Serial Digital Input Signal Swing DRDDI ∆VDDI – Differential with internal 100Ω input termination – 200 270 600 – 1000 Mb/s mVp-p 1 1 – – Serial Digital Output Serial Output Data Rate Serial Output Swing Serial Output Rise Time 20% ~ 80% Serial Output Fall Time 20% ~ 80% Serial Output Intrinsic Jitter Serial Output Duty Cycle Distortion DRSDO ∆VSDO trSDO – RSET = 281Ω Load = 75Ω ORL compensation using recommended circuit ORL compensation using recommended circuit Pseudorandom and pathological – – – 400 270 800 550 – – 1500 Mb/s mVp-p ps 1 1 1 – – – tfSDO 400 550 1500 ps 1 – tIJ DCDSDO – – 270 20 350 – ps ps 1 6,7 3 4 Parallel Output Parallel Clock Frequency Parallel Clock Duty Cycle Output Data Hold Time Output Data Delay Time Output Data Rise/Fall Time fPCLK DCPCLK tOH tOD tr/tf – – – – – 13.5 40 19.5 – – – 50 – – – 27.0 60 – 22.8 1.5 MHz % ns ns ns 1 1 1 1 6,7 5 5 5 22208 - 8 January 2007 16 of 61 GS9060 Data Sheet Table 2-2: AC Electrical Characteristics (Continued) TA = 0°C to 70°C, unless otherwise shown Parameter GSPI GSPI Input Clock Frequency GSPI Input Clock Duty Cycle GSPI Input Data Setup Time GSPI Input Data Hold Time GSPI Output Data Hold Time GSPI Output Data Delay Time TEST LEVELS Symbol Conditions Min Typ Max Units Test Levels Notes fSCLK DCSCLK – – – – – – – 40 0 1.43 2.10 – NOTES 1. 2. 3. 4. – 50 – – – – 6.6 60 – – – 7.27 MHz % ns ns ns ns 1 6,7 6,7 6,7 6,7 6,7 – – – – – – 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 6MHz sine wave modulation. SD = 525i Serial Digital Output Reclocked (RC_BYP = HIGH). Serial Duty Cycle Distortion is defined here to be the difference between the width of a ‘1’ bit, and the width of a ‘0’ bit. 5. With 15pF load. 6. See Section 3.15 on page 55, Figure 3-15. 22208 - 8 January 2007 17 of 61 GS9060 Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. The recommended standard eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-2. Temperature 60-150 sec. 10-20 sec. 230˚C 220˚C 3 ˚C/sec max 183˚C 6˚C/sec max 150˚C 100˚C 25˚C Time 120 sec. max 6 min. max Figure 2-1: Standard Eutectic Solder Reflow Profile Temperature 60-150 sec. 20-40 sec. 2 60˚C 2 50˚C 3 ˚C/sec max 2 17˚C 6˚C/sec max 2 00˚C 1 50˚C 25˚C Tim e 60-180 sec. max 8 min. max Figure 2-2: Maximum Pb-free Solder Reflow Profile (Pb-free package) 22208 - 8 January 2007 18 of 61 GS9060 Data Sheet 2.5 Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. DDI VDD 50 45K TERM 150K 50 DDI Figure 2-3: Serial Digital Input VCO VDD 25 1.5K 5K 25 VCO Figure 2-4: VCO Input LB_CONT 865mV 7.2K Figure 2-5: PLL Loop Bandwidth Control 22208 - 8 January 2007 19 of 61 GS9060 Data Sheet SDO SDO Figure 2-6: Serial Digital Output LF CP_CAP 300 Figure 2-7: VCO Control Output & PLL Lock Time Capacitor 22208 - 8 January 2007 20 of 61 GS9060 Data Sheet 2.6 Host Interface Map 15 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used VFO4-b7 VFO2-b7 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used VFO4-b6 VFO2-b6 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used VFO4-b5 VFO2-b5 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used VFO4-b4 VFO2-b4 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b11 b11 VFO4-b3 VFO2-b3 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b10 b10 b10 b10 VFO4-b2 VFO2-b2 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 VFO4-b1 VFO2-b1 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 VFO4-b0 VFO2-b0 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 VFO3-b7 VFO1-b7 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 VFO3-b6 VFO1-b6 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 VFO3-b5 VFO1-b5 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 VFO3-b4 VFO1-b4 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 VFO3-b3 VFO1-b3 Not Used Not Used Not Used Not Used VD_STD_ ERR_MASK FF_CRC_ ERR_MASK AP_CRC_ ERR_MASK LOCK_ ERR_MASK Not Used CS_ERR_ MASK Not Used Not Used Not Used b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 VFO3-b2 VFO1-b2 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SAV_ERR_ MASK b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 VFO3-b1 VFO1-b1 0 EAV_ERR_ MASK b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 VFO3-b0 VFO1-b0 REGISTER NAME ERROR_MASK ADDRES S 1Ah FF_LINE_END_F1 FF_LINE_START_F1 FF_LINE_END_F0 FF_LINE_START_F0 AP_LINE_END_F1 AP_LINE_START_F1 AP_LINE_END_F0 AP_LINE_START_F0 RASTER_STRUCTURE4 RASTER_STRUCTURE3 RASTER_STRUCTURE2 RASTER_STRUCTURE1 VIDEO_FORMAT_OUT_B VIDEO_FORMAT_OUT_A ANC_TYPE5 ANC_TYPE4 ANC_TYPE3 ANC_TYPE2 ANC_TYPE1 VIDEO_STANDARD Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used VD_STD_ERR Not Used FF_CRC_ERR Not Used ANC-UES ANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UES FF-IDH LOCK_ERR Not Used 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h b15 b15 b15 b15 b15 Not Used b14 b14 b14 b14 b14 VDS-b4 b13 b13 b13 b13 b13 VDS-b3 b12 b12 b12 b12 b12 VDS-b2 b11 b11 b11 b11 b11 VDS-b1 b10 b10 b10 b10 b10 VDS-b0 b9 b9 b9 b9 b9 INT_PROG b7 b7 b7 b7 b7 Not Used b6 b6 b6 b6 b6 Not Used FF-EDA Not Used Not Used b5 b5 b5 b5 b5 Not Used FF-EDH CS_ERR ILLEGAL_ REMAP b4 b4 b4 b4 b4 Not Used AP-UES Not Used EDH_CRC_ INS b3 b3 b3 b3 b3 DF-b3 AP-IDA Not Used ANC_CSUM_ INS b8 b8 b8 b8 b8 STD_ LOCK FF-IDA AP_CRC_ERR H_CONFIG b2 b2 b2 b2 b2 DF-b2 AP-IDH Not Used Not Used b1 b1 b1 b1 b1 DF-b1 AP-EDA SAV_ERR Not Used b0 b0 b0 b0 b0 DF-b0 AP-EDH EAV_ERR TRS_INS EDH_FLAG ERROR_STATUS IOPROC_DISABLE 03h 02h 01h 00h 22208 - 8 January 2007 21 of 61 GS9060 Data Sheet 2.6.1 Host Interface Map (R/W registers) 15 14 13 12 11 10 VD_STD_ ERR_MASK b6 b6 b6 b6 b6 b6 b6 b6 b5 b5 b5 b5 b5 b5 b5 b5 b4 b4 b4 b4 b4 b4 b4 b4 b3 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 6 Not Used 5 CS_ERR_ MASK 4 Not Used 3 Not Used 2 Not Used 1 SAV_ERR_ MASK b1 b1 b1 b1 b1 b1 b1 b1 0 EAV_ERR_ MASK b0 b0 b0 b0 b0 b0 b0 b0 REGISTER NAME ERROR_MASK ADDRESS 1Ah FF_LINE_END_F1 FF_LINE_START_F1 FF_LINE_END_F0 FF_LINE_START_F0 AP_LINE_END_F1 AP_LINE_START_F1 AP_LINE_END_F0 AP_LINE_START_F0 9 FF_CRC_ ERR_MASK b9 b9 b9 b9 b9 b9 b9 b9 8 AP_CRC_ ERR_MASK b8 b8 b8 b8 b8 b8 b8 b8 7 LOCK_ ERR_MASK b7 b7 b7 b7 b7 b7 b7 b7 ANC_TYPE5 ANC_TYPE4 ANC_TYPE3 ANC_TYPE2 ANC_TYPE1 b15 b15 b15 b15 b15 b14 b14 b14 b14 b14 b13 b13 b13 b13 b13 b12 b12 b12 b12 b12 b11 b11 b11 b11 b11 b10 b10 b10 b10 b10 b9 b9 b9 b9 b9 b8 b8 b8 b8 b8 b7 b7 b7 b7 b7 b6 b6 b6 b6 b6 b5 b5 b5 b5 b5 b4 b4 b4 b4 b4 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 IOPROC_DISABLE 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h H_CONFIG ILLEGAL_ REMAP EDH_CRC_ INS ANC_CSUM_ INS TRS_INS 22208 - 8 January 2007 22 of 61 GS9060 Data Sheet 2.6.2 Host Interface Map (Read only registers) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER NAME RASTER_STRUCTURE4 RASTER_STRUCTURE3 RASTER_STRUCTURE2 RASTER_STRUCTURE1 VIDEO_FORMAT_OUT_B VIDEO_FORMAT_OUT_A VFO4-b7 VFO2-b7 VFO4-b6 VFO2-b6 VFO4-b5 VFO2-b5 VFO4-b4 VFO2-b4 b11 b11 VFO4-b3 VFO2-b3 b10 b10 b10 b10 VFO4-b2 VFO2-b2 b9 b9 b9 b9 VFO4-b1 VFO2-b1 b8 b8 b8 b8 VFO4-b0 VFO2-b0 b7 b7 b7 b7 VFO3-b7 VFO1-b7 b6 b6 b6 b6 VFO3-b6 VFO1-b6 b5 b5 b5 b5 VFO3-b5 VFO1-b5 b4 b4 b4 b4 VFO3-b4 VFO1-b4 b3 b3 b3 b3 VFO3-b3 VFO1-b3 b2 b2 b2 b2 VFO3-b2 VFO1-b2 b1 b1 b1 b1 VFO3-b1 VFO1-b1 b0 b0 b0 b0 VFO3-b0 VFO1-b0 VIDEO_STANDARD EDH_FLAG VD_STD_ERR FF_CRC_ERR AP_CRC_ERR VDS-b4 ANC-UES VDS-b3 ANC-IDA VDS-b2 ANC-IDH VDS-b1 ANC-EDA VDS-b0 ANC-EDH INT_PROG FF-UES STD_LOCK FF-IDA FF-IDH LOCK_ERR FF-EDA FF-EDH CS_ERR AP-UES DF-b3 AP-IDA DF-b2 AP-IDH DF-b1 AP-EDA SAV_ERR DF-b0 AP-EDH EAV_ERR ERROR_STATUS ADDRESS 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h 22208 - 8 January 2007 23 of 61 GS9060 Data Sheet 3. Detailed Description 3.1 Functional Overview The GS9060 is a dual-standard reclocking deserializer with an integrated serial digital loop-through output. When used in conjunction with any Gennum cable equalizer and the external GO1555/GO1525* Voltage Controlled Oscillator, a receive solution at 270Mb/s is realized. The application layer must set external device pins for the correct reception of either SMPTE or DVB-ASI data. The GS9060 also supports the reclocking and deserializing of data not conforming to SMPTE or DVB-ASI streams. The provided serial loop-through outputs may be selected as either buffered or reclocked versions of the input signal and feature a high impedance mode, output mute on loss of signal and adjustable signal swing. In the digital signal processing core, several data processing functions are implemented including error detection and correction and automatic video standards detection. These features are all enabled by default, but may be individually disabled via internal registers accessible through the GSPI host interface. Finally, the GS9060 contains a JTAG interface for boundary scan test implementations. *For new designs use GO1555 3.2 Serial Digital Input The GS9060 contains two current mode differential serial digital input buffers, allowing the device to be connected to two SMPTE 259M-C compliant input signals. Both input buffers have internal 50Ω termination resistors which are connected to ground via the TERM1 and TERM2 pins. The input common mode level is set by internal biasing resistors such that the serial digital input signals must be AC coupled into the device. Gennum recommends using a capacitor value of 4.7uF to accommodate pathological signals. The input buffers use a separate power supply of +1.8V DC supplied via the BUFF_VDD and PDBUFF_GND pins. 3.2.1 Input Signal Selection A 2x1 input multiplexer is provided to allow the application layer to select between the two serial digital input streams using a single external pin. When IP_SEL is set HIGH, serial digital input 1 (DDI1 / DDI1) is selected as the input to the GS9060's reclocker stage. When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected. 22208 - 8 January 2007 24 of 61 GS9060 Data Sheet 3.2.2 Carrier Detect Input For each of the differential inputs, an associated carrier detect input signal is included, (CD1 and CD2). These signals are generated by Gennum's family of automatic cable equalizers. When LOW, CDx indicates that a valid serial digital data stream is being delivered to the GS9060 by the equalizer. When HIGH, the serial digital input to the device should be considered invalid. If no equalizer precedes the device, the application layer should set CD1 and CD2 accordingly. NOTE: If the GS9064 Automatic Cable Equalizer is used, the MUTE/CD output signal from that device must be translated to TTL levels before passing to the GS9060 CDx inputs. See Section 4.1 on page 56 for a recommended transistor network that will set the correct voltage levels. A 2x1 input multiplexer is also provided for these signals. The internal carrier_detect signal is determined by the setting of the IP_SEL pin and is used by the lock detect block of the GS9060 to determine the lock status of the device, Section 3.6 on page 28. 3.2.3 Single Input Configuration If the application requires a single differential input, the second set of inputs may be left unconnected. Tie the associated carrier detect pin HIGH, and leave the termination pin unconnected. 3.3 Serial Digital Reclocker The output of the 2x1 serial digital input multiplexer passes to the GS9060's internal reclocker stage. The function of this block is to lock to the input data stream, extract a clean clock, and retime the serial digital data to remove high frequency jitter. The reclocker was designed with a 'hexabang' phase and frequency detector. That is, the PFD used can identify six 'degrees' of phase / frequency misalignment between the input data stream and the clock signal provided by the VCO, and correspondingly signal the charge pump to produce six different control voltages. This results in fast and accurate locking of the PLL to the data stream. If lock is achieved, the reclocker provides an internal pll_lock signal to the lock detect block of the device. 22208 - 8 January 2007 25 of 61 GS9060 Data Sheet 3.3.1 External VCO The GS9060 requires the external GO1555/GO1525* Voltage Controlled Oscillator as part of the reclocker's phase-locked loop. This external VCO implementation was chosen to ensure high quality reclocking. Power for the external VCO is generated entirely by the GS9060 from an integrated voltage regulator. The internal regulator uses +3.3V DC supplied via the CP_VDD / CP_GND pins to provide +2.5V DC on the VCO_VCC / VCO_GND pins. The control voltage to the VCO is output from the GS9060 on the LF pin and requires 4.7kΩ pull-up and pull-down resistors to ensure correct operation. The GO1555/GO1525* produces a reference signal for the reclocker, input on the VCO pin of the GS9060. Both LF and VCO signals should be referenced to the supplied VCO_GND as shown in the recommended application circuit of Section 4.1 on page 56. *For new designs use GO1555 3.3.2 Loop Bandwidth The loop bandwidth of the integrated reclocker is nominally 1.4MHz, but may be increased or decreased via the LB_CONT pin. It is recommended that this pin be connected to VCO_GND through 39.2kΩ to maximize the input jitter tolerance of the device. 3.4 Serial Digital Loop-Through Output The GS9060 contains an integrated current mode differential serial digital cable driver with automatic slew rate control. When enabled, this serial digital output provides an active loop-through of the input signal. To enable the loop-through output, SDO_EN/DIS must be set HIGH by the application layer. Setting the SDO_EN/DIS signal LOW will cause the SDO and SDO output pins to become high impedance, resulting in reduced device power consumption. With suitable external return loss matching circuitry, the GS9060's loop-through outputs will provide a minimum output return loss of -15dB at 270Mb/s. The integrated cable driver uses a separate power supply of +1.8V DC supplied via the CD_VDD and CD_GND pins. 3.4.1 Output Swing Nominally, the voltage swing of the serial digital loop-through output is 800mVp-p single-ended into a 75Ω load. This is set externally by connecting the RSET pin to CD_VDD through 281Ω. The loop-through output swing may be decreased by increasing the value of the RSET resistor. The relationship is approximated by the curve shown in Figure 3-1. 22208 - 8 January 2007 26 of 61 GS9060 Data Sheet Alternatively, the serial digital output can drive 800mVp-p into a 50Ω load. Since the output swing is reduced by a factor of approximately one third when the smaller load is used, the RSET resistor must be 187Ω to obtain 800mVp-p. 1000 900 800 ∆VSDO(mVp-p) 700 600 500 400 300 50Ω load 75Ω load 200 250 300 350 400 450 500 550 600 650 700 RSET(Ω) Figure 3-1: Serial Digital Loop-Through Output Swing 3.4.2 Reclocker Bypass Control The serial digital loop-through output may be either a buffered version of the serial digital input signal, or a reclocked version of that signal. The application layer may choose the reclocked output by setting RC_BYP to logic HIGH. If RC_BYP is set LOW, the data stream will bypass the internal reclocker and the serial digital output will be a buffered version of the input. 3.4.3 Serial Digital Output Mute The GS9060 will automatically mute the serial digital loop-through output when the internal carrier_detect signal indicates an invalid serial input. The loop-through output will also be muted when SDO/SDO is selected as reclocked, (RC_BYP = HIGH), but the lock detect block has failed to lock to the data stream, (LOCKED = LOW). Table 3-1 summarizes the possible states of the serial digital loop-through output data stream. Table 3-1: Serial Digital Loop-Through Output Status SDO RECLOCKED BUFFERED MUTED MUTED CD LOW LOW LOW HIGH Locked HIGH X LOW LOW* RC_BYP HIGH LOW HIGH X *NOTE: LOCKED = HIGH if and only if CD = LOW 22208 - 8 January 2007 27 of 61 GS9060 Data Sheet 3.5 Serial-To-Parallel Conversion The retimed data and phase-locked clock signals from the reclocker are fed to the serial-to-parallel converter. The function of this block is to extract 10-bit data words from the reclocked serial data stream and present them to the SMPTE and DVB-ASI word alignment blocks simultaneously. 3.6 Lock Detect The lock detect block controls the centre frequency of the integrated reclocker to ensure lock to the received serial digital data stream is achieved, and indicates via the LOCKED output pin that the device has detected the appropriate sync words. In Data Through mode, the detection for appropriate sync words is turned off. The LOCKED pin is an indication of analog lock. Lock detection is a continuous process, which begins at device power up or after a system reset, and continues until the device is powered down or held in reset. The lock detection algorithm first determines if a valid serial digital input signal has been presented to the device by sampling the internal carrier_detect signal. As described in Section 3.2.2 on page 25, this signal will be LOW when a good serial digital input signal has been detected. If the carrier_detect signal is HIGH, the serial data into the device is considered invalid, and the VCO frequency will be set to the centre of the pull range. The LOCKED pin will be LOW and all outputs of the device except for the PCLK output will be muted. Instead, the PCLK output frequency will operate within +/-3% of the rates shown in Table 3-15 of Section 3.11.5 on page 51. NOTE: When the device is operating in DVB-ASI mode, the parallel outputs will not mute when the carrier_detect signal is HIGH. The LOCKED signal will function normally. If a valid input signal has been detected the lock algorithm will enter a hunt phase where four attempts are made to detect the presence of either SMPTE TRS sync words or DVB-ASI sync words. The centre frequency of the reclocker will be 270Mb/s. Assuming that a valid SMPTE or DVB-ASI signal has been applied to the device, asynchronous lock times will be as listed in AC Characteristics, Table 2-2. NOTE: The PCLK output will continue to operate during the lock detection process. The frequency may toggle will be 27MHz when the 20bit/10bit pin is set LOW, and 13.5MHz when 20bit/10bit is set HIGH. For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED output signal HIGH if (1) the reclocker has locked to the input data stream as indicated by the internal pll_lock signal, and (2) TRS or DVB-ASI sync words have been correctly identified. 22208 - 8 January 2007 28 of 61 GS9060 Data Sheet If after four attempts lock has not been achieved, the lock detection algorithm will enter into PLL lock mode. In this mode, the reclocker will attempt to lock to the input data stream without detecting SMPTE TRS or DVB-ASI sync words. This unassisted process can take up to 10ms to achieve lock. When reclocker lock as indicated by the internal pll_lock signal is achieved in this mode, data will be passed directly to the parallel outputs without any further processing taking place and the LOCKED signal will be asserted HIGH if and only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW. 3.6.1 Input Control Signals The GS9060 contains three input control signals which determine how the device locks to the input. It is required that the application layer set the SMPTE_BYPASS and DVB_ASI inputs to reflect the appropriate input data format. If either is configured incorrectly, the device will not lock to the input data stream, and the DATA_ERROR pin will be set LOW. The third input signal, RC_BYP, allows the application layer to determine whether the serial digital loop-through output will be a reclocked or buffered version of the input, Section 3.4.2 on page 27. Table 3-2 shows the required settings for various input formats. Table 3-2: Input Control Signals Format Pin Settings SMPTE_BYPASS SD SMPTE DVB-ASI NOT SMPTE OR DVB-ASI* HIGH LOW LOW DVB_ASI LOW HIGH LOW *NOTE: See Section 3.9 on page 36 for a complete description of Data-Through mode. 22208 - 8 January 2007 29 of 61 GS9060 Data Sheet 3.7 SMPTE Functionality The GS9060 is said to be in SMPTE mode once the device has detected SMPTE TRS sync words and locked to the input data stream as described in Section 3.6 on page 28. The device will remain in SMPTE mode until such time that SMPTE TRS sync words fail to be detected. The lock detect block may also drop out of SMPTE mode under the following conditions: • • • • RESET_TRST is asserted LOW CDx is HIGH SMPTE_BYPASS is asserted LOW DVB_ASI is asserted HIGH TRS word detection is a continuous process and both 8-bit and 10-bit TRS words will be identified by the device. The application layer must assert the DVB_ASI pin LOW and the SMPTE_BYPASS pin HIGH in order to enable SMPTE operation. 3.7.1 SMPTE Descrambling and Word Alignment After serial-to-parallel conversion, the internal 10-bit data bus is fed to the SMPTE descramble and word alignment block. The function of this block is to carry out NRZI-to-NRZ decoding, descrambling according to SMPTE 259M, and word alignment of the data to the TRS sync words. Word alignment occurs when two consecutive valid TRS words (SAV and EAV inclusive) with the same bit alignment have been detected. In normal operation, re-synchronization of the word alignment process will only take place when two consecutive identical TRS word positions have been detected. When automatic or manual switch line lock handling is 'actioned', Section 3.7.3 on page 31, word alignment re-synchronization will occur on the next received TRS code word. 3.7.2 Internal Flywheel The GS9060 has an internal flywheel which is used in the generation of internal / external timing signals, in the detection and correction of certain error conditions and in automatic video standards detection. It is only operational in SMPTE mode. The flywheel consists of a number of counters and comparators operating at video pixel and video line rates. These counters maintain information about the total line length, active line length, total number of lines per field / frame, and total active lines per field / frame for the received video stream. The flywheel 'learns' the video standard by timing the horizontal and vertical reference information contained in the TRS ID words of the received video stream. Full synchronization of the flywheel to the received video standard therefore requires one complete video frame. 22208 - 8 January 2007 30 of 61 GS9060 Data Sheet Once synchronization has been achieved, the flywheel will continue to monitor the received TRS timing information to maintain synchronization. The FW_EN/DIS input pin controls the synchronization mechanism of the flywheel. When this input signal is LOW, the flywheel will re-synchronize all pixel and line based counters on every received TRS ID word. When FW_EN/DIS is held HIGH, re-synchronization of the pixel and line based counters will only take place when a consistent synchronization error has been detected. Two consecutive video lines with identical TRS timing different to the current flywheel timing must occur to initiate re-synchronization of the counters. This provides a measure of noise immunity to internal and external timing signal generation. The flywheel will be disabled should the LOCKED signal or the RESET_TRST signal be LOW. A LOW to HIGH transition on either signal will cause the flywheel to re-acquire synchronization on the next received TRS word, regardless of the setting of the FW_EN/DIS pin. 3.7.3 Switch Line Lock Handling The principal of switch line lock handling is that the switching of synchronous video sources will only disturb the horizontal timing and alignment of the stream, whereas the vertical timing remains in synchronization. To account for the horizontal disturbance caused by a synchronous switch, it is necessary to re-synchronize the flywheel immediately after the switch has taken place. Rapid re-synchronization of the GS9060 to the new video standard can be achieved by controlling the flywheel using the FW_EN/DIS pin. At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW to HIGH transition at this pin is detected anywhere within the active line, the flywheel will re-synchronize immediately to the next TRS word. This is shown in Figure 3-2. To ensure switch line lock handling, the FW_EN/DIS signal should be LOW for a minimum of one PCLK cycle (maximum one video line) anywhere within the active portion of the line on which the switch has taken place. 22208 - 8 January 2007 31 of 61 GS9060 Data Sheet Switch point Video source 1 EAV ANC SAV ACTIVE PICTURE EAV ANC SAV EAV ACTIVE PICTURE ANC EAV ANC SAV ACTIVE PICTURE EAV ANC SAV Video source 2 EAV ANC SAV ACTIVE PICTURE EAV ANC SAV EAV ACTIVE PICTURE ANC EAV ANC SAV ACTIVE PICTURE EAV ANC SAV switch video source 1 to 2 DATA IN EAV ANC SAV ACTIVE PICTURE EAV ANC SAV ACTIVE PICTURE ANC EAV ANC SAV ACTIVE PICTURE EAV ANC SAV DATA OUT Flywheel TRS position FW_EN/DIS EAV ANC SAV ACTIVE PICTURE EAV ANC SAV ACTIVE PICTURE ANC EAV ANC SAV ACTIVE PICTURE EAV ANC SAV Flywheel re-synch Switch point Video source 1 EAV ANC SAV ACTIVE PICTURE EAV ANC SAV EAV ACTIVE PICTURE ANC EAV ANC SAV ACTIVE PICTURE EAV ANC SAV Video source 2 EAV ANC SAV ACTIVE PICTURE EAV ANC SAV EAV ACTIVE PICTURE ANC EAV ANC SAV ACTIVE PICTURE EAV ANC SAV switch video source 2 to 1 DATA IN EAV ANC SAV ACTIVE PICTURE EAV ANC SAV ACTIVE PICTURE EAV ANC SAV ACTIVE PICTURE EAV ANC SAV DATA OUT Flywheel TRS position FW_EN/DIS EAV ANC SAV ACTIVE PICTURE EAV ANC SAV ACTIVE PICTURE EAV ANC SAV ACTIVE PICTURE EAV ANC SAV Flywheel re-synch Figure 3-2: Switch Line Locking The ability to manually re-synchronize the flywheel is also important when switching asynchronous sources or to implement other non-standardized video switching functions. The GS9060 also implements automatic switch line lock handling. By utilizing the synchronous switch points defined by SMPTE RP168 for all major video standards with the automatic video standards detect function, the device automatically re-synchronizes the flywheel at the switch point. This function will occur regardless of the setting of the FW_EN/DIS pin. The switch line is defined as follows: • • • • For 525 line interlaced systems: re-sync takes place at the end of lines 10 & 273. For 525 line progressive systems: re-sync takes place at the end of line 10. For 625 line interlaced systems: re-sync takes place at the end of lines 6 & 319. For 625 line progressive systems: re-sync takes place at the end of line 6. A full list of all major video standards and switching lines is shown in Table 3-3. NOTE: The flywheel timing will define the line count such that the line numbers shown in Table 3-3 may not correspond directly to the digital line counts. 22208 - 8 January 2007 32 of 61 GS9060 Data Sheet Table 3-3: Switch Line Position for Digital Systems System SDTI Video Format 720x576/50 (2:1) 720x483/59.94 (2:1) Sampling 4:2:2 4:2:2 4:2:2 4:4:4:4 4:4:4:4 4:4:4:4 4:2:2 4:2:2 4:2:2 4:2:0 4:2:2 4:2:2 4:2:0 4:2:2 4:4:4:4 4:4:4:4 4:4:4:4 4:2:2 Signal Standard BT.656 125M 267M 267M 267M 267M 125M 293M 293M 293M BT.1358 BT.1358 BT.1358 BT.601 BT.799 BT.799 BT.799 BT.601 Parallel Interface BT.656 + 305M 125M + 305M 267M 347M RP174 RP175 125M 347M 293M 293M 347M BT.1358 BT.1358 BT.656 347M BT.799 BT.799 125M Serial Interface 259M 259M 259M 344M 344M RP175 259M 344M 294M 294M 344M BT.1362 BT.1362 259M 344M 344M – 259M Switch Line No. 6, 319 10, 273 10, 273 10, 273 10, 273 10, 273 10, 273 10 10 10 6 6 6 6, 319 6, 319 6, 319 6, 319 6, 319 525 960x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (2:1) 720x483/59.94 (1:1) 720x483/59.94 (1:1) 720x483/59.94 (1:1) 625 720x576/50 (1:1) 720x576/50 (1:1) 720x576/50 (1:1) 960x576/50 (2:1) 720x576/50 (2:1) 720x576/50 (2:1) 720x576/50 (2:1) 720x576/50 (2:1) 3.7.4 HVF Timing Signal Generation The GS9060 extracts critical timing parameters from either the received TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator (FW_EN/DIS = HIGH). Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F) timing are all extracted and presented to the application layer via the H:V:F status output pins. The H signal timing is configurable via the H_CONFIG bit of the internal IOPROC_DISABLE register as either active line based blanking, or TRS based blanking, Section 3.10.6 on page 46. Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode, the H output is HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words. This is the default H timing used by the device. 22208 - 8 January 2007 33 of 61 GS9060 Data Sheet When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H output will be HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words. The timing of these signals is shown in Figure 3-3. PCLK CHROMA DATA OUT 3FF 000 3FF 000 LUMA DATA OUT H V F H_CONFIG = HIGH 000 XYZ (eav) 000 XYZ (SAV) H SIGNAL TIMING: H_CONFIG = LOW H:V:F TIMING – 20-BIT OUTPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT H V F 3FF 000 000 XYZ (eav) 3FF 000 000 XYZ (sav) H:V:F TIMING – 10-BIT OUTPUT MODE Figure 3-3: H, V, F Timing 3.8 DVB-ASI Functionality The GS9060 conforms to DVB-ASI standard EN 50083-9:1998. The GS9060 is said to be in DVB-ASI mode once the device has detected 32 consecutive DVB-ASI words without a single word or disparity error being generated. The device will remain in DVB-ASI mode until 32 consecutive DVB-ASI word or disparity errors are detected, or until SMPTE TRS ID words have been detected. The lock detect block may also drop out of DVB-ASI mode under the following conditions: • • • • RESET_TRST is asserted LOW CDx is HIGH SMPTE_BYPASS is asserted HIGH DVB_ASI is asserted LOW K28.5 sync patterns in the received DVB-ASI data stream will be detected by the device in either inverted or non-inverted form. The application layer must set SMPTE_BYPASS LOW and DVB_ASI HIGH in order to enable DVB-ASI operation. 22208 - 8 January 2007 34 of 61 GS9060 Data Sheet 3.8.1 Transport Packet Format Transport packet structure shall conform to the specifications of EN/ISO/IEC 13818-1 and ETS 300 429 for Transport Stream Packets. The packet length can be 188 or 204 bytes. 3.8.2 DVB-ASI 8b/10b Decoding and Word Alignment After serial-to-parallel conversion, the internal 10-bit data bus is fed to the DVB-ASI 8b/10b decode and word alignment block. The function of this block is to word align the data to the K28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve bit alignment with the data outputs. The extracted 8-bit data will be presented to DOUT[17:10], bypassing all internal SMPTE mode data processing. NOTE: When operating in DVB-ASI mode, DOUT[9:0] are forced LOW. 3.8.3 Status Signal Outputs In DVB-ASI mode, the DOUT19 and DOUT18 pins will be configured as DVB-ASI status signals SYNCOUT and WORDERR respectively. SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output. This output may be used to drive the write enable signal of an external FIFO, thus providing a means of removing the K28.5 sync characters from the data stream. Parallel DVB-ASI data may then be clocked out of the FIFO at some rate less than 27MHz. See Figure 3-4. WORDERR will be high whenever the device has detected an illegal code word. DDI DDI GS9060 AOUT ~ HOUT 8 8 TS FE FF WORDERR FIFO WORDERR PCLK = 27MHz SYNCOUT CLK_IN WE CLK_OUT READ_CLK