HM514400B

ADE-203-269A (Z) 1,048,576-word × 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576word × 4-bit. HM514400B/BL, HM514400C/CL have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM514400B/BL, HM514400C/CL offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514400B/BL, HM514400C/CL to be packaged in standard 300-mil 26-pin plastic SOJ, standard 400-mil 20-pin plastic ZIP and 26pin plastic TSOP II. • Test function • Battery back up operation — HM514400BL Series (L-version) — HM514400CL Series (L-version) HM514400B/BL Series HM514400C/CL Series Features • Single 5 V (±10%) • High speed — Access time 60 ns/70 ns/80 ns (max) • Low power dissipation — Active mode 605 mW/550 mW/495 mW (max) — Standby mode 11 mW (max) 0.55 mW (max) (L-version) • Fast page mode capability • 1024 refresh cycles : 16 ms 1024 refresh cycles : 128 ms (L-version) • 3 variations of refresh — RAS-only refresh — CAS-before-RAS refresh — Hidden refresh HM514400B/BL, HM514400C/CL Series Ordering Information Type No. HM514400BS-6 HM514400BS-7 HM514400BS-8 HM514400BLS-6 HM514400BLS-7 HM514400BLS-8 HM514400CS-6 HM514400CS-7 HM514400CS-8 HM514400CLS-6 HM514400CLS-7 HM514400CLS-8 HM514400BZ-6 HM514400BZ-7 HM514400BZ-8 HM514400BLZ-6 HM514400BLZ-7 HM514400BLZ-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 400-mil 20-pin plastic ZIP (ZP-20) Package 300-mil 26-pin plastic SOJ (CP-26/20D) Type No. HM514400CZ-6 HM514400CZ-7 HM514400CZ-8 HM514400CLZ-6 HM514400CLZ-7 HM514400CLZ-8 HM514400BTT-6 HM514400BTT-7 HM514400BTT-8 HM514400BLTT-6 HM514400BLTT-7 HM514400BLTT-8 HM514400CTT-6 HM514400CTT-7 HM514400CTT-8 HM514400CLTT-6 HM514400CLTT-7 HM514400CLTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 26-pin plastic TSOPII (TTP-26/20D) Package 400-mil 20-pin plastic ZIP (ZP-20) 2 HM514400B/BL, HM514400C/CL Series Pin Arrangement HM514400BS/BLS Series HM514400CS/CLS Series HM514400BZ/BLZ Series HM514400CZ/CLZ Series 1 OE CAS 2 3 I/O3 I/O4 4 I/O1 6 WE 8 A9 5 22 OE A9 10 11 A0 A0 9 A1 10 A2 11 A3 12 VCC 13 18 A8 17 A7 16 A6 15 A5 14 A4 A1 12 13 A2 A3 14 A4 16 A6 18 19 A7 A8 20 (Bottom view) 15 VCC 17 A5 9 RAS 5 VSS 7 I/O2 I/O1 1 I/O2 2 WE 3 RAS 4 26 VSS 25 I/O4 24 I/O3 23 CAS (Top view) HM514400BTT/BLTT Series HM514400CTT/CLTT Series I/O1 1 I/O2 2 WE 3 RAS 4 A9 5 26 VSS 25 I/O4 24 I/O3 23 CAS 22 OE A0 9 18 A8 17 A7 16 A6 15 A5 14 A4 A1 10 A2 11 A3 12 VCC 13 (Top view) 3 HM514400B/BL, HM514400C/CL Series Pin Description Pin name A0 to A9 A0 to A9 I/O1 to I/O4 RAS CAS WE OE VCC VSS Function Address input Refresh address input Data-in/Data-out Row address strobe Column address strobe Read/Write enable Output enable Power (+5 V) Ground 4 Block Diagram RAS Row Driver Row Driver RAS Control Circuit 256 k Memory Array Mat 256 k Memory Array Mat I/O1 I/O1 Buffer I/O Bus & Column Decoder Row Driver Row Driver I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat 256 k Memory Array Mat Row Driver Row Driver CAS CAS Control Circuit 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver Row Driver Row Address Buffer I/O2 I/O2 Buffer I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat WE WE Control Circuit Row Decoder & Peripheral Circuit Address A0–A9 Row Driver Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O3 OE I/O3 Buffer OE Control Circuit 256 k Memory Array Mat Row Driver Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder Column Address Buffer Row Driver Row Driver I/O4 I/O4 Buffer I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat HM514400B/BL, HM514400C/CL Series 5 HM514400B/BL, HM514400C/CL Series Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value –1.0 to +7.0 –1.0 to +7.0 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: VIH VIL Min 0 4.5 2.4 –1.0 Typ 0 5.0 — — Max 0 5.5 6.5 0.8 Unit V V V V 1 1 1 Note 1. All voltage referred to VSS. 6 HM514400B/BL, HM514400C/CL Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM514400B/BL, HM514400C/CL -6 Parameter Operating current Standby current Symbol ICC1 ICC2 -7 -8 Notes 1, 2 RAS, CAS cycling tRC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface 4 RAS, CAS =VIH WE, OE, Address and Din = VIH or VIL Dout = High-Z tRC = min 2 Min Max Min Max Min Max Unit Test conditions — — 110 — 2 — 100 — 2 — 90 2 mA mA — 1 — 1 — 1 mA Standby current (L-version) ICC2 — 100 — 100 — 100 µA RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current Battery back up current (Standby with CBR refresh) (L-version) Input leakage current Output leakage current Output high voltage Output low voltage ICC3 ICC5 ICC6 ICC7 ICC10 — — — — — 110 — 5 — 100 — 5 — 90 5 90 90 mA mA mA mA RAS = VIH, CAS = VIL 1 Dout = enable tRC = min tPC = min tRC = 125 µs tRAS ≤ 1 µs WE = VIH, CAS = VIL OE, Address and Din = VIH or VIL Dout = High-Z 0 V ≤ Vin ≤ 7 V 0 V ≤ Vout ≤ 7 V Dout = disable High Iout = –5 mA Low Iout = 4.2 mA 1, 3 4 110 — 110 — 200 — 100 — 100 — 200 — 200 µA ILI ILO VOH VOL –10 10 –10 10 2.4 0 –10 10 –10 10 –10 10 –10 10 µA µA VCC 2.4 0.4 0 VCC 2.4 0.4 0 VCC V 0.4 V Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VCC – 0.2 V ≤ VIH ≤ 6.5 V and 0 V ≤ VIL ≤ 0.2 V. 7 HM514400B/BL, HM514400C/CL Series Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ — — — Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) *1, *14, *15, *16 Test Conditions • Input rise and fall times : 5 ns • Input timing reference levels : 0.8 V, 2.4 V • Output load : 2 TTL gate + CL (100 pF) (Including scope and jig) 8 HM514400B/BL, HM514400C/CL Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514400B/BL, HM514400C/CL -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT tREF tREF Min 110 40 60 15 0 10 0 15 20 15 15 60 10 15 0 0 3 — — Max — — -7 Min 130 50 Max — — -8 Min 150 60 Max — — Unit ns ns 19 20 Notes 10000 70 10000 20 — — — — 45 30 — — — — — — 50 16 128 0 10 0 15 20 15 20 70 10 20 0 0 3 — — 10000 80 10000 20 — — — — 50 35 — — — — — — 50 16 128 0 10 0 15 20 15 20 80 10 20 0 0 3 — — 10000 ns 10000 ns — — — — 60 40 — — — — — — 50 16 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 8 9 7 9 HM514400B/BL, HM514400C/CL Series Read Cycle HM514400B/BL, HM514400C/CL -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off time to OE CAS to Din delay time OE pulse width Symbol tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tOFF1 tOFF2 tCDD tOEP Min — — — — 0 0 0 30 0 0 15 15 Max 60 15 30 15 — — — — 15 15 — — -7 Min — — — — 0 0 0 35 0 0 20 20 Max 70 20 35 20 — — — — 20 20 — — -8 Min — — — — 0 0 0 40 0 0 20 20 Max 80 20 40 20 — — — — 20 20 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns 6 6 18 18 Notes 2, 3, 17 3, 4, 13, 17 3, 5, 13, 17 3, 17 Write Cycle HM514400B/BL, HM514400C/CL -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 15 10 15 15 0 15 Max — — — — — — — -7 Min 0 15 10 20 20 0 15 Max — — — — — — — -8 Min 0 15 10 20 20 0 15 Max — — — — — — — Unit ns ns ns ns ns ns ns 11 11 Notes 10 10 HM514400B/BL, HM514400C/CL Series Read-Modify-Write Cycle HM514400B/BL, HM514400C/CL -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 150 80 35 50 15 Max — — — — — -7 Min 180 95 45 60 20 Max — — — — — -8 Min 200 105 45 65 20 Max — — — — — Unit ns ns ns ns ns 10 10 10 Notes Refresh Cycle HM514400B/BL, HM514400C/CL -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol tCSR tCHR tRPC tCPN Min 10 10 10 10 Max — — — — -7 Min 10 10 10 10 Max — — — — -8 Min 10 10 10 10 Max — — — — Unit ns ns ns ns Notes Fast Page Mode Cycle HM514400B/BL, HM514400C/CL -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol tPC tRASC tACP tRHCP Min 40 10 — — 35 Max — — -7 Min 45 10 Max — — -8 Min 50 10 Max — — Unit ns ns 12 3, 13, 17 Notes Fast page mode CAS precharge time tCP 100000 — 35 — — 40 100000 — 40 — — 45 100000 ns 45 — ns ns 11 HM514400B/BL, HM514400C/CL Series Fast Page Mode Read-Modify-Write Cycle HM514400B/BL, HM514400C/CL -6 Parameter Fast page mode read-modify-write cycle time Fast page mode read-modify-write cycle CAS precharge to WE delay time Symbol tPCM tCPW Min 80 55 Max — — -7 Min 95 65 Max — — -8 Min 100 70 Max — — Unit ns ns 10 Notes Test Mode Cycle HM514400B/BL, HM514400C/CL -6 Parameter Test mode WE setup time Test mode WE hold time Symbol tWS tWH Min 0 10 Max — — -7 Min 0 10 Max — — -8 Min 0 10 Max — — Unit ns ns Notes Counter Test Cycle HM514400B/BL, HM514400C/CL -6 Parameter CAS precharge time in counter test cycle Symbol tCPT Min 40 Max — -7 Min 40 Max — -8 Min 40 Max — Unit ns Notes 12 HM514400B/BL, HM514400C/CL Series Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. tWCS, tRWD, tCWD, tCPW and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tCPW ≥ tCPW (min) and tAWD ≥ tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among tAA, tCAC and tACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. In order to end this test mode operation, perform a RAS-only refresh cycle or a CAS-before-RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. Either tRCH or tRRH must be satisfied 19. tRAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 20. tCAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 13 HM514400B/BL, HM514400C/CL Series Timing Waveforms*21 Read Cycle t RC t RAS RAS tT t RCD t RSH t CAS t CSH t RP t CRP CAS t RAD t ASR t RAH t ASC t RAL t CAH Address Row Column t RCS t RCH WE t CAC t AA Dout t RAC t DZC Din t DZO High-Z t OAC t RRH t OFF1 Dout t OFF2 t CDD t ODD t OEP OE À € @ À € @ Notes: 21. 14 H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) Invalid Dout HM514400B/BL, HM514400C/CL Series Early Write Cycle t RC t RAS RAS tT t RCD t CSH CAS t RSH t CAS t RP t CRP t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) ** OE : H or L 15 HM514400B/BL, HM514400C/CL Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Column t CWL t RWL Address Row t RCS t WP WE t DS t DH Din t DZC t DZO High-Z Din t ODD t OEH  Dout Invalid Dout* t OFF2 OE * * Invalid Dout comes out, when OE is low level. 16 HM514400B/BL, HM514400C/CL Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC tCAH Address Row t RCS Column t CWD t AWD t CWL t RWL t WP WE t RWD t RAC t DZC Din High-Z t AA t CAC t DS t DH Din Dout t OAC Dout t OFF2 t DZO OE t OEP t ODD t OEH 17 HM514400B/BL, HM514400C/CL Series Hidden Refresh Cycle tRC t RAS (Read) t RC t RP t RAS (Refresh) t RC t RP t RAS (Refresh) tRP RAS tT t RSH t RCD CAS t ASC t ASR t RAD t RAH Address Row t RAL t CAH Column t RCH t RRH t RCS WE t RAC Dout t DZC Dout t OFF2 High-Z tDZO t OAC t ODD t CAC t AA t OFF1 t CAS t CHR t CRP t CDD Din OE 18 HM514400B/BL, HM514400C/CL Series Fast Page Mode Read Cycle t RASC t RHCP t RP RAS tT t CSH t RCD CAS t ASR t RAD t RAH Address Row tASC t CAH Column t ASC t CAH Column t ASC t CAH Column t RAL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din High-Z t ODD t CAC t RAC t AA t DZC t CDD High-Z tCAC t AA t ACP t OFF1 Dout t OAC t DZO t OFF2 t OEP Dout t DZO t OEP Dout t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t CAC t AA t ACP t OFF1 t DZO Dout t ODD t OFF2 t OEP t OAC t OFF2 t ODD t OFF1 OE t OAC 19 HM514400B/BL, HM514400C/CL Series Fast Page Mode Early Write Cycle t RASC t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column Column Column t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din Din Din Dout High-Z * OE : H or L 20 HM514400B/BL, HM514400C/CL Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS tT t CSH tRCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Column t CWL t RCS t WP WE t DH t DS t RCS t DS t DH t RCS t DS Din t DH t ASC t CAH t ASC t CAH Address Row Column t CWL t WP Column t CWL t WP t RWL Din Din Din t OEH Dout t ODD High-Z OE 21 HM514400B/BL, HM514400C/CL Series Fast Page Mode Read-Modify-Write Cycle t RASC RAS t RCD tT t CAS CAS t RAD t RAH t ASR t CAH t ASC t ACP t ASC t CAH t CAH t ASC t CP t CAS t PCM t CP t CAS t RP t CRP Address Row Column t AWD t CWD t RWD t CWL t WP t RCS Column t AWD t CWD t CPW t CWL t WP Column t CPW t AWD t RCS t CWD t CWL t RWL t WP t RCS WE t CAC t DS t DH High-Z tAA t RAC tOAC Dout t DZO Dout t OFF2 t DZO t OEH t OAC Dout t OFF2 t OEH t DZC t CAC t DS t DH t ACP t DZC High-Z t CAC t AA t OAC Dout t OFF2 t OEH t DS t DH t DZC Din Din High-Z t AA Din Din t DZO OE t ODD t OEP t OEP t ODD tOEP t ODD 22 HM514400B/BL, HM514400C/CL Series Test Mode Cycle *,** Reset Cycle Set Cycle** Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L Test Mode Set Cycle WE-and-CAS-Before RAS-Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR tT CAS t CPN@ t WS t CHR t RPC t CRP t WH  WE Address t OFF1 Dout High-Z ÀÀ €€ @@ t CPN 23 HM514400B/BL, HM514400C/CL Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS tT t CPN t RPC t CSR t CHR t CPN t RPC t CRP CAS t WS t WH WE Address t OFF1 High-Z Dout 
24 HM514400B/BL, HM514400C/CL Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC tCRP CAS t ASR t RAH Address Row Dout High-Z * Refresh address : A0 – A9 (AX0 – AX9) ** WE : H or L 25 HM514400B/BL, HM514400C/CL Series CAS-Before-RAS Refresh Counter Check Cycle (Read) t RAS RAS tT t CSR t CHR t CPT t RSH t CAS t RP tCRP CAS t ASC t CAH Address Column t RCH t RRH t WS t WH t RCS WE t DZC t CDD Din t CAC t AA High-Z t OFF1 Dout t DZO t OAC Dout t OFF2 t OEP t ODD OE 26 HM514400B/BL, HM514400C/CL Series CAS-Before-RAS Refresh Counter Check Cycle (Write) t RAS RAS tT t CSR t CHR t CPT t RSH t CAS t RP t CRP CAS t ASC t CAH Address Column t WS t WH t WCS t WCH WE t DS t DH Din Din Dout High-Z OE 27