341MPLF

DATASHEET ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER Description Features The ICS341 is a low cost, single-output, field programmable clock synthesizer. The ICS341 can generate an output frequency from 250 kHz to 200 MHz and may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). • 8-pin SOIC package (Pb-free) • Highly accurate frequency generation • M/N Multiplier PLL: M = 1...2048, N = 1...1024 • Output clock frequencies up to 200 MHz • Four ROM locations for frequency and spread selection • Spread spectrum capability for lower system EMI • Center or Down Spread up to 4% total • Selectable 32 kHz or 120 kHz modulation • Input crystal frequency from 5 to 27 MHz • Input clock frequency from 2 to 50 MHz • Operating voltage of 3.3 V • Advanced, low-power CMOS process • For two output clocks, use the ICS342. For three output Using IDT’s VersaClock™software to configure the PLL and output, the ICS341 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include 4 selectable configuration registers. The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. clocks, see the ICS343. For more than three outputs, see the ICS345 or ICS348. The ICS341 is also available in factory programmed custom versions for high-volume applications. Block Diagram VDD S1:0 2 OTP ROM with PLL Divider Values Crystal or clock input PLL Clock Synthesis, Spred Spectrum and Control Circuitry CLK X1/ICLK Crystal Oscillator X2 External capacitors are required with a crystal input. GND IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER PDTS (output and PLL) 1 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Pin Assignment Output Clock Selection Table S1 S0 CLK (MHz) Spread Percentage 0 0 S1 0 1 CLK 1 0 1 1 User Configurable User Configurable User Configurable User Configurable User Configurable User Configurable User Configurable User Configurable X1/ I CLK 1 8 X2 VDD 2 7 PDTS GND 3 6 S0 4 5 8-pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 X1/ICLK XI 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 S0 Input 5 CLK Output 6 S1 Input 7 PDTS Input 8 X2 XO Pin Description Connect this pin to a crystal or external clock input. Select pin 0 for frequency selection on CLK. Internal pull-up resistor. Clock output. Weak internal pull-down when tri-state. Select pin 1 for frequency selection on CLK. Internal pull-up resistor. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up resistor. Connect this pin to a crystal, or float for clock input. External Components Series Termination Resistor capacitors must be connected from each of the pins X1 and X2 to ground. Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. Decoupling Capacitor PCB Layout Recommendations As with any high-performance mixed-signal IC, the ICS341 must be isolated from system power supply noise to perform optimally. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 2 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS341. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Spread Spectrum Modulation can be applied as either “center spread” or “down spread”. During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. ICS341 Configuration Capabilities The architecture of the ICS341 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS341 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between +/- 0.125% to +/-2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. The ICS341 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate Each output frequency can be represented as: OutputFreq = REFFreq -------------------------------------OutputDivide The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of “down-circuit” PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. ----M N IDT VersaClock Software Using VersaClock Products with an Input Clock Source IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. In order to ensure proper startup with an input clock rather than a crystal, the supply voltage must be within the operating range (3.3V ±10%) and the input signal must be stable and free from glitching. The input clock must provide pulses of at least 20ns, and no more than 500ns, for at least 160 clock cycles without any interruptions to the clock or power during this period. It may take up to 4ms for output frequencies to reach their target frequency values. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. An alternative method is to have the PDTS pin asserted low while power supplies and clock sources stabilize.Once the power supply and input clock source are constant and within the acceptable frequency range, bring PDTS high. This approach is preferred if the clock source is derived from another PLL, or the source oscillator produces unpredictable output pulses prior to stabilization. No considerations need to be taken when using a crystal input source with VersaClock products. Spread Spectrum Modulation The ICS341 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system’s electro-magnetic interference (EMI). IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 3 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS341. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Supply Voltage, VDD Referenced to GND Inputs Clock Outputs Max. Units -0.5 7 V Referenced to GND -0.5 VDD+ 0.5 V Referenced to GND -0.5 VDD+ 0.5 V -65 150 C 260 C 125 C Storage Temperature Soldering Temperature Typ. Max 10 seconds Junction Temperature Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS341M) 0 +70 C Ambient Operating Temperature (ICS341MI) -40 +85 C +3.45 V 4 ms Power Supply Voltage (measured in respect to GND) Power Supply Ramp Time IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 4 +3.15 +3.3 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85C Parameter Operating Voltage Symbol Conditions VDD Min. Typ. Max. Units 3.15 3.3 3.45 V Configuration Dependent - See VersaClockTM mA 33.3333 MHz output, PDTS = 1, no load Note 1 11 mA 20 A V Operating Supply Current Input High Voltage IDD Input High Voltage VIH PDTS = 0 S1:S0 Input Low Voltage VIL S1:S0 Input High Voltage, PDTS VIH Input Low Voltage, PDTS VIL Input High Voltage VIH ICLK Input Low Voltage VIL ICLK Output High Voltage (CMOS High) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS ±70 mA Nominal Output Impedance ZO 20  2 0.4 VDD-0.5 V V 0.4 VDD/2+1 V V VDD/2-1 0.4 V V Internal pull-up resistor RPUP S1:S0 250 k Internal pull-up resistor RPUP PDTS 250 k Internal pull-down resistor RPD CLK output 525 k Input Capacitance CIN inputs 4 pF Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V. IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 5 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85 C Parameter Input Frequency Symbol FIN Conditions Min. Typ. Max. Units Fundamental Crystal 5 27 MHz Input Clock 2 50 MHz 0.25 200 MHz Output Frequency Output Rise Time tOR 20% to 80%, Note 1 1 ns Output Fall Time tOF 80% to 20%, Note 1 1 ns Duty Cycle Note 2 Output Frequency Synthesis Error Configuration Dependent Power-up Time PLL lock time from power-up 4 10 ms PDTS goes high until stable CLK output, Spread Spectrum Off .2 2 ms PDTS goes high until stable CLK output, Spread Spectrum On 4 7 ms Configuration Dependent 50 ps Deviation from Mean. Configuration Dependent +200 ps One Sigma Clock Period Jitter Maximum Absolute Jitter tja 40 49-51 60 TBD % ppm Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Note 3: ICS test mode output occurs for first 170 clock cycles on CLK for each PLL powered up. PDTS transition high on select address change. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Units JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W 40 C/W JC IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E Min A A1 B C D E e H h L  H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 h x 45 A1 C -Ce B SEATING PLANE  L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 341MPLF 341MPLFT 341MIPLF 341MIPLFT 341MP-XXLF 341MP-XXLFT 341MIP-XXLF 341MIP-XXLFT 341MPLF 341MPLF 341MIPLF 341MIPLF 341-XXMPLF 341-XXMPLF 341-XXMIPLF 341-XXMIPLF Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C “LF” suffix to the part number denotes Pb-Free configuration, RoHS compliant. The 341M-XXLF and 341MI-XXLF are factory programmed versions of the 341MPLF and 341MIPLF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 7 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Revision History Rev. Date Originator M 09/06/13 S. Zheng N 07/28/16 V.A. Description of Change Added brief applications section/verbiage “Using VersaClock Products with an Input Clock Source” on page 3. Updated ordering information for factory programmables. IDT® / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 8 ICS341 REV N 072816 ICS341 FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2016 Integrated Device Technology, Inc. All rights reserved. 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