24-Lane 6-Port PCIe® Gen2
System Interconnect Switch
89HPES24NT6AG2
Datasheet
®
Device Overview
• Two BARs (BAR2 and BAR4) support look-up table based
address translation
– 32 inbound and outbound doorbell registers
– 4 inbound and outbound message registers
– Supports up to 64 masters
– Unlimited number of outstanding transactions
Multicast
– Compliant with the PCI-SIG multicast
– Supports 64 multicast groups
– Supports multicast across non-transparent port
– Multicast overlay mechanism support
– ECRC regeneration support
Integrated Direct Memory Access (DMA) Controllers
– Supports up to 2 DMA upstream ports, each with 2 DMA channels
– Supports 32-bit and 64-bit memory-to-memory transfers
• Fly-by translation provides reduced latency and increased
performance over buffered approach
• Supports arbitrary source and destination address alignment
• Supports intra- as well as inter-partition data transfers using
the non-transparent endpoint
– Supports DMA transfers to multicast groups
– Linked list descriptor-based operation
– Flexible addressing modes
• Linear addressing
• Constant addressing
Quality of Service (QoS)
– Port arbitration
• Round robin
– Request metering
• IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
– High performance switch core architecture
• Combined Input Output Queued (CIOQ) switch architecture
with large buffers
Clocking
– Supports 100 MHz and 125 MHz reference clock frequencies
– Flexible port clocking modes
• Common clock
• Non-common clock
• Local port clock with SSC (spread spectrum setting) and port
reference clock input
The 89HPES24NT6AG2 is a member of the IDT family of PCI
Express® switching solutions. The PES24NT6AG2 is a 24-lane, 6-port
system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include multi-host or
intelligent I/O based systems where inter-domain communication is
required, such as servers, storage, communications, and embedded
systems.
Features
High Performance Non-Blocking Switch Architecture
– 24-lane, 6-port PCIe switch with flexible port configuration
– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
– Delivers up to 24 GBps (192 Gbps) of switching capacity
– Supports 128 Bytes to 2 KB maximum payload size
– Low latency cut-through architecture
– Supports one virtual channel and eight traffic classes
Port Configurability
– Six x4 ports
– Automatic per port link width negotiation
(x4 x2 x1)
– Crosslink support
– Automatic lane reversal
– Per lane SerDes configuration
• De-emphasis
• Receive equalization
• Drive strength
Innovative Switch Partitioning Feature
– Supports up to 6 fully independent switch partitions
– Logically independent switches in the same device
– Configurable downstream port device numbering
– Supports dynamic reconfiguration of switch partitions
• Dynamic port reconfiguration — downstream, upstream,
non-transparent bridge
• Dynamic migration of ports between partitions
• Movable upstream port within and between switch partitions
Non-Transparent Bridging (NTB) Support
– Supports up to 6 NT endpoints per switch, each endpoint can
communicate with other switch partitions or external PCIe
domains or CPUs
– 6 BARs per NT Endpoint
• Bar address translation
• All BARs support 32/64-bit base and limit address translation
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2013 Integrated Device Technology, Inc
December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Hot-Plug and Hot Swap
– Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
– All ports support hot-plug using low-cost external I2C I/O
expanders
– Configurable presence-detect supports card and cable applications
– GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system
support
– Hot-swap capable I/O
Power Management
– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)
• Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
• Configurable L0s and L1 entry timers allow performance/
power-savings tuning
– SerDes power savings
• Supports low swing / half-swing SerDes operation
• SerDes associated with unused ports are turned off
• SerDes associated with unused lanes are placed in a low
power state
Reliability, Availability, and Serviceability (RAS)
– ECRC support
– AER on all ports
– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Initialization / Configuration
– Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
– Common switch configurations are supported with pin strapping (no external components)
– Supports in-system Serial EEPROM initialization/programming
On-Die Temperature Sensor
– Range of 0 to 127.5 degrees Celsius
– Three programmable temperature thresholds with over and
under temperature threshold alarms
– Automatic recording of maximum high or minimum low
temperature
9 General Purpose I/O
Test and Debug
– Ability to inject AER errors simplifies in system error handling
software validation
– On-chip link activity and status outputs available for several
ports
– Per port link activity and status outputs available using
external I2C I/O expander for all remaining ports
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Standards and Compatibility
– PCI Express Base Specification 2.1 compliant
– Implements the following optional PCI Express features
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting
• Multicast
• VGA and ISA enable
• L0s and L1 ASPM
• ARI
Power Supplies
– Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
Product Description
With Non-Transparent Bridging functionality and innovative Switch
Partitioning feature, the PES24NT6AG2 allows true multi-host or multiprocessor communications in a single device. Integrated DMA controllers enable high-performance system design by off-loading data transfer
operations across memories from the processors. Each lane is capable
of 5 GT/s link speed in both directions and is fully compliant with PCI
Express Base Specification 2.1.
A non-transparent bridge (NTB) is required when two PCI Express
domains need to communicate to each other. The main function of the
NTB block is to initialize and translate addresses and device IDs to
allow data exchange across PCI Express domains. The major functionalities of the NTB block are summarized in Table 1.
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Block Diagram
6-Port Switch Core / 24 Gen2 PCI Express Lanes
Frame Buffer
Port
Arbitration
Route Table
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes SerDes
(Port 2)
(Port 0)
(Ports 4, 6, 8,)
Phy
Logical
Layer
(Port 12)
Figure 1 PES24NT6AG2 Block Diagram
Function
Number
Description
NTB ports
Up to 6
Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Mapping table
entries
Up to 64 for entire
device
Each device can have up to 64 masters ID for address and ID translations.
Mapping windows
Six 32-bits or three
64-bits
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Address translation Direct-address and
lookup table translations
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell registers
32 bits
Doorbell register is used for event signaling between domains, where an outbound doorbell bit
sets a corresponding bit at the inbound doorbell in the other domain.
Message registers
4 inbound and outbound registers of
32-bits
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Table 1 Non-Transparent Bridge Function Summary
SMBus Interface
The PES24NT6AG2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES24NT6AG2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES24NT6AG2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface
is also used by an external Hot-Plug I/O expander.
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Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration. In the split configuration, the
master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not
support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM
and I/O expander slaves.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 2 Split SMBus Interface Configuration
Hot-Plug Interface
The PES24NT6AG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES24NT6AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES24NT6AG2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES24NT6AG2. In response to an I/O expander interrupt, the PES24NT6AG2 generates
an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24NT6AG2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES24NT6AG2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Note: Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.
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Signal
Type
Name/Description
PE00RN[3:0]
PE00RP[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for
port 0.
PE00TN[3:0]
PE00TP[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for
port 0.
PE02RN[3:0]
PE02RP[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for
port 2.
PE02TN[3:0]
PE02TP[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2.
PE04RN[3:0]
PE04RP[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for
port 4.
PE04TN[3:0]
PE04TP[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for
port 4.
PE06RN[3:0]
PE06RP[3:0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for
port 6.
PE06TN[3:0]
PE06TP[3:0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for
port 6.
PE08RN[3:0]
PE08RP[3:0]
I
PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pair for
port 8.
PE08TN[3:0]
PE08TP[3:0]
O
PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pair for
port 8.
PE12RN[3:0]
PE12RP[3:0]
I
PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pair for
port 12.
PE12TN[3:0]
PE12TP[3:0]
O
PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pair for
port 12.
Table 2 PCI Express Interface Pins
Signal
Type
Name/Description
GCLKN[1:0]
GCLKP[1:0]
I
Global Reference Clock. Differential reference clock input pairs. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
Note: Both pairs of the Global Reference Clocks must be connected to and
derived from the same clock source. Refer to the Overview section of
Chapter 2 in the PES24NT6AG2 User Manual for additional details.
P00CLKN
P00CLKP
I
Port Reference Clock. Differential reference clock pair associated with
port 0.
P02CLKN
P02CLKP
I
Port Reference Clock. Differential reference clock pair associated with
port 2.
P04CLKN
P04CLKP
I
Port Reference Clock. Differential reference clock pair associated with
port 4.
Table 3 Reference Clock Pins (Part 1 of 2)
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Signal
Type
Name/Description
P06CLKN
P06CLKP
I
Port Reference Clock. Differential reference clock pair associated with
port 6.
P08CLKN
P08CLKP
I
Port Reference Clock. Differential reference clock pair associated with
port 8.
P12CLKN
P12CLKP
I
Port Reference Clock. Differential reference clock pair associated with
port 12.
Table 3 Reference Clock Pins (Part 2 of 2)
Signal
Type
Name/Description
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[2,1]
I
Slave SMBus Address. These pins determine the SMBus address to which the slave
SMBus interface responds.
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the
slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.
Table 4 SMBus Interface Pins
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: PART0PERSTN
1st Alternate function pin type: Input/Output
1st Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: PART1PERSTN
1st Alternate function pin type: Input/Output
1st Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: PART2PERSTN
1st Alternate function pin type: Input/Output
1st Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition.
2nd Alternate function pin name: P4LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 4 Link Up Status output.
Table 5 General Purpose I/O Pins (Part 1 of 2)
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IDT 89HPES24NT6AG2 Datasheet
Signal
Type
Name/Description
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: PART3PERSTN
1st Alternate function pin type: Input/Output
1st Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition.
2nd Alternate function pin name: P4ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 4 Link Active Status Output.
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER0
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the corresponding failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: P0LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 0 Link Up Status output.
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: GPEN
1st Alternate function pin type: Output
1st Alternate function: Hot-plug general purpose even output.
2nd Alternate function pin name: P0ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 0 Link Active Status Output.
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER1
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the corresponding failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: FAILOVER3
2nd Alternate function pin type: Input
2nd Alternate function: When this signal changes state and the corresponding failover capability is enabled, a failover event is signaled.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER2
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the corresponding failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: P8LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 8 Link Up Status output.
GPIO[8]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: IOEXPINTN
1st Alternate function pin type: Input
1st Alternate function: IO expander interrupt.
2nd Alternate function pin name: P8ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 8 Link Active Status Output.
Table 5 General Purpose I/O Pins (Part 2 of 2)
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Signal
Type
Name/Description
STK0CFG[0]
I
Stack 0 Configuration. This pin selects the configuration of stack 0.
STK1CFG[0]
I
Stack 1 Configuration. This pin selects the configuration of stack 1.
STK2CFG[0]
I
Stack 2 Configuration. This pin selects the configuration of stack 2.
Table 6 Stack Configuration Pins
Signal
Type
Name/Description
CLKMODE[1:0]
I
Clock Mode. These signals determine the port clocking mode used by ports of the
device.
GCLKFSEL
I
Global Clock Frequency Select. These signals select the frequency of the GCLKP
and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the device.
RSTHALT
I
Reset Halt. When this signal is asserted during a switch fundamental reset sequence,
the switch remains in a quasi-reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device before normal
device operation begins. The device exits the quasi-reset state when the RSTHALT bit
is cleared in the SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the switch operating mode.
These pins should be static and not change following the negation of PERSTN.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 - Single partition with Serial EEPROM Jump 0 initialization
0x3 - Single partition with Serial EEPROM Jump 1 initialization
0x4 through 0x7 - Reserved
0x8 - Single partition with reduced latency
0x9 - Single partition with Serial EEPROM initialization and reduced latency
0xA - Multi-partition with Unattached ports
0xB - Multi-partition with Unattached ports and I2C Reset
0xC - Multi-partition with Unattached ports and Serial EEPROM initialization
0xD - Multi-partition with Unattached ports with I2C Reset and Serial EEPROM initialization
0xE - Multi-partition with Disabled ports
0xF - Multi-partition with Disabled ports and Serial EEPROM initialization
Table 7 System Pins
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Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 8 Test Pins
Signal
Type
Name/Description
REFRES[5:0]
Analog
External Reference Resistor. Reference for the corresponding SerDes
bias currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should
be connected from this pin to ground and isolated from any source of noise
injection. Each bit of this signal corresponds to a SerDes quad, e.g.,
REFRES[5] is the reference resistor for SerDes quad 5.
REFRESPLL
Analog
PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground and isolated from any source of noise
injection.
VDDCORE
I
Core VDD. Power supply for core logic (1.0V).
VDDI/O
I
I/O VDD. LVTTL I/O buffer power supply (3.3V).
VDDPEA
I
PCI Express Analog Power. Serdes analog power supply (1.0V).
VDDPEHA
I
PCI Express Analog High Power. Serdes analog power supply (2.5V).
VDDPETA
I
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
VSS
I
Ground.
Table 9 Power, Ground, and SerDes Resistor Pins
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Pin Characteristics
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to
appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, floating
pins can cause a slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally, No Connection pins
should not be connected.
Function
PCI Express Interface
Reference Clocks
Pin Name
I/O
Type
Internal
Resistor1
Type
Buffer
Notes
PE00RN[3:0]
I
Serial Link
PE00RP[3:0]
I
PCIe
differential2
Note: Unused SerDes
pins can be left floating
PE00TN[3:0]
O
PE00TP[3:0]
O
PE02RN[3:0]
I
PE02RP[3:0]
I
PE02TN[3:0]
O
PE02TP[3:0]
O
PE04RN[3:0]
I
PE04RP[3:0]
I
PE04TN[3:0]
O
PE04TP[3:0]
O
PE06RN[3:0]
I
PE06RP[3:0]
I
PE06TN[3:0]
O
PE06TP[3:0]
O
PE08RN[3:0]
I
PE08RP[3:0]
I
PE08TN[3:0]
O
PE08TP[3:0]
O
PE12RN[3:0]
I
PE12RP[3:0]
I
PE12TN[3:0]
O
PE12TP[3:0]
O
GCLKN[1:0]
I
HCSL
Refer to Table 11
GCLKP[1:0]
I
Diff. Clock
Input
P00CLKN
I
P00CLKP
I
P02CLKN
I
P02CLKP
I
P04CLKN
I
Note: Unused port
clock pins should be
connected to Vss on
the board.
Table 10 Pin Characteristics (Part 1 of 2)
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IDT 89HPES24NT6AG2 Datasheet
Function
Reference Clocks (cont.)
SMBus
Pin Name
I/O
Type
Type
Buffer
P04CLKP
I
HCSL
P06CLKN
I
Diff. Clock
Input
P06CLKP
I
P08CLKN
I
P08CLKP
I
P12CLKN
I
P12CLKP
I
MSMBCLK
I/O
LVTTL
STI3
MSMBDAT
I/O
SSMBADDR[2,1]
STI
I
Internal
Resistor1
Notes
Refer to Table 11
Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specification.
pull-up
SSMBCLK
I/O
STI
SSMBDAT
I/O
STI
General Purpose I/O
GPIO[8:0]
I/O
LVTTL
STI, High
Drive
pull-up
Unused pins can be left
floating.
Stack Configuration
STK0CFG[0]
I
LVTTL
Input
pull-down
STK1CFG[0]
I
pull-down
Unused pins can be left
floating.
STK2CFG[0]
I
pull-down
CLKMODE[1:0]
I
GCLKFSEL
I
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-down
JTAG_TCK
I
JTAG_TDI
I
JTAG_TDO
O
JTAG_TMS
JTAG_TRST_N
System Pins
EJTAG / JTAG
SerDes Reference Resistors
REFRES[5:0]
LVTTL
Input
Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specification.
pull-up
pull-down
Unused pins can be left
floating.
Schmitt trigger
LVTTL
STI
pull-up
STI
pull-up
I
STI
pull-up
I
STI
pull-up
Analog
REFRESPLL
Unused pins can be left
floating.
Unused pins can be left
floating.
Unused pins should be
connected to Vss on
the board.
Table 10 Pin Characteristics (Part 2 of 2)
1. Internal resistor values under typical operating conditions are 92K for pull-up and 91K for pull-down.
2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
Schmitt Trigger Input (STI).
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Logic Diagram — PES24NT6AG2
Global
Reference Clocks
PCIe Switch
SerDes Input
Port 0
PCIe Switch
SerDes Input
Port 2
PCIe Switch
SerDes Input
Port 4
PCIe Switch
SerDes Input
Port 6
PCIe Switch
SerDes Input
Port 8
PCIe Switch
SerDes Input
Port 12
Slave
SMBus Interface
Master
SMBus Interface
GCLKN[1:0]
GCLKP[1:0]
GCLKFSEL
P00CLKN
P00CLKP
PE00RP[3:0]
PE00RN[3:0]
P02CLKN
P02CLKP
PE02RP[3:0]
PE02RN[3:0]
P04CLKN
P04CLKP
PE04RP[3:0]
PE04RN[3:0]
P06CLKN
P06CLKP
PE06RP[3:0]
PE06RN[3:0]
P08CLKN
P08CLKP
PE08RP[3:0]
PE08RN[3:0]
PE12RP[3:0]
PE12RN[3:0]
System
Pins
Stack
Configuration
RSTHALT
PERSTN
SWMODE[3:0]
PE02TP[3:0]
PE02TN[3:0]
PCIe Switch
SerDes Output
Port 2
PE04TP[3:0]
PE04TN[3:0]
PCIe Switch
SerDes Output
Port 4
PE06TP[3:0]
PE06TN[3:0]
PCIe Switch
SerDes Output
Port 6
PE08TP[3:0]
PE08TN[3:0]
PCIe Switch
SerDes Output
Port 8
PE12TP[3:0]
PE12TN[3:0]
PCIe Switch
SerDes Output
Port 12
2
REFRES[5:0]
REFRESPLL
9
MSMBCLK
MSMBDAT
CLKMODE[1:0]
PCIe Switch
SerDes Output
Port 0
PES24NT6AG2
P12CLKN
P12CLKP
SSMBADDR[2,1]
SSMBCLK
SSMBDAT
PE00TP[3;0]
PE00TN[3:0]
GPIO[8:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
2
4
STK0CFG[0]
STK1CFG[0]
STK2CFG[0]
SerDes
Reference
Resistors
General Purpose
I/O
JTAG Pins
VDDCORE
VDDI/O
VDDPEA
Power/Ground
VDDPEHA
VDDPETA
VSS
Figure 3 PES24NT6AG2 Logic Diagram
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 16 and 15.
Parameter
Description
Condition
Min
Typical
Max
Unit
100
1251
MHz
RefclkFREQ
Input reference clock frequency range
TC-RISE
Rising edge rate
Differential
0.6
4
V/ns
TC-FALL
Falling edge rate
Differential
0.6
4
V/ns
VIH
Differential input high voltage
Differential
+150
VIL
Differential input low voltage
Differential
VCROSS
Absolute single-ended crossing point
voltage
Single-ended
VCROSS-DELTA
Variation of VCROSS over all rising clock
edges
Single-ended
VRB
Ring back voltage margin
Differential
-100
TSTABLE
Time before VRB is allowed
Differential
500
TPERIOD-AVG
Average clock period accuracy
-300
2800
ppm
TPERIOD-ABS
Absolute period, including spread-spectrum and jitter
9.847
10.203
ns
TCC-JITTER
Cycle to cycle jitter
150
ps
VMAX
Absolute maximum input voltage
+1.15
V
VMIN
Absolute minimum input voltage
-0.3
Duty Cycle
Duty cycle
40
Rise/Fall Matching
Single ended rising Refclk edge rate versus falling Refclk edge rate
ZC-DC
Clock source output DC impedance
mV
+250
-150
mV
+550
mV
+140
mV
+100
mV
ps
V
60
%
20
%
40
60
Table 11 Input Clock Requirements
1.
The input clock frequency will be either 100 or 125 MHz depending on signal GCLKFSEL.
AC Timing Characteristics
Parameter
Gen 1
Description
Gen 2
Min1
Typ1
Max1
Min1
Typ1
Max1
399.88
400
400.12
199.94
200
200.06
Units
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
TX Rise/Fall Time: 20% - 80%
TTX- IDLE-MIN
Minimum time in idle
0.75
0.75
0.125
ps
UI
UI
0.125
0.15
UI
20
20
UI
Table 12 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES24NT6AG2 Datasheet
Parameter
Gen 1
Description
1
Min
Typ1
TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending
an Idle ordered set
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
Gen 2
Max1
Min1
Typ1
Max1
Units
8
8
ns
8
8
ns
1.3
1.3
ns
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
TMIN-PULSED
Minimum Instantaneous Lone Pulse Width
NA
TTX-HF-DJ-DD
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
NA
0.15
UI
TRF-MISMATCH
Rise/Fall Time Differential Mismatch
NA
0.1
UI
200.06
ps
0.9
UI
PCIe Receive
UI
Unit Interval
399.88
400
400.12
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
TRX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation
0.3
TRX-SKEW
Lane to lane input skew
20
TRX-HF-RMS
1.5 — 100 MHz RMS jitter (common clock)
TRX-HF-DJ-DD
0.4
199.94
0.4
UI
UI
8
ns
NA
3.4
ps
Maximum tolerable DJ by the receiver (common clock)
NA
88
ps
TRX-LF-RMS
10 KHz to 1.5 MHz RMS jitter (common clock)
NA
4.2
ps
TRX-MIN-PULSE
Minimum receiver instantaneous eye width
NA
0.6
UI
Table 12 PCIe AC Timing Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1.
Note: Refclk jitter compliant to PCIe Gen2 Common Clock architecture is adequate for the GCLKN/P[x] and PE[x]CLKN/P pins of this IDT
PCIe switch. This same jitter specification is applicable when interfacing the switch to another IDT switch in a Separate (Non-Common)
Clock architecture.
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tpw_13b2
None
50
—
ns
See Figure 4.
GPIO
GPIO[8:0]1
Table 13 GPIO AC Timing Characteristics
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
EXTCLK
Tpw_13b
GPIO (asynchronous input)
Figure 4 GPIO AC Timing Waveform
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
50.0
—
ns
See Figure 5.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
JTAG_TDO
Tsu_16b
JTAG_TCK rising
Thld_16b
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 14 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2. The values for this symbol were determined by calculation, not by testing.
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
Recommended Operating Temperature
Grade
Temperature
Commercial
0C to +70C Ambient
Industrial
-40C to +85C Ambient
Table 15 PES24NT6AG2 Operating Temperatures
Recommended Operating Supply Voltages — Commercial Temperature
Symbol
Parameter
Minimum
Typical
Maximum
Unit
0.9
1.0
1.1
V
VDDCORE
Internal logic supply
VDDI/O
I/O supply except for SerDes
3.125
3.3
3.465
V
VDDPEA1
PCI Express Analog Power
0.95
1.0
1.1
V
PCI Express Analog High Power
2.25
2.5
2.75
V
VDDPETA
PCI Express Transmitter Analog Voltage
0.95
1.0
1.1
V
VSS
Common ground
0
0
0
V
VDDPEHA2
1
Table 16 PES24NT6AG2 Operating Voltages — Commercial Temperature
1. V PEA and V PETA should have no more than 25mV
DD
DD
peak-peak AC power supply noise superimposed on the 1.0V nominal DC
value.
2. V PEHA should have no more than 50mV
DD
peak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
Recommended Operating Supply Voltages — Industrial Temperature
Symbol
Parameter
Minimum
Typical
Maximum
Unit
0.9
1.0
1.1
V
VDDCORE
Internal logic supply
VDDI/O
I/O supply except for SerDes
3.125
3.3
3.465
V
VDDPEA1
PCI Express Analog Power
0.95
1.0
1.05
V
VDDPEHA2
VDDPETA1
PCI Express Analog High Power
2.25
2.5
2.75
V
PCI Express Transmitter Analog Voltage
0.95
1.0
1.1
V
VSS
Common ground
0
0
0
V
Table 17 PES24NT6AG2 Operating Voltages — Industrial Temperature
VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC
value.
1.
2.
VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
Power-Up/Power-Down Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages. The power-down sequence can occur in any order.
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 16
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 16 (and also listed below).
PCIe Analog
Supply
PCIe Analog
High Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465
mA
2260
3400
1343
1471
178
178
516
574
3
5
Watts
2.26
3.74
1.34
1.62
0.45
0.49
0.52
0.63
0.01
0.02
mA
2260
3400
1155
1265
178
178
268
299
3
5
Watts
2.26
3.74
1.16
1.39
0.45
0.49
0.27
0.33
0.01
.02
Number of Active
Lanes per Port
x8/x8/x4/x4
(Full Swing)
x8/x8/x4/x4
(Half Swing)
PCIe
Transmitter
Supply
Core Supply
I/O Supply
Total
Typ
Power
Max
Power
4.58
6.5
4.15
5.97
Table 18 PES24NT6AG2 Power Consumption
Note 1: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in VDDPEA, VDDPEHA, and
VDDPETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turnedoff port is close to zero. For example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 3/16 multiplied by the power consumption indicated in the above table.
Note 2: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: VDDPEA, VDDPEHA, and
VDDPETA.
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IDT 89HPES24NT6AG2 Datasheet
Thermal Considerations
This section describes thermal considerations for the PES24NT6AG2 (23mm2 FCBGA484 package). The data in Table 19 below contains information that is relevant to the thermal performance of the PES24NT6AG2 switch.
Symbol
Parameter
Value
TJ(max)
Junction Temperature
125
o
Maximum
70
o
Maximum for commercial-rated products
85
o
TA(max)
JA(effective)
Ambient Temperature
Effective Thermal Resistance, Junction-to-Ambient
Units
Conditions
C
C
C
Maximum for industrial-rated products
15.2
o
C/W
Zero air flow
8.5
o
C/W
1 m/S air flow
7.1
oC/W
2 m/S air flow
JB
Thermal Resistance, Junction-to-Board
3.1
oC/W
JC
Thermal Resistance, Junction-to-Case
0.15
oC/W
P
Power Dissipation of the Device
6.5
Watts
Maximum
Table 19 Thermal Specifications for PES24NT6AG2, 23x23 mm FCBGA484 Package
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value
specified in Table 19. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be
maintained below the value determined by the formula:
JA = (TJ(max) - TA(max))/P
Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to
achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value
provided in Table 19), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the
circuit board (number of layers and size of the board). It is strongly recommended that users perform their own thermal analysis for their own
board and system design scenarios.
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 16.
Note: See Table 10, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Description
Gen1
Min1
Typ1
Gen2
Max1
Min1
Typ1
Unit
Conditions
Max1
PCIe Transmit
VTX-DIFFp-p
Differential peak-to-peak output
voltage
800
1200
800
1200
mV
VTX-DIFFp-p-LOW
Low-Drive Differential Peak to
Peak Output Voltage
400
1200
400
1200
mV
VTX-DE-RATIO-
De-emphasized differential output
voltage
-3
-4
-3.0
-3.5
-4.0
dB
-5.5
-6.0
-6.5
dB
3.6
V
3.5dB
6.0dB
De-emphasized differential output
voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode
output voltage
VTX-DE-RATIO-
NA
0
3.6
0
20
mV
VTX-CM-DC-active- Abs delta of DC common mode
voltage between L0 and idle
idle-delta
100
100
mV
Abs delta of DC common mode
voltage between D+ and D-
25
25
mV
delta
VTX-Idle-DiffP
Electrical idle diff peak output
20
20
mV
RLTX-DIFF
Transmitter Differential Return
loss
10
10
dB
0.05 - 1.25GHz
8
dB
1.25 - 2.5GHz
RLTX-CM
Transmitter Common Mode
Return loss
6
6
dB
ZTX-DIFF-DC
DC Differential TX impedance
80
120
VTX-CM-ACpp
Peak-Peak AC Common
100
mV
VTX-DC-CM
Transmit Driver DC Common
Mode Voltage
3.6
V
600
mV
VTX-CM-DC-line-
100
NA
0
3.6
VTX-RCV-DETECT The amount of voltage change
allowed during Receiver Detection
ITX-SHORT
Transmitter Short Circuit Current
Limit
120
0
600
0
90
90
mA
Table 20 DC Electrical Characteristics (Part 1 of 3)
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December 17, 2013
IDT 89HPES24NT6AG2 Datasheet
I/O Type
Serial Link
(cont.)
Parameter
Description
Gen1
Min1
Typ1
Gen2
Max1
Min1
1200
120
Typ1
Unit
Conditions
Max1
PCIe Receive
VRX-DIFFp-p
Differential input voltage (peak-topeak)
175
RLRX-DIFF
Receiver Differential Return Loss
10
1200
mV
10
dB
0.05 - 1.25GHz
8
RLRX-CM
Receiver Common Mode Return
Loss
6
ZRX-DIFF-DC
Differential input impedance (DC)
80
100
ZRX--DC
DC common mode impedance
40
50
ZRX-COMM-DC
Powered down input common
mode impedance (DC)
200k
350k
1.25 - 2.5GHz
6
dB
120
Refer to return loss spec
60
40
60
50k
ZRX-HIGH-IMP-DC- DC input CM input impedance for
V>0 during reset or power down
POS
50k
50k
ZRX-HIGH-IMP-DCNEG
DC input CM input impedance for
V
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