74ALVCH162245

IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS AND BUS-HOLD .EATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages IDT74ALVCH162245 DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. The ALVCH162245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The ALVCH162245 has series resistors in the device out-put structure of the “A” port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The “B” port has a ±24mA driver. The ALVCH162245 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE .EATURES: • Balanced Output Drivers: ±12mA (A port) • High Output Drivers: ±24mA (B port) APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems .UNCTIONAL BLOCK DIAGRAM 1 D IR 1 2 D IR 48 24 25 1 OE 1A 1 47 2 46 3 44 5 43 6 41 8 40 9 38 11 2 OE 2A 1 1B 1 2A 2 1B 2 2A 3 1B 3 2A 4 1B 4 2A 5 1B 5 2A 6 1B 6 2A 7 1B 7 2A 8 12 36 13 35 14 33 16 32 17 30 19 29 20 27 22 2B 1 1A 2 2B 2 1A 3 2B 3 1A 4 2B 4 1A 5 2B 5 1A 6 2B 6 1A 7 2B 7 1A 8 37 26 1B 8 23 2B 8 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 © 1999 Integrated Device Technology, Inc. APRIL 1999 DSC-4748/1 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE PIN CON.IGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max –0.5 to +4.6 –0.5 to VCC+0.5 –65 to +150 –50 to +50 ±50 –50 ±100 Unit V V °C mA mA mA mA 1 DIR 1B 1 1B 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 OE 1A 1 1A 2 GND 1B 3 1B 4 GND 1A 3 1A 4 V CC 1B 5 1B 6 V CC 1A 5 1A 6 GND 1B 7 1B 8 2B 1 2B 2 GND 1A 7 1A 8 2A 1 2A 2 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF GND 2B 3 2B 4 GND 2A 3 2A 4 NOTE: 1. As applicable to the device type. V CC 2B 5 2B 6 V CC 2A 5 2A 6 PIN DESCRIPTION Pin Names x OE DIR xAx(1) xBx(1) Description Output Enable Inputs (Active LOW) Direction Control Inputs Side A Inputs or 3-State Outputs Side B Inputs or 3-State Outputs GND 2B 7 2B 8 2 DIR GND 2A 7 2A 8 2 OE NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. SSOP/ TSSOP/ TVSOP TOP VIEW .UNCTION TABLE (EACH 8-BIT SECTION)(1) Inputs xOE L L H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care xDIR L H X Outputs B data to A bus A data to B bus Isolation 2 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ∆ICC Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = –18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 — — — — — — — — — Typ.(1) — — — — — — — — –0.7 100 0.1 Max. — — 0.7 0.8 ±5 ±5 ±10 ±10 –1.2 — 40 V mV µA µA µA µA V Unit V Quiescent Power Supply Current Variation — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V Min. – 75 75 – 45 45 — Typ.(2) — — — — — Max. — — — — ±500 Unit µA µA µA 3 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS (A PORT) Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = – 0.1mA IOH = – 4mA IOH = – 6mA IOH = – 4mA IOH = – 8mA IOH = – 6mA IOH = – 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC – 0.2 1.9 1.7 2.2 2 2.4 2 — — — — — — — Max. — — — — — — — 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OUTPUT DRIVE CHARACTERISTICS (B PORT) Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = – 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA IOH = – 12mA Min. VCC – 0.2 2 1.7 2.2 2.4 2 — — — — — Max. — — — — — — 0.2 0.4 0.7 0.4 0.55 V Unit V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 23 4 VCC = 3.3V ± 0.3V Typical 30 5 Unit pF 4 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS (A PORT)(1) VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xBx to xAx Output Enable Time xOE to xAx Output Disable Time xOE to xAx Output Skew(2) 1 6.3 1 6.8 Min. 1 Max. 4.9 Min. VCC = 2.7V Max. 4.7 6.7 5.7 VCC = 3.3V ± 0.3V Min. 1 1 1 Max. 4.2 5.6 5.5 500 Unit ns ns ns ps — — — — — — — — NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. SWITCHING CHARACTERISTICS (B PORT)(1) VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xBx Output Enable Time xOE to xBx Output Disable Time xOE to xBx Output Skew(2) 1 5.2 1 5.7 Min. 1 Max. 3.7 Min. VCC = 2.7V Max. 3.6 5.4 4.6 VCC = 3.3V ± 0.3V Min. 1 1 1 Max. 3 4.4 4.1 500 Unit ns ns ns ps — — — — — — — — NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 5 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE V IH VT 0V V OH VT V OL V IH VT 0V ALVC Link TEST CIRCUITS AND WAVE.ORMS TEST CONDITIONS Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 V CC 500 Ω Pulse Generator (1, 2) SAME PHASE INPUT TRANSITION VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF V LOAD Open GND tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 6 2.7 1.5 300 300 50 tPHL Propagation Delay ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH V LOAD/2 VT tPHZ VT 0V tPLZ DISABLE V IH VT 0V V LOAD/2 V LZ V OL V OH V HZ 0V ALVC Link V IN D.U.T. V OUT RT 500 Ω CL A LVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. V IH DATA VT INPUT 0V tSU tH V IH TIMING VT INPUT 0V tREM V IH ASYNCHRONOUS VT CONTROL 0V V IH SYNCHRONOUS VT CONTROL tSU 0V tH ALVC Link SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open V IH INPUT VT 0V V OH OUTPUT 1 VT V OL V OH OUTPUT 2 tPLH2 tPHL2 ALVC Link Set-up, Hold, and Release Times tPLH1 tPHL1 LOW-HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT tSK (x) tSK (x) VT V OL VT ALVC Link Pulse Width tSK (x) = tPLH2 - tPLH1 o r tPHL2 - tPHL1 Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH162245 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING IN.ORMATION IDT XX ALVC X XX Fam ily XXX Device Type XX Package Tem p. R ange Bus-Hold PV PA PF 245 Shrink Sm all O utline P ackage Thin Shrink Sm all O utline Package Thin Very Sm all O utline Package 16-Bit Bus Transceiver with 3-State O utputs 162 Double-Density with Resistors, ±12m A (A port) ± 24m A (B port) Bus-Hold – 40°C to +85°C H 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 7