82V3391

SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 Product Brief 82V3391 FEATURES HIGHLIGHTS • Single chip PLL: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE) • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks) • Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments • Provides clocks for 1 Gigabit and 10 Gigabit Ethernet application • Supports clock generation for IEEE-1588 applications Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, Stratum 4E, Stratum 4, SMC, EEC-Option 1 and EEC-Option 2 Clocks Supports 1PPS input and output Employs PLL architecture to feature excellent jitter performance and minimize the number of external components Integrates T4 DPLL and T0 DPLL; T4 DPLL locks independently or locks to T0 DPLL Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy Supports hitless reference switching to minimize phase transients on T0 DPLL output to be no more than 0.61 ns Supports programmable input-to-output phase offset adjustment Limits the phase and frequency offset of the outputs Provides OUT1~OUT7 output clocks whose frequency cover from 1PPS to 644.53125 MHz • Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS outputs • Includes 25.78125 MHz, 128.90625 MHz and 161.1328125 MHz for CMOS outputs • Includes 25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential outputs • Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, 322.265625 MHz and 644.53125 MHz for differential outputs Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/ 2.048 MHz (BITS/SSU) Provides IN1 and IN2 for composite clocks • • • • • • • • • • • • • MAIN FEATURES • • • • • • • • • • Provides IN3~IN14 input clocks whose frequencies cover from 2 kHz to 625 MHz • Includes 25MHz, 125 MHz and 156.25 MHz for CMOS inputs • Includes 25MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential inputs Internal DCO can be controlled by an external processor to be used for IEEE-1588 clock generation Supports Forced or Automatic operating mode switch controlled by an internal state machine. Automatic mode switch supports FreeRun, Locked and Holdover modes Supports manual and automatic selected input clock switch Supports automatic hitless selected input clock switch on clock failure Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2 kHz or 8 kHz frame sync output signal Provides a 1PPS sync Input signal, and a 1PPS sync output signal Provides output clocks for BITS, GPS, 3G, GSM, etc. Supports AMI, PECL/LVDS and CMOS input/output technologies Supports master clock calibration Supports Master/Slave application (two chips used together) to enable system protection against single chip failure Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recommendations Multiple microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola, I2C and Serial IEEE 1149.1 JTAG Boundary Scan Single 3.3 V operation with 5 V tolerant CMOS I/Os 100-pin TQFP package, green package options available 1 Gigabit Ethernet and 10 Gigabit Ethernet BITS / SSU SMC / SEC (SONET / SDH) DWDM cross-connect and transmission equipment Synchronous Ethernet equipment Central Office Timing Source and Distribution Core and access IP switches / routers Gigabit and Terabit IP switches / routers IP and ATM core switches and access equipment Cellular and WLL base-station node clocks Broadband and multi-service access equipment OTHER FEATURES • • • • • • • • • • • • • • • APPLICATIONS • • IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1  2012 Integrated Device Technology, Inc. March 5, 2012 DSC-7238/- IDT82V3391 PRODUCT BRIEF SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588 DESCRIPTION The IDT82V3391 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, Stratum 4E, Stratum 4, SMC, EEC-Option1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device supports several types of input clock sources: recovered clock from Synchronous Ethernet, STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH / Synchronous Ethernet network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 path. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. There are 2 high performance APLLs that can be used for low jitter SONET and Ethernet Clocks The device provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A highly stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a microprocessor interface. The device supports six microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola, I2C and Serial. In general, the device can be used in Master/Slave application. In this application, two devices should be used together to enable system protection against single chip failure. Description 2 March 5, 2012 12 OUT1 MUX Divider OUT1 Functional Block Diagram T4 DPLL 77.76 MHz Divider 12 OUT2 MUX OUT2 IDT82V3391 PRODUCT BRIEF GSM/GPS/16E1/16T1 12 T4 Input Selector MUX T4 PFD & LPF 16E1/16T1 OUT3 MUX Divider OUT3 Input 12 OUT4 MUX Divider 12E1/24T1/E3/T3 Divider OUT4 IN1 ETH Input Pre-Divider Priority IN2 Input Pre-Divider Priority IN3 12 T0 77.76 MHz T4 APLL Input Pre-Divider Priority FUNCTIONAL BLOCK DIAGRAM IN4 Input Pre-Divider Priority IN5 T4 APLL MUX Input Pre-Divider Priority IN6 Monitors T0 8 kHz 8 k Divider Input Pre-Divider Priority OUT5 MUX Divider OUT5 IN7 Input Pre-Divider Priority IN8 Input Pre-Divider Priority IN9 77.76 MHz Input Pre-Divider Priority SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588 3 GSM/OBSAI/16E1/16T1 12 IN10 Input Pre-Divider Priority Input Pre-Divider Priority OUT6 MUX Divider OUT6 Input Pre-Divider Priority IN11 IN12 IN13 T0 APLL MUX Input Pre-Divider Priority IN14 16E1/16T1 Phase Offset T0 Input Selector T0 PFD & LPF 12E1/GPS/E3/T3 ETH Input Pre-Divider Priority T0 APLL 12 EX_SYNC1 Selection OUT7 MUX Divider OUT7 From T0 77.76 MHz From T4 77.76 MHz From T0 16E1/16T1 OUT8 MUX Auto Divider OUT8 Divider T0 DPLL From T4 16E1/16T1 OUT9 MUX Auto Divider OUT9 Auto Divider Auto Divider FRSYNC_8K_1PPS MFRSYNC_2K_1PPS Output APLL Microprocessor Interface JTAG March 5, 2012 OSCI IDT82V3391 DATASHEET SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588 ORDERING INFORMATION XXXXXXX Device Type XX X Process / Temperature Range Blank Industrial (- 40 °C to+ 85 °C) EQG Green Thin Quad Flatpack ( TQFP, EQG100) 82V3391B WAN PLL 4 March 5, 2012 IDT82V3391 PRODUCT BRIEF SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588 We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved. 5 March 5, 2012