AV9107C-17

Integrated Circuit Systems, Inc. AV9107C-17 CPU Frequency Generator General Description The AV9107C-17 o ffers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output frequency which is the same as the input reference crystal (or clock). The other clock, CLK1, can vary between 25.06 and 33.29 MHz. The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A mini-mum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitter-free operation. Features • • • • • • • • Patented on-chip Phase-Locked Loop with VCO for clock generation Provides reference clock and synthesized clock Generates frequencies of 25 and 33 MHz 8-pin DIP or SOIC package 14.318 MHz input reference frequency On-chip loop filter Low power CMOS technology Single +3.3 or +5 volt power supply Applications Computer: The AV9107C-17 i s the ideal solution for replacing high speed oscillators and for reducing clock speeds to save power in computers. The device provides smooth, glitch-free frequency transitions so that the CPU can continue to operate during slow down or speed up. The rate of frequency change makes the AV9107C-17 compatible with all 386DX, 386SX, 486DX, 486DX2, and 486SX devices. Block Diagram AV 9107-17 RevC052197P AV9107C-17 Pin Configuration Functionality (at 14.318) MHz reference frequency input) FS 0 1 CLK1 25.06 MHz 33.29 MHz 8-Pin DIP, SOIC Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME FS0 GND X1/ICLK X2 OE CLK1 VDD REFCLK TYPE Input Input DESCRIPTION Frequency Select 0 for CLK1. Digital Ground. Crystal Output or Input Clock frequency. Typically 14.318 MHz system clock. Output Crystal Output (No Connect when clock used.). Input Output Enable. Tristates CLK1 and REFCLK when low. Has internal pull-up. Output Clock 1 Output (see decoding tables). Digital power supply (+5V DC). Reference Clock output. Produces a buffered version of the input clock or crystal frequency Output (typically 14.318 MHz). - Frequency Transitions A key AV9107C-17 feature is the ability to provide glitchfree frequency transitions between its output frequencies. Output Enable The Output Enable feature tristates the specified output clock pins. This places the selected output pin in a high impedance state to allow for system level diagnostic testing. Absolute Maximum Ratings AVDD, VDD referenced to GND . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 2 AV9107C-17 Electrical Characteristics at 5.0V Operating VDD = +4.5V to +5.5V; TA =0°C to 70°C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input Low Current Input High Current Output Low Voltage, Note 1 Output High Voltage, Note 1 Output Low Current, Note 1 Output High Current, Note 1 Supply Current Supply Current; Power-down (-03 only) Supply Current; Power-down (-03 only) Supply Current; Slow Clock (-11 only) Pull-up Resistor, Note 1 Rise Time 0.8 to 2.0V, Note 1 Fall Time 2.0 to 0.8V, Note 1 Rise Time 20% to 80%, Note 1 Fall Time 80% to 20%, Note 1 Duty Cycle, Note 1 Jitter, One Sigma, Note 1 Jitter, One Sigma, Note 1 Jitter, One Sigma, Note 1 Jitter, Absolute, Note 1 Jitter, Absolute, Note 1 Jitter, Absolute, Note 1 Input Frequency, Note 1 Output Frequency Power-up Time, Note 1 Transition Time, Note 1 SYMBOL VIL VIH IIL IIL IIH VOL VOH IOL IOH IDD IDD (PD low) IDD (PD low) IDD (Slow Clock low) Rpu Tr Tf Tr Tf Dt Tjis Tjis Tjis Tjab Tjab Tjab Fi Fo Tpu Tft TEST CONDITIONS MIN 2.0 -2.0 -2.0 2.4 22.0 - TYP 6.0 MAX 0.8 16.0 2.0 UNITS V V µA µA µA V V mA mA mA µA µA µA k ohms ns ns ns ns % ps ps % ps ps % MHz MHz ms ms VIN=0V (Pull-up input) VIN=0V (Input with no pull-up) VIN=V DD IOL=10mA IOH=-30mA VOL=0.8V VOH=2.0V Unload, 50 Mhz Unload, Logic Inputs 000 Unload, Logic Inputs 111 Unloaded, Slow Clock pin low 0.15 3.25 35.0 -50.0 18.0 38.0 14.0 5.5 380.0 0.60 0.40 2.0 1.0 50.0 50.0 100.0 0.2 2.0 0.40 -35.0 42.0 100.0 40.0 9.0 700.0 1.40 1.00 3.5 2.5 55.0 150.0 200.0 1.0 250.0 500.0 3.0 19.0 120.0 18.0 13.0 AC Characteristics 15pF 15pF 15pF 15pF load load load load 45.0 - 15pF load @1.4V From 20 to 100 Mhz From 14 to 16 Mhz From 14 to Below From 20 to 100 Mhz From 14 to 16 Mhz From 14 to Below -250.0 -500.0 11.0 2.0 1.0 14.3 7.58 6.0 25 to 33.3 Mhz Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 AV9107C-17 Electrical Characteristics at 3.3V Operating VDD = +3.0V to +3.7V; TA =0°C to 70°C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input Low Current Input High Current Output Low Voltage, Note 1 Output High Voltage, Note 1 Output Low Current, Note 1 Output High Current, Note 1 Supply Current Supply Current; Power-down (-03 only) Supply Current; Power-down (-03 only) Supply Current; Slow Clock (-11 only) Pull-up Resistor Rise Time 20% to 80%, Note 1 Fall Time 80% to 20%, Note 1 Duty Cycle, Note 1 Jitter, One Sigma, Note 1 Jitter, One Sigma, Note 1 Jitter, One Sigma, Note 1 Jitter, Absolute, Note 1 Jitter, Absolute, Note 1 Jitter, Absolute, Note 1 Input Frequency, Note 1 Output Frequency, Note 1 Power-up Time, Note 1 Transition Time, Note 1 SYMBOL VIL VIH IIL IIL IIH VOL VOH IOL IOH IDD IDD (PD low) IDD (PD low) IDD (Slow Clock low) Rpu Tr Tf Dt Tjis Tjis Tjis Tjab Tjab Tjab Fi Fo Tpu Tft TEST CONDITIONS MIN 0.7VDD -2.0 -2.0 0.85 15.0 - TYP 2.5 0.15 0.92 22.0 -17.0 22.0 13.0 4.0 3.5 550.0 2.2 1.2 46.0 50.0 100.0 0.4 MAX 0.20V DD 7.0 2.0 2.0 0.1 -10.0 40.0 40.0 12.0 6.0 900.0 3.5 2.5 53.0 150.0 200.0 1.0 250.0 500. 3.0 15.3 66.6 18.0 13.0 UNITS V V µA µA µA V V mA mA mA µA µA mA k ohms ns ns % ps ps % ps ps % MHz MHz ms ms VIN=0V (Pull-up input) VIN=0V (Input with no pull-up) VIN=VDD IOL=6mA IOH=-5mA VOL=0.2VDD VOL=0.7VDD Unloaded, 50 Mhz Unload, Logic Inputs 000 Unload, Logic Inputs 111 Unloaded, Slow Clock pin low AC Characteristics 15pF load 15pF load 15pF load @ 50% From 25 to 66 Mhz From 14 to 20 Mhz From From From From 14 25 14 14 to to to to Below 66 Mhz 20 Mhz Below 40.0 - -250.0 -500.0 13.3 2.0 1.0 14.3 7.58 6.0 25 to 33.3 Mhz Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 AV9107C-17 8-Pin DIP Package 8-Pin Plastic SOIC Package Ordering Information AV9107C-17CN08 or AV9107C-17CS08 Example: XXX XXXX-PPP M X#W Lead Count & Package Width Lead Count=1, 2 or 3 digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type N=DIP (Plastic) S=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 5