IDT72205LB15G

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Integrated Device Technology, Inc. IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB FEATURES: • • • • • • • • • • • • • • • • 256 x 18-bit organization array (IDT72205LB) 512 x 18-bit organization array (IDT72215LB) 1,024 x 18-bit organization array (IDT72225LB) 2,048 x 18-bit organization array (IDT72235LB) 4,096 x 18-bit organization array (IDT72245LB) 10 ns read/write cycle time Empty and Full flags signal FIFO status Easily expandable in depth and width Asynchronous or coincident read and write clocks Programmable Almost-Empty and Almost-Full flags with default settings Half-Full flag capability Dual-Port zero fall-through time architecture Output enable puts output data bus in high-impedance state High-performance submicron CMOS technology Available in a 64-lead thin quad flatpack (TQFP/STQFP) and plastic leaded chip carrier (PLCC) Industrial temperature range (–40°C to +85°C) is available DESCRIPTION: The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used in a single device configuration. These devices are depth expandable using a Daisy-Chain technique. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated using IDT’s high-speed submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM WCLK D0-D17 INPUT REGISTER OFFSET REGISTER WRITE CONTROL LOGIC WRITE POINTER • • RAM ARRAY 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 • • FLAG LOGIC /( READ POINTER READ CONTROL LOGIC ) ( )/ EXPANSION LOGIC OUTPUT REGISTER RESET LOGIC Q0-Q17 SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc RCLK 2766 drw 01 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2000 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. MAY 2000 DSC-2766/- 1 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges PIN CONFIGURATIONS D15 D16 D17 GND RCLK VCC GND VCC Q17 Q16 GND Q15 D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 10 60 1 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 WCLK Q0 Q1 GND Q2 Q3 VCC VCC / VCC Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND Q4 2766 drw 02 PLCC (J68-1, order code: J) TOP VIEW D16 D17 GND RCLK VCC GND PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 WCLK Q0 Q1 GND Q2 Q3 VCC / 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Q17 Q16 GND Q15 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC 2766 drw 03 TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW 2 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges PIN DESCRIPTION Symbol D0–D17 Name Data Inputs Reset I/O I I Data inputs for a 18-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full. When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW. When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty. Description RS WCLK Write Clock Write Enable I I WEN RCLK Read Clock Read Enable I I REN OE LD When REN is LOW and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. Output Enable Load I I FL WXI RXI FF EF PAE PAF WXO/HF RXO Q0–Q17 VCC GND When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-toHIGH transition of the RCLK, when REN is LOW. First Load I In the single device or width expansion configuration, FL is grounded. In the depth expansion configuration, FL is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain. In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration, WXI is connected to WXO (Write Expansion Out) of the previous device. Write Expansion Read Expansion Full Flag Empty Flag Programmable Almost-Empty Flag Programmable Almost-Full Flag Write Expansion Out/Half-Full Flag Read Expansion Out Data Outputs Power Ground I I O O O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB. In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous device. O When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The default offset at reset is 31 from full for IDT72205LB, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/72245LB. In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the FIFO is written. O O O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location in the FIFO is read. Data outputs for a 18-bit bus. +5V power supply pins. Eight ground pins for the PLCC and seven pins for the TQFP/STQFP. 3 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges ABSOLUTE MAXIMUM RATINGS Symbol VTERM TSTG IOUT Rating Terminal Voltage with respect to GND Storage Temperature DC Output Current Com'l & Ind'l –0.5 to +7.0 –55 to +125 –50 to +50 Unit V °C mA RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Supply Voltage VCC Com'l/Ind'l GND VIH VIL(1) TA TA Supply Voltage Input High Voltage Com'l/Ind'l Input Low Voltage Com'l/Ind'l Operating Temperature Commercial Operating Temperature Industrial Min. 4.5 0 2.0 — 0 –40 Typ. 5.0 0 — — — — Max. Unit 5.5 V 0 — 0.8 70 85 V V V °C °C 2766 tbl 03 NOTE: 2766 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0 °C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C ) IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB Commercial and Industrial(1) tCLK = 10, 15, 25 ns Min. Typ. –1 –10 2.4 — — — — — — — — — Symbol ILI(2) ILO(3) VOH VOL ICC1(4,5,6) ICC2(4,7) Parameter Input Leakage Current (any input) Output Leakage Current Output Logic “1” Voltage, IOH = –2 mA Output Logic “0” Voltage, IOL = 8 mA Active Power Supply Current Standby Current Max. 1 10 — 0.4 60 5 Unit µA µA V V mA mA 2766 tbl 04 NOTES: 1. Industrial temperature range product for the 15ns and the 25 ns speed grade is available as a standard device. 2. Measurements with 0.4 ≤ VIN ≤ VCC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC . 4. Tested with outputs open (IOUT = 0). 5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz. 6. For the 72205/72215/72225 the typical ICC1 = 1.81 + 1.12*fS + 0.02*C L*fS (in mA); for the 72235/72245 the typical ICC1 = 2.85 + 1.30*fS + 0.02*CL*fS (in mA). These equations are valid under the following conditions: VCC = 5V, T A = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN (2) AC TEST CONDITIONS Unit pF pF 2766 tbl 05 Parameter (1) Conditions VIN = 0V VOUT = 0V Max. 10 10 Input Capacitance Output Capacitance COUT(1,2) Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 2766 tbl 06 NOTES: 1. With output deselected, (OE ≥ VIH). 2. Characterized values, not currently tested. 4 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40 °C to +85°C) Commercial 72205LB10 72215LB10 72225LB10 72235LB10 72245LB10 Min. Max. — 2 10 4.5 4.5 3 0 3 0 10 8 8 — 0 3 3 — — — — — — 3 3.5 5 5 Low-Z(3) 100 6.5 — — — — — — — — — — 15 — 6 6 6.5 6.5 17 17 17 6.5 — — — — Com'l & Ind'l(1) 72205LB15 72205LB25 72215LB15 72215LB25 72225LB15 72225LB25 72235LB15 72235LB25 72245LB15 72245LB25 Min. Max. Min. Max. — 2 15 6 6 4 1 4 1 15 10 10 — 0 3 3 — — — — — — 6.5 5 6 6 66.7 10 — — — — — — — — — — 20 — 8 8 10 10 24 24 24 10 — — — — — 2 25 10 10 6 1 6 1 25 15 15 — 0 3 3 — — — — — — 10 10 10 10 40 15 — — — — — — — — — — 25 — 12 12 15 15 26 26 26 15 — — — — Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tHF tXO tXI tXIS tSKEW1 tSKEW2 Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(2) Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Output Enable to Output Valid Output Enable to Output in High-Z(3) Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Empty Flag Clock to Half-Full Flag Clock to Expansion Out Expansion In Pulse Width Expansion In Set-Up Time Skew time between Read Clock & Write Clock for Full Flag Skew time between Read Clock & Write Clock for Empty Flag Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Industrial temperature range is available as standard product for the 15ns and the 25ns speed grade. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 2766 tbl 07 5V 1.1K D.U.T. 680Ω 30pF* 2766 drw 04 Figure 1. Output Load * Includes jig and scope capacitances. 5 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges SIGNAL DESCRIPTIONS: INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. OUTPUT ENABLE (OE) When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When OE is disabled (HIGH), the Q output data bus is in a highimpedance state. LOAD (LD) The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices contain two 12-bit offset registers with data on the inputs, or read on the outputs. When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and (WEN) are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register. However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FF), Half-Full Flag (HF) and Programmable AlmostFull Flag (PAF) will be reset to HIGH after tRSF. The Empty Flag (EF ) and Programmable Almost-Empty Flag (PAE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. WRITE CLOCK (WCLK) A write cycle is initiated on the LOW-to-HIGH transition of the write clock (WCLK). Data set-up and hold times must be met with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coincident. WRITE ENABLE (WEN ) When the WEN input is LOW and LD input is HIGH, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored when the FIFO is full. READ CLOCK (RCLK) Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK), when Output Enable (OE) is set LOW. The write and read clocks can be asynchronous or coincident. READ ENABLE (REN) When Read Enable is LOW and LD input is HIGH, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. Every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated on the rising edge of RCLK. LD 0 WEN 0 WCLK Selection Writing to offset registers: Empty Offset Full Offset 0 1 1 1 0 1 No Operation Write Into FIFO No Operation NOTE: 2766 tbl 08 1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register 17 11 EMPTY OFFSET REGISTER DEFAULT VALUE 001FH (72205) 003FH (72215): 007FH (72225/72235/72245) 0 17 11 FULL OFFSET REGISTER DEFAULT VALUE 001FH (72205) 003FH (72215): 007FH (72225/72235/72245) 0 2766 drw 05 NOTE: 1. Any bits of the offset register not being programmed should be set to zero. Figure 3. Offset Register Location and Default Values 6 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). The act of reading the control registers employs a dedicated read offset register pointer. (The read and write pointers operate independently). A read and a write should not be performed simultaneously to the offset registers. FIRST LOAD (FL) FL is grounded to indicate operation in the Single Device or Width Expansion mode. In the Depth Expansion configuration, FL is grounded to indicate it is the first device loaded and is set to HIGH for all other devices in the Daisy Chain. (See Operating Configurations for further details.) WRITE EXPANSION INPUT (WXI) This is a dual purpose pin. WXI is grounded to indicate operation in the Single Device or Width Expansion mode. WXI is connected to Write Expansion Out (WXO) of the previous device in the Daisy Chain Depth Expansion mode. READ EXPANSION INPUT (RXI) This is a dual purpose pin. RXI is grounded to indicate operation in the Single Device or Width Expansion mode. RXI is connected to Read Expansion Out (RXO) of the previous device in the Daisy Chain Depth Expansion mode. EMPTY FLAG (EF) When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. The EF is updated on the LOW-to-HIGH transition of the read clock (RCLK). PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full Flag (PAF) will go LOW when FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the PAF will go LOW after (256-m) writes for the IDT72205LB, (512-m) writes for the IDT72215LB, (1,024-m) writes for the IDT72225LB, (2,048–m) writes for the IDT72235LB and (4,096–m) writes for the IDT72245LB. The offset “m” is defined in the FULL offset register. If there is no Full offset specified, the PAF will be LOW when the device is 31 away from completely full for IDT72205LB, 63 away from completely full for IDT72215LB, and 127 away from completely full for IDT72225LB/72235LB/72245LB. The PAF is asserted LOW on the LOW-to-HIGH transition of the write clock (WCLK). PAF is reset to HIGH on the LOWto-HIGH transition of the read clock (RCLK). Thus PAF is asynchronous. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty Flag (PAE) will go LOW when the read pointer is “n+1” locations less than the write pointer. The offset “n” is defined in the EMPTY offset register. If there is no Empty offset specified, the Programmable Almost-Empty Flag (PAE) will be LOW when the device is 31 away from completely empty for IDT72205LB, 63 away from completely empty for IDT72215LB, and 127 away from completely empty for IDT72225LB/72235LB/72245LB. The PAE is asserted LOW on the LOW-to-HIGH transition of the read clock (RCLK). PAE is reset to HIGH on the LOWto-HIGH transition of the write clock (WCLK). Thus PAE is asynchronous. WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF) This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion In (WXI) and Read Expansion In (RXI) are grounded, this output acts as an indication of a half-full memory. OUTPUTS: FULL FLAG (FF ) When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72205LB, 512 for the IDT72215LB, 1,024 for the IDT72225LB, 2,048 for the IDT72235LB and 4,096 for the IDT72245LB. The FF is updated on the LOW-to-HIGH transition of the write clock (WCLK). TABLE I — STATUS FLAGS 72205 0 1 to n (1) 72215 0 1 to n(1) Number of Words in FIFO Memory 72225 72235 0 1 to n(1) (n + 1) to 512 (1,024-m)(2) to 1,023 0 1 to n(1) (n + 1) to 1,024 (2,048-m)(2) to 2,047 72245 0 1 to n(1) (n + 1) to 2,048 (4,096-m)(2) to 4,095 FF PAF HF PAE EF H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H (n + 1) to 128 (256-m) (2) (n + 1) to 256 (512-m)(2) 512 to 511 129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1,024-(m+1)) 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1)) to 255 256 1,024 2,048 4,096 NOTES: 1. n = Empty Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127) 2. m = Full Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127) 2766 tbl 09 7 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag ( HF) is then reset to HIGH by the LOW-to-HIGH transition of the read clock (RCLK). The HF is asynchronous. In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device writes to the last location of memory. READ EXPANSION OUT (RXO) In the Daisy Chain Depth Expansion configuration, Read Expansion In (RXI ) is connected to Read Expansion Out (RXO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device reads from the last location of memory. DATA OUTPUTS (Q0-Q17) Q0-Q17 are data outputs for 18-bit wide data. t RS tRSS , , t RSF , t RSF , , t RSF Q0 - Q17 t RSR = 1(1) =0 2766 drw 06 NOTES: 1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 2. The clocks (RCLK, WCLK) can be free-running during reset. Figure 4. Reset Timing(2) 8 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges t CLK t CLKH WCLK t DS D0 - D17 DATA IN VALID t CLKL t DH t ENH t ENS NO OPERATION t WFF t WFF t SKEW1(1) RCLK 2766 drw 07 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 5. Write Cycle Timing t CLK t CLKH RCLK t ENS t ENH NO OPERATION t CLKL t REF tA Q0 - Q17 t OLZ t OE t SKEW2 WCLK (1) t REF VALID DATA t OHZ 2766 drw 08 NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle Timing 9 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges WCLK t DS D0 - D17 t ENS D0 (first valid write) D1 D2 D3 D4 t FRL(1) t SKEW2 RCLK t REF tENS tA Q0 - Q17 t OLZ t OE D0 tA D1 NOTES: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, t FRL (maximum) = either 2*tCLK + tSKEW2 or t CLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 2. The first word is available the cycle after EF goes HIGH, always. Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write 2766 drw 09 NO WRITE NO WRITE WCLK t SKEW1 D0 - D17 (1) t DS DATA WRITE t WFF t WFF t SKEW1 (1) t DS DATA WRITE t WFF RCLK t ENS t ENH t ENS t ENH LOW tA Q0 - Q17 DATA IN OUTPUT REGISTER DATA READ tA NEXT DATA READ 2766 drw 10 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 8. Full Flag Timing 10 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges WCLK tDS D0 - D17 tENS DATA WRITE 1 tENH (1) tDS DATA WRITE 2 tENS tENH tFRL tSKEW2 tREF tREF tREF (1) tSKEW2 RCLK tFRL LOW tA Q0 - Q17 DATA IN OUTPUT REGISTER DATA READ 2766 drw 11 NOTE: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + t SKEW2, or t CLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW). Figure 9. Empty Flag Timing tCLK tCLKH WCLK tENS LD tENS WEN tDS D0–D15 PAE OFFSET PAF OFFSET D0–D11 2766 drw 12 tCLKL tENH tDH PAE OFFSET Figure 10. Write Programmable Registers tCLKH RCLK tCLK tCLKL tENS tENH tENS tA Q0–Q15 UNKNOWN PAE OFFSET PAF OFFSET PAE OFFSET 2766 drw 13 Figure 11. Read Programmable Registers 11 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges tCLKH WCLK tCLKL tENS tENH tPAE n + 1 words in FIFO n words in FIFO tPAE RCLK tENS NOTE: 1. n = PAE offset. Number of data words written into FIFO already = n. Figure 12. Programmable Almost-Empty Flag Timing 2766 drw 14 tCLKH WCLK tCLKL (1) tENS tENH tPAF D – m + 1 words in FIFO memory (1) D – m words (2) in FIFO memory tPAF D – m + 1 words in FIFO memory (1) RCLK tENS 2766 drw 15 NOTES: 1. m = PAF offset. D = maximum FIFO Depth. Number of data words written into FIFO memory = 256 - m + 1 for the IDT72205, 512 -m + 1 for the IDT72215, 1,024 - m + 1 for the IDT72225, 2,048 - m + 1 for the IDT72235 and 4,096 - m + 1 for the IDT72245. 2. 256 - m words in IDT72205, 512 - m words in IDT72215, 1,024 - m words in IDT72225, 2,048 - m words in IDT72235 and 4,096 - m words in IDT72245. Figure 13. Programmable Almost-Full Flag Timing tCLKH WCLK tCLKL tENH tENS tHF D/2 words in FIFO memory (1) D/2 + 1 words in FIFO memory(2) tHF D/2 words in FIFO memory(1) RCLK tENS 2766 drw 16 NOTE: 1. D = maximum FIFO Depth = 256 words for the IDT72205, 512 words for the IDT72215, 1,024 words for the IDT72225, 2,048 words for the IDT72235 and 4,096 words for the IDT72245. Figure 14. Half-Full Flag Timing 12 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges t CLKH WCLK Note 1 t XO t XO t ENS 2766 drw 17 NOTE: 1. Write to Last Physical Location. Figure 15. Write Expansion Out Timing t CLKH RCLK Note 1 t XO t XO t ENS 2766 drw 18 NOTE: 1. Read from Last Physical Location. Figure 16. Read Expansion Out Timing t XI t XIS WCLK 2766 drw 19 Figure 17. Write Expansion In Timing t XI t XIS RCLK 2766 drw 20 Figure 18. Read Expansion In Timing 13 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72205LB/72215LB/72225LB/72235LB/72245LB may be used when the application requirements are for 256/ 512/1,024/2,048/4,096 words or less. These FIFOs are in a single Device Configuration when the First Load (FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are grounded (Figure 19). RESET ( WRITE CLOCK (WCLK) WRITE ENABLE ( LOAD ( ) IDT 72205LB 72215LB 72225LB 72235LB 72245LB ) ) ) ) READ CLOCK (RCLK) READ ENABLE ( OUTPUT ENABLE ( DATA OUT (Q0 - Q17) EMPTY FLAG ( ) ) ) ) DATA IN (D0 - D17) FULL FLAG ( ) PROGRAMMABLE ( HALF-FULL FLAG ( PROGRAMMABLE ( FIRST LOAD ( ) ) READ EXPANSION IN ( WRITE EXPANSION IN ( ) 2766 drw 21 Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the Empty Flag and Full Flag. Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary by one cycle between FIFOs. To avoid problems the RESET ( ) user must create composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 20 demonstrates a 36-word width by using two IDT72205B/72215B/ 72225B/72235B/72245Bs. Any word width can be attained by adding additional IDT72205B/72215B/72225B/72235B/ 72245Bs. Please see the Application Note AN-83. RESET ( ) DATA IN (D) 36 18 18 READ CLOCK (RCLK) READ ENABLE ( OUTPUT ENABLE ( ) 72205LB 72215LB 72225LB 72235LB 72245LB 72205LB 72215LB 72225LB 72235LB 72245LB PROGRAMMABLE ( ) ) ) WRITE CLOCK (WCLK) WRITE ENABLE ( LOAD ( ) ) PROGRAMMABLE ( HALF FULL FLAG ( ) EMPTY FLAG ( ) FULL FLAG ( ) 18 FIRST LOAD ( ) WRITE EXPANSION IN ( READ EXPANSION IN ( 18 DATA OUT (Q) 36 ) ) 2766 drw 22 NOTE: 1. Do not connect any output control signals directly together. Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36 Synchronous FIFO Memory Used in a Width Expansion Configuration 14 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges DEPTH EXPANSION CONFIGURATION (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requiring more than 256/512/1,024/2,048/4,096 words of buffering. Figure 21 shows Depth Expansion using three IDT72205LB/ 72215LB/72225LB/72235LB/72245LBs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. See Figure 21. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. See Figure 21. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in this Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flags for monitoring. The composite PAE and PAF flags are not precise. WCLK RCLK Dn Vcc IDT 72205LB 72215LB 72225LB 72235LB 72245LB Qn WCLK RCLK DATA IN Vcc Dn IDT 72205LB 72215LB 72225LB 72235LB 72245LB Qn DATA OUT WRITE CLOCK WRITE ENABLE RESET WCLK RCLK READ CLOCK READ ENABLE OUTPUT ENABLE Dn LOAD IDT 72205LB 72215LB 72225LB 72235LB 72245LB Qn FIRST LOAD ( ) 2766 drw 23 Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration 15 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Commercial And Industrial Temperature Ranges ORDERING INFORMATION IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK I (1) J PF TF 10 15 25 Commercial (0°C to +70°C) Industrial (–40°C to +85°C) Plastic Leaded Chip Carrier (PLCC, J68-1) Thin Plastic Quad Flatpack (TQFP, PN64-1) Slim Thin Plastic Quad Flatpack (STQFP, PP64-1) Commercial Only Commercial & Industrial Commercial & Industrial Clock Cycle Time (tCLK) Speed in Nanoseconds LB 72205 72215 72225 72235 72245 Low Power 256 x 18 Synchronous FIFO 512 x 18 Synchronous FIFO 1,024 x 18 Synchronous FIFO 2,048 x 18 Synchronous FIFO 4,096 x 18 Synchronous FIFO 2766 drw 24 NOTE: 1. Industrial temperature range is available as standard product for the 15ns and the 25 ns speed grade. 16