NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL9238
ISL9237
DATASHEET
FN8723
Rev.5.00
Nov 29, 2017
Buck-Boost Narrow VDC Battery Charger with SMBus Interface and USB OTG
The ISL9237 is a buck-boost Narrow Output Voltage DC (NVDC)
charger utilizing Intersil’s advanced R3™ Technology to provide
high light-load efficiency, fast transient response and
seamless DCM/CCM transitions for a variety of mobile and
industrial applications.
Features
In Charge mode, the ISL9237 takes input power from a wide
range of DC power sources (conventional AC/DC charger
adapters, USB PD ports, travel adapters, etc.) and safely
charges battery packs with up to 3 cells in a series
configuration.
• System power monitor PSYS output, IMVP-8 compliant
ISL9237 supports On-the-Go (OTG) function for 2- and 3-cell
battery applications. When OTG function is enabled, the
ISL9237 operates in the reverse Buck mode to provide 5V at
the USB port.
• Battery discharging current monitor (BMON)
As a NVDC topology charger, it also regulates the system
output to a narrow DC range for stable system bus voltage. The
system power can be provided from the adapter, battery or a
combination of both. The ISL9237 can operate with only a
battery, only an adapter or both connected. For Intel IMVP8
compliant systems, the ISL9237 includes PSYS functionality,
which provides an analog signal representing total platform
power. The PSYS output will connect to a wide range of Intersil
IMVP8 core regulators to provide an IMVP8 compliant power
domain function.
• Optional ASGATE FET control
• Buck-boost NVDC charger for 1-, 2- or 3-cell Li-ion batteries
• Input voltage range 3.2V to 23.4V (no dead zone)
• System output voltage 2.4V to 13.824V
• Up to 1MHz switching frequency
• LDO output for charger VDD
• Adapter current monitor (AMON)
• PROCHOT# open-drain output, IMVP-8 compliant
• Allows trickle charging of depleted battery
• Ideal diode control in Turbo mode
• Supports OTG function for 2- and 3-cell batteries
• SMBus and auto-increment I2C compatible
• Two-level adapter current limit available
• Pb-free (RoHS compliant)
• Package 4x4 32 Ld QFN
Applications
The ISL9237 has serial communication via SMBus/I2C that
allows programming of many critical parameters to deliver a
customized solution. These programming parameters include,
but are not limited to: Adapter current limit, charger current
limit, system voltage setting and trickle charging current limit.
• Mobile devices with rechargeable batteries
• Industrial devices with rechargeable batteries
Related Literature
• For a full list of related documents please visit our web page
- ISL9237 product page
VADP
OPTIONAL
Rs1
VSYS
Q1
Q4
L1
LGATE2
PHASE2
BOOT2
PHASE1
BOOT1
LGATE1
UGATE1
UGATE2
Q3
Q2
VSYS
CSIN
CSOP
CSIP
Rs2
ASGATE
CSON
ADP
ACIN
ISL9237
ACOK
GND
PROCHOT#
BGATE
AMON/BMON
VBAT
BATGONE
VBAT
OTGPG/CMOUT
VDDP
VDD
DCIN
PSYS
PROG
COMP
SCL
SDA
OTGEN/CMIN
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FN8723 Rev.5.00
Nov 29, 2017
Page 1 of 40
ISL9237
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SMBUS Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus and I2C Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISL9237 SMBus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
16
16
16
16
16
17
17
Setting Charging Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Setting Adapter Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Two-Level Adapter Current Limit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Maximum Charging Voltage or System Regulating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Minimum System Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting PROCHOT# Threshold for Adapter Overcurrent Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting PROCHOT# Threshold for Battery Over Discharging Current Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting PROCHOT# Debounce Time and Duration Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTGVoltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTGCurrent Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISL9237 Buck-Boost Charger with USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Charger Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Learn Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turbo Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-Level Adapter Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSYS Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trickle Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charger Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB OTG (On-the-Go) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand-Alone Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Way Overcurrent Protection (WOCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Power MOSFET Gate Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adapter Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
20
20
20
21
21
21
24
25
25
26
26
27
28
28
29
29
29
30
30
30
30
31
31
31
31
31
33
33
33
33
33
34
34
37
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FN8723 Rev.5.00
Nov 29, 2017
Page 2 of 40
ISL9237
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP. RANGE
(°C)
PART MARKING
ISL9237HRZ
923 7HRZ
ISL9237EVAL2Z
Evaluation Board
PACKAGE
(RoHS Compliant)
-10 to +100
32 Ld 4x4 QFN
PKG.
DWG. #
L32.4x4A
NOTES:
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit, or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL9237. For more information on MSL, please see tech brief TB363.
Pin Configuration
BGATE
VBAT
PSYS
AMON/BMON
COMP
PROG
OTGPG/CMOUT
BATGONE
ISL9237
(32 LD 4x4 QFN)
TOP VIEW
32
31
30
29
28
27
26
25
CSON
1
24
ACOK
CSOP
2
23
PROCHOT#
VSYS
3
22
SCL
BOOT2
4
21
SDA
20
OTGEN/CMIN
GND
(BOTTOM PAD)
18
VDD
VDDP
8
17
DCIN
9
10
11
12
13
14
15
16
ADP
7
CSIP
LGATE2
CSIN
ACIN
ASGATE
19
BOOT1
6
UGATE1
PHASE2
PHASE1
5
LGATE1
UGATE2
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
BOTTOM PAD
GND
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. It should also be used as the
thermal pad for heat dissipation.
1
CSON
Battery current sense “–” input. Connect to battery current resistor negative input. Place a 0.1µF ceramic capacitor
between CSOP to CSON to provide differential mode filtering.
2
CSOP
Battery current sense “+” input. Connect to battery current resistor positive input. Place a 0.1µF ceramic capacitor
between CSOP to CSON to provide differential mode filtering.
3
VSYS
Provides feedback voltage for MaxSystemVoltage regulation.
FN8723 Rev.5.00
Nov 29, 2017
Page 3 of 40
ISL9237
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
4
BOOT2
High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 pin and the PHASE2 pin. The
boot capacitor is charged through an internal boot diode connected from the VDDP pin to the BOOT2 pin when the
PHASE2 pin drops below VDDP minus the voltage drop across the internal boot diode.
5
UGATE2
High-side MOSFET Q4 gate drive.
6
PHASE2
Current return path for the high-side MOSFET Q4 gate drive. Connect this pin to the node consisting of the high-side
MOSFET Q4 source, the low-side MOSFET Q3 drain and the one terminal of the inductor.
7
LGATE2
Low-side MOSFET Q3 gate drive.
8
VDDP
9
LGATE1
Low-side MOSFET Q2 gate drive.
10
PHASE1
Current return path for the high side MOSFET Q1 gate drive. Connect this pin to the node consisting of the high-side
MOSFET Q1 source, the low-side MOSFET Q2 drain and the input terminal of the inductor.
11
UGATE1
High-side MOSFET Q1 gate drive.
12
BOOT1
High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 pin and the PHASE1 pin. The
boot capacitor is charged through an internal boot diode connected from the VDDP pin to the BOOT1 pin when the
PHASE1 pin drops below VDDP minus the voltage drop across the internal boot diode.
13
ASGATE
Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional, if not used, leave ASGATE pin
floating.
When ASGATE turns on, it is clamped 10V below ADP pin voltage.
14
CSIN
Adapter current sense “-” input.
15
CSIP
Adapter current sense “+” input. The modulator also uses this for sensing input voltage in forward mode and output
voltage in reverse mode.
16
ADP
Adapter input. Used to sense adapter voltage. When adapter voltage is higher than 3.2V, AGATE is turned on.
ADP pin is also one of the two internal low power LDO inputs.
17
DCIN
Input of an internal LDO; provides power to the IC. Connect a diode OR from adapter and system outputs. Bypass this
pin with an MLCC capacitor.
18
VDD
Output of the internal LDO; provides the bias power for the internal analog and digital circuit. Connect a 1µF ceramic
capacitor to GND.
If VDD is pulled below 2V for more than 1ms, ISL9237 will reset all the SMBus register values to the default.
19
ACIN
Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN
pin voltage is greater than 0.8V.
20
OTGEN/
CMIN
OTG function enable pin or stand-alone comparator input pin.
Pull high to enable OTG function. The OTG function is enabled when the control register is written to select OTG mode
and when the battery voltage is above 5.8V.
When OTG function is not selected, this pin is the general purpose stand-alone comparator input.
21
SDA
SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor
according to SMBus specification.
22
SCL
SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor
according to SMBus specification.
23
PROCHOT#
24
ACOK
25
BATGONE
26
OTGPG/
CMOUT
FN8723 Rev.5.00
Nov 29, 2017
Power supply for the gate drivers. Connect to VDD pin through a 4.7Ω resistor and connect a 1µF ceramic capacitor to
GND.
Open-drain output. Pulled low when ACProchot#, DCProchot# or Low_VSYS event is detected. IMVP-8 compliant.
Adapter presence indicator output to indicate the adapter is ready.
Input pin to the IC. Logic high on this pin indicates the battery has been removed. Logic low on this pin indicates the
battery is present.
BATGONE pin logic high will force BGATE FET to turn off in any circumstance.
Open-drain output. OTG function output power-good indicator or the stand-alone comparator output.
When OTG function is enabled, low if OTG output voltage is not within regulation window.
When OTG function is not used, it is the general purpose comparator output.
Page 4 of 40
ISL9237
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
27
PROG
A resistor from PROG pin to GND sets the following configurations:
1. Default number of the battery cells in series, 1-, 2- or 3-cell.
2. Default switching frequency 733kHz or 1MHz.
3. Default adapter current limit value 0.476A or 1.5A.
Refer to Table 18 for programming options.
28
COMP
Error amplifier output. Connect a compensation network externally from COMP to GND.
29
AMON/
BMON
Adapter current monitor output or battery discharging current monitor output.
VAMON = 18 x (VCSIP - VCSIN); VBMON = 18 x (VCSON - VCSOP)
30
PSYS
Current source output that indicates the whole platform power consumption.
31
VBAT
Battery voltage sensing. Used for trickle charging detection and ideal diode mode control. The VBAT pin is also one of
the two internal low power LDO inputs.
32
BGATE
Gate drive output to the P-channel FET connecting the system and the battery. This pin can go high to disconnect the
battery, low to connect the battery or operate in a linear mode to regulate trickle charge current during trickle charge.
ISL9237 pulls down BGATE to GND to turn on BGATE PFET. Therefore, BGATE PFET gate-to-source voltage rating should
be higher than the battery voltage.
Simplified Application Circuit
VADP
OPTIONAL
Rs1
VSYS
20m
Q1
Q4
L1
UGATE2
BOOT2
PHASE2
PHASE1
BOOT1
LGATE1
UGATE1
LGATE2
Q3
Q2
VSYS
CSIN
CSOP
CSIP
Rs2
ASGATE
CSON
ADP
10m
ACIN
ISL9237
ACOK
PROCHOT#
BGATE
GND
AMON/BMON
VBAT
BATGONE
VBAT
OTGPG/CMOUT
OTGEN/CMIN
VADP
VDDP
VDD
DCIN
PROG
COMP
SDA
SCL
PSYS
VSYS
FIGURE 2. SIMPLIFIED APPLICATION DIAGRAM
FN8723 Rev.5.00
Nov 29, 2017
Page 5 of 40
ISL9237
Absolute Maximum Ratings
Thermal Information
CSIP, CSIN, DCIN, ADP, ASGATE . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +28V
PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-2V(
BUCK-BOOST -> BOOST OPERATION MODE TRANSITION
Page 12 of 40
ISL9237
Typical Performance (Continued)
FIGURE 10. BOOST MODE, OUTPUT VOLTAGE LOOP TO ADAPTER
CURRENT LOOP TRANSITION. VADP = 5V,
MAXSYSTEMVOLTAGE = 8.496V, VBAT = 7V, SYSTEM
LOAD 0.5A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A
FIGURE 11. BOOST MODE, CHARGING CURRENT LOOP TO ADAPTER
CURRENT LOOP TRANSITION. VADP = 5V,
MAXSYSTEMVOLTAGE = 8.496V, VBAT = 7V, SYSTEM
LOAD 0.5A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 1A
FIGURE 12. BUCK-BOOST MODE, OUTPUT VOLTAGE LOOP TO
ADAPTER CURRENT LOOP TRANSITION. VADP = 12V,
MAXSYSTEMVOLTAGE = 12.6V, VBAT = 11V, SYSTEM
LOAD 1A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A
FIGURE 13. BUCK-BOOST MODE, CHARGING CURRENT LOOP TO
ADAPTER CURRENT LOOP TRANSITION. VADP = 12V,
MAXSYSTEMVOLTAGE = 12.6V, VBAT = 11V, SYSTEM
LOAD 1A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 1A
FN8723 Rev.5.00
Nov 29, 2017
Page 13 of 40
ISL9237
Typical Performance (Continued)
FIGURE 14. BUCK MODE, OUTPUT VOLTAGE LOOP TO ADAPTER
CURRENT LOOP TRANSITION. VADP = 20V,
MAXSYSTEMVOLTAGE = 8.496V, VBAT = 7V, SYSTEM
LOAD 2A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A
FIGURE 15. BUCK MODE, CHARGING CURRENT LOOP TO ADAPTER
CURRENT LOOP TRANSITION. VADP = 20V,
MAXSYSTEMVOLTAGE = 8.496V, VBAT = 7V, SYSTEM
LOAD 2A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 2A
FIGURE 16. BOOST MODE, OUTPUT VOLTAGE LOOP TO INPUT
VOLTAGE LOOP TRANSITION. VADP = 5V,
MAXSYSTEMVOLTAGE = 8.496V, VBAT = 7V,
VINDAC = 4.5V, SYSTEM LOAD 0.5A TO 10A STEP,
CHARGECURRENT = 0A
FIGURE 17. BOOST MODE, CHARGING CURRENT LOOP TO INPUT
VOLTAGE LOOP TRANSITION. VADP = 5V,
MAXSYSTEMVOLTAGE = 8.496V, VBAT = 7V,
VINDAC = 4.5V, SYSTEM LOAD 0.5A TO 10A STEP,
CHARGECURRENT = 1A
FN8723 Rev.5.00
Nov 29, 2017
Page 14 of 40
ISL9237
Typical Performance (Continued)
FIGURE 18. OTG MODE ENABLE, OTG ENABLE 150ms DEBOUNCE TIME
FN8723 Rev.5.00
Nov 29, 2017
FIGURE 19. OTG MODE 0.5A TO 2A TRANSIENT LOAD,
OTG VOLTAGE = 5.12V
Page 15 of 40
ISL9237
General SMBus Architecture
Acknowledge
VDD SMB
INPUT
SMBUS SLAVE
SCL
OUTPUT CONTROL
SMBUS MASTER
INPUT
INPUT
SCL
CONTROL OUTPUT
SDA
OUTPUT CONTROL
STATE
MACHINE
REGISTERS
MEMORY
etc...
INPUT
CPU
SDA
CONTROL OUTPUT
INPUT
SMBUS SLAVE
SCL
OUTPUT CONTROL
INPUT
SCL SDA
Each address and data transmission uses 9 clock pulses. The
ninth pulse is the acknowledge bit (ACK). After the start
condition, the master sends 7 slave address bits and a R/W bit
during the next 8 clock pulses. During the 9 clock pulse, the
device that recognizes its own address holds the data line low to
acknowledge (Refer to Figure 23). The acknowledge bit is also
used by both the master and the slave to acknowledge receipt of
register addresses and data.
SDA
OUTPUT CONTROL
STATE
MACHINE
REGISTERS
MEMORY
etc...
MSB
SDA
SCL
TO OTHER
SLAVE DEVICES
1
8
START
FIGURE 20. GENERAL SMBus ARCHITECTURE
9
ACKNOWLEDGE
FROM SLAVE
Data Validity
FIGURE 23. ACKNOWLEDGE ON THE SMBus
The data on the SDA line must be stable during the HIGH period
of the SCL, unless generating a START or STOP condition. The
HIGH or LOW state of the data line can only change when the
clock signal on the SCL line is LOW. Refer to Figure 21.
SDA
SCL
DATA LINE
STABLE
DATA VALID
2
CHANGE
OF DATA
ALLOWED
FIGURE 21. DATA VALIDITY
START and STOP Conditions
Figure 22 START condition is a HIGH to LOW transition of the SDA
line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA line
while SCL is HIGH. A STOP condition must be sent before each
START condition.
SDA
SMBus Transactions
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7 bits of slave address (0001001 for the ISL9237)
and the R/W bit. The R/W bit is 0 for a WRITE or 1 for a READ. If
any slave device on the SMBus bus recognizes its address, it will
acknowledge by pulling the serial data (SDA) line low for the last
clock cycle in the control byte. If no slave exists at that address or
it is not ready to communicate, the data line will be one,
indicating a Not Acknowledge condition.
Once the control byte is sent and the ISL9237 acknowledges it,
the second byte sent by the master must be a register address
byte such as 0x14 for the ChargeCurrent register. The register
address byte tells the ISL9237 which register the master will
write or read. See Table 1 on page 17 for details of the registers.
Once the ISL9237 receives a register address byte, it will respond
with an acknowledge.
Byte Format
Every byte put on the SDA line must be 8 bits long and must be
followed by an acknowledge bit. Data is transferred with the
Most Significant Bit first (MSB) and the Least Significant Bit (LSB)
last. The LO BYTE data is transferred before the HI BYTE data. For
example, when writing 0x41A0, 0xA0 is written first and 0x41 is
written second.
WRITE TO A REGISTER
SLAVE
ADDR + W
S
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 22. START AND STOP WAVEFORMS
REGISTER
ADDR
A
A
LO BYTE
DATA
A
HI BYTE
DATA
A P
READ FROM A REGISTER
SLAVE
ADDR + W
S
REGISTER
ADDR
A
A P S
S
START
A
ACKNOWLEDGE
P
STOP
N
NO
ACKNOWLEDGE
SLAVE
ADDR + R
A
LO BYTE
DATA
A
HI BYTE
DATA
N P
DRIVEN BY THE
MASTER
P
DRIVEN BY THE IC
FIGURE 24. SMBus READ AND WRITE PROTOCOL
FN8723 Rev.5.00
Nov 29, 2017
Page 16 of 40
ISL9237
SMBus and I2C Compatibility
The ISL9237 SMBus minimum input logic high voltage is 2V, so it
is compatible with an I2C with higher than 2V pull-up power supply.
The ISL9237 SMBus registers are 16 bits, so it is compatible with
a 16-bit I2C or an 8-bit I2C with auto-increment capability.
ISL9237 SMBus Commands
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs
that can accommodate slow edges. Choose pull-up resistors for
SDA and SCL to achieve rise times according to the SMBus
specifications.
The illustration in this datasheet is based on current sensing
resistors Rs1 = 20mΩand Rs2 = 10mΩ unless otherwise
specified.
The ISL9237 receives control inputs from the SMBus interface after
Power-On Reset (POR). The serial interface complies with the
System Management Bus Specification, which can be downloaded
from www.smbus.org. The ISL9237 uses the SMBus Read-word and
Write-word protocols (see Figure 24 on page 16) to communicate
with the host system and a smart battery. The ISL9237 is an SMBus
slave device and does not initiate communication on the bus. It
responds to the 7-bit address 0b0001001_:
Read address = 0b00010011 (0x13H) and
Write address = 0b00010010 (0x12H).
TABLE 1. REGISTER SUMMARY
REGISTER
NAMES
REGISTER
ADDRESS
READ/
WRITE
NUMBER OF
BITS
ChargeCurrentLimit
0x14
R/W
11
[12:2] 11-bit, LSB size 4mA, maximum range 6080mA for 0A
10mΩ Rs2.
AdapterCurrentLimit1
0x3F
R/W
11
[12:2] 11-bit, LSB size 4mA, maximum range 6080mA for Set by PROG pin
20mΩ Rs1.
AdapterCurrentLimit2
0x3B
R/W
11
[12:2] 11-bit, LSB size 4mA, maximum range 6080mA for 1500mA
20mΩ Rs1.
MaxSystemVoltage
0x15
R/W
11
[13:3] 11-bit, LSB size 8mV, maximum range 13.824V.
DESCRIPTION
DEFAULT
4.192V for 1-cell
8.384V for 2-cell
12.576V for 3-cell
MinSystemVoltage
0x3E
R/W
11
[13:3] 11-bit, LSB size 8mV, maximum range 13.824V.
2.688V for 1-cell
5.376V for 2-cell
8.064V for 3-cell
ACProchot#
0x47
R/W
6
[12:7] adapter current Prochot# threshold.
LSB size 128mA, maximum 6.4A for 20mΩ Rs1.
3.072A
DCProchot#
0x48
R/W
6
[13:8] Battery discharging current Prochot# threshold.
LSB size 256mA, maximum 12.8A for 10mΩ Rs2.
4.096A
T1 and T2
0x38
R/W
6
Configure two-level adapter current limit duration
0x000h
Control0
0x39
R/W
8
Configure various charger options
0x0000h
Control1
0x3C
R/W
16
Configure various charger options
0x0000h
Control2
0x3D
R/W
16
Configure various charger options
0x0000h
Information
0x3A
R
16
Indicate various charger status
0x0000h
OTGVoltage
0x49
R/W
6
[12:7] 6-bit, OTG mode output voltage reference.
LSB size 128mV, maximum 5.376V and minimum
4.864V.
5.12V
OTGCurrent
0x4A
R/W
6
[12:7] 6-bit, OTG mode output current limit.
LSB size 128mA, maximum 4.096A for 20mΩ Rs1.
512mA
ManufacturerID
0xFE
R
8
Manufacturers ID register – 0x49 - Read only
0x0049h
DeviceID
0xFF
R
8
Device ID register - 0x0A- Read only
0x000Ah
FN8723 Rev.5.00
Nov 29, 2017
Page 17 of 40
ISL9237
Setting Charging Current Limit
To set the charging current limit, write a 16-bit ChargeCurrentLimit
command (0x14H or 0b00010100) using the Write-word protocol
shown in Figure 24 on page 16 and the data format shown in
Table 2 for a 10mΩ Rs2 or Table 3 for a 5mΩ Rs2.
TABLE 3. ChargeCurrentLimit REGISTER 0x14H (11-BIT, 8mA STEP,
5mΩ SENSE RESISTOR, x36)
BIT
DESCRIPTION
Not used
0 = Add 0mA of charge current limit.
1 = Add 8mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 16mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 32mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 64mA of charge current limit.
After POR, the ChargeCurrentLimit register is reset to 0x0000H. To
set the battery charging current value, write a non-zero number to
the ChargeCurrentLimit register. The ChargeCurrentLimit register
can be read back to verify its content.
0 = Add 0mA of charge current limit.
1 = Add 128mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 256mA of charge current limit.
Table 2 shows the conditions to enable fast charging according to
the ChargeCurrentLimit register setting.
0 = Add 0mA of charge current limit.
1 = Add 512mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 1024mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 2048mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 4096mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 8192mA of charge current limit.
The ISL9237 limits the charging current by limiting the
CSOP-CSON voltage. By using the recommended current sense
resistor values Rs1 = 20mΩand Rs2 = 10mΩ, the register’s LSB
always translates to 1mA of charging current. The
ChargeCurrentLimit register accepts any charging current
command but only the valid register bits will be written to the
register and the maximum value is clamped at 6080mA for
Rs2 = 10mΩ.
TABLE 2. ChargeCurrentLimit REGISTER 0x14H (11-BIT, 4mA STEP,
10mΩ SENSE RESISTOR, x36)
BIT
DESCRIPTION
Not used
0 = Add 0mA of charge current limit.
1 = Add 4mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 8mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 16mA of charge current limit.
Not used
0 = Add 0mA of charge current limit.
1 = Add 32mA of charge current limit.
Maximum
= 10111110000, 12160mA
0 = Add 0mA of charge current limit.
1 = Add 64mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 128mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 256mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 512mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 1024mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 2048mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 4096mA of charge current limit.
Not used
Maximum
= 10111110000, 6080mA
Setting Adapter Current Limit
To set the adapter current limit, write a 16-bit
AdapterCurrentLimit1 command (0x3FH or 0b00111111) and/or
AdapterCurrentLimit2 command (0x3BH or 0b00111011) using
the Write-word protocol shown in Figure 24 and the data format
shown in Table 4 for a 20mΩ Rs1 or Table 5 for a 10mΩ Rs1.
The ISL9237 limits the adapter current by limiting the CSIP-CSIN
voltage. By using the recommended current sense resistor values,
the register’s LSB always translates to 1mA of adapter current. Any
adapter current limit command will be accepted but only the valid
register bits will be written to the AdapterCurrentLimit1 and
AdapterCurrentLimit2 registers, and the maximum value is
clamped at 6080mA for Rs1 = 20mΩ.
After adapter POR, the AdapterCurrentLimit1 register is reset to
the value programmed through the PROG pin resistor. The
AdapterCurrentLimit2 register is set to its default value of 1.5A or
keep the value that is written to it previously if battery is present
first. The AdapterCurrentLimit1 and AdapterCurrentLimit2
registers can be read back to verify their content.
To set a second level adapter current limit, write a 16-bit
AdapterCurrentLimit2 (0x3BH or 0b00111011) command using
the Write-word protocol shown in Figure 24 and the data format as
shown in Table 4 for a 20mΩ Rs1 or Table 5 for a 10mΩ Rs1.
FN8723 Rev.5.00
Nov 29, 2017
Page 18 of 40
ISL9237
The AdapterCurrentLimit2 register has the same specification as
the AdapterCurrentLimit1 register. Refer to “Two-Level Adapter
Current Limit” on page 30 for detailed operation.
TABLE 4. AdapterCurrentLimit1 REGISTER 0x3FH AND
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT,
4mA STEP, 20mΩ SENSE RESISTOR, x16)
BIT
DESCRIPTION
TABLE 5. AdapterCurrentLimit1 REGISTER 0x3FH AND
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, 8mA
STEP, 10mΩ SENSE RESISTOR, x16) (Continued)
BIT
DESCRIPTION
0 = Add 0mA of adapter current limit.
1 = Add 512mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 1024mA of adapter current limit.
Not used
0 = Add 0mA of adapter current limit.
1 = Add 4mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 2048mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 8mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 4096mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 16mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 8192mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 32mA of adapter current limit.
Not used
0 = Add 0mA of adapter current limit.
1 = Add 64mA of adapter current limit.
Maximum
= 10111110000, 12160mA
0 = Add 0mA of adapter current limit.
1 = Add 128mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 256mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 512mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 1024mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 2048mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 4096mA of adapter current limit.
Not used
Maximum
= 10111110000, 6080mA
Setting Two-Level Adapter Current Limit
Duration
For a two-level adapter current limit, write a 16-bit T1 and T2
command (0x38H or 0b00111000) using the Write-word protocol
shown in Figure 24 and the data format as shown in Table 6 to set
the AdapterCurrentLimit1 duration T1. Write a 16-bit T2
command (0x38H or 0b00111000) to set AdapterCurrentLimit2
duration T2. T1 and T2 register accepts any command, however,
only the valid register bits will be written. Refer to “Two-Level
Adapter Current Limit” on page 30 for detailed operation.
TABLE 6. T1 AND T2 REGISTER 0x38H
BIT
T1
000 = 10ms
001 = 20ms
010 = 15ms
011 = 5ms
100 = 1ms
101 = 0.5ms
110 = 0.1ms
111 = 0ms
T2
000 = 10µs (default)
001 = 100µs
010 = 500µs
011 = 1ms
100 = 300µs
101 = 750µs
110 = 2ms
111 = 10ms
TABLE 5. AdapterCurrentLimit1 REGISTER 0x3FH AND
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, 8mA
STEP, 10mΩ SENSE RESISTOR, x16)
BIT
DESCRIPTION
Not used.
0 = Add 0mA of adapter current limit.
1 = Add 8mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 16mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 32mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 64mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 128mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 256mA of adapter current limit.
FN8723 Rev.5.00
Nov 29, 2017
DESCRIPTION
Page 19 of 40
ISL9237
Setting Maximum Charging Voltage or
System Regulating Voltage
To set the maximum charging voltage or the system regulating
voltage, write a 16-bit MaxSystemVoltage command (0x15H or
0b00010101) using the Write-word protocol shown in Figure 24
and the data format as shown in Table 7.
The MaxSystemVoltage register accepts any voltage command
however, only the valid register bits will be written to the register
and the maximum value is clamped at 13.824V.
The MaxSystemVoltage register sets the battery full charging
voltage limit. The MaxSystemVoltage register setting also is the
system bus voltage regulation point when battery is absent or
battery is present, however, is not in charging mode. See “System
Voltage Regulation” on page 31 for details.
The VSYS pin is used to sense the battery voltage for maximum
charging voltage regulation. VSYS pin is also the system bus
voltage regulation sense point.
TABLE 7. MaxSystemVoltage REGISTER 0x15H (8mV STEP)
BIT
DESCRIPTION
Not used
and the maximum value is clamped at 13.824V. The
MinSystemVoltage register value should be set lower than the
MaxSystemVoltage register value.
The MinSystemVoltage register sets the battery voltage threshold
for entry and exit of the trickle charging mode and for entry and
exit of the Learn mode. The VBAT pin is used to sense the battery
voltage to compare with the MinSystemVoltage register setting.
Refer to “Trickle Charging” on page 31 and “Battery Learn Mode”
on page 29 for details.
The MinSystemVoltage register setting also is the system voltage
regulation point when it is in trickle charging mode. The CSON
pin is the system voltage regulation sense point in trickle
charging mode. Refer to “System Voltage Regulation” on page 31”
for details.
TABLE 8. MinSystemVoltage REGISTER 0x3EH
BIT
DESCRIPTION
Not used
0 = Add 0mV of charge voltage.
1 = Add 8mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 16mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 8mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 32mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 16mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 64mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 32mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 128mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 64mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 256mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 128mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 512mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 256mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 1024mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 512mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 2046mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 1024mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 4096mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 2046mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 8192mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 4096mV of charge voltage.
Not used
0 = Add 0mV of charge voltage.
1 = Add 8192mV of charge voltage.
Maximum
= 11011000000, 13824mV
Not used
Maximum
= 11011000000, 13824mV
Setting Minimum System Voltage
To set the minimum system voltage, write a 16-bit
MinSystemVoltage command (0x3EH or 0b00111110) using the
Write-word protocol shown in Figure 24 and the data format as
shown in Table 8.
The MinSystemVoltage register accepts any voltage command,
however, only the valid register bits will be written to the register,
FN8723 Rev.5.00
Nov 29, 2017
Setting PROCHOT# Threshold for Adapter
Overcurrent Condition
To set the PROCHOT# assertion threshold for adapter overcurrent
condition, write a 16-bit ACProchot# command (0x47H or
0b01000111) using the Write-word protocol shown in Figure 24
and the data format shown in Table 9 on page 21. By using the
recommended current sense resistor values, the register’s LSB
always translates to 1mA of adapter current. The ACProchot#
register accepts any current command, however, only the valid
register bits will be written to the register, and the maximum value
is clamped at 6400mA for Rs1 = 20mΩ.
Page 20 of 40
ISL9237
After POR, the ACProchot# register is reset to 0x0C00H. The
ACProchot# register can be read back to verify its content.
If the adapter current exceeds the ACProchot# register setting,
PROCHOT# signal will assert after the debounce time programmed
by the Control2 register Bit and latch on for a minimum time
programmed by Control2 register Bit.
TABLE 9. ACProchot# REGISTER 0x47H (20mΩ SENSING RESISTOR,
128mA STEP, x18 GAIN)
BIT
DESCRIPTION
TABLE 10. DCPROCHOT# REGISTER 0x48H (10mΩ SENSING
RESISTOR, 256mA STEP, x18 GAIN)
BIT
DESCRIPTION
Not used
0 = Add 0mA of DCProchot# threshold.
1 = Add 256mA of DCProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 512mA of DCProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 1024mA of DCProchot# threshold.
Not used
0 = Add 0mA of ACProchot# threshold.
1 = Add 128mA of ACProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 2048mA of DCProchot# threshold.
0 = Add 0mA of ACProchot# threshold.
1 = Add 256mA of ACProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 4096mA of DCProchot# threshold.
0 = Add 0mA of ACProchot# threshold.
1 = Add 512mA of ACProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 8192mA of DCProchot# threshold.
0 = Add 0mA of ACProchot# threshold.
1 = Add 1024mA of ACProchot# threshold.
Not used
Maximum
= 110010, 12800mA
0 = Add 0mA of ACProchot# threshold.
1 = Add 2048mA of ACProchot# threshold.
0 = Add 0mA of ACProchot# threshold.
1 = Add 4096mA of ACProchot# threshold.
Not used
Maximum
= 110010, 6400mA
Setting PROCHOT# Debounce Time and
Duration Time
Control2 register Bit configures the PROCHOT# signal
debounce time before its assertion for ACProchot# and
DCProchot#. The low system voltage Prochot# has a fixed
debounce time of 10µs.
Setting PROCHOT# Threshold for Battery
Over Discharging Current Condition
Control2 register Bit configures the minimum duration of
Prochot# signal once asserted.
To set the PROCHOT# signal assertion threshold for battery over
discharging current condition, write a 16-bit DCProchot#
command (0x48H or 0b01001000) using the Write-word protocol
shown in Figure 24 and the data format shown in Table 10. By
using the recommended current sense resistor values, the
register’s LSB always translates to 1mA of adapter current. The
DCProchot# register accepts any current command, however, only
the valid register bits will be written to the register and the
maximum value is clamped at 12.8A for Rs2 = 10mΩ.
Control Registers
Control0, Control1 and Control2 registers configure the operation of
the ISL9237. To change certain functions or options after POR, write
an 8-bit control command to Control0 register (0x39H or
0b00111001) or a 16-bit control command to Control1 register
(0x3CH or 0b00111100) or Control2 register (0x3DH or
0b00111101) using the Write-word protocol shown in Figure 24
and the data format shown in Tables 11, 12 and 13, respectively.
After POR, the DCProchot# register is reset to 0x1000H. The
DCProchot# register can be read back to verify its content.
If the battery discharging current exceeds the DCProchot# register
setting, the PROCHOT# signal will assert after the debounce time
programmed by the Control2 register Bit and latch on for a
minimum time programmed by Control2 register Bit.
In battery only and Low Power mode, the DCProchot# threshold
is set by Control0 register Bit.
In battery only mode, DCProchot# function works only when
PSYS is enabled, since enabling PSYS will activate the internal
comparator reference. The Information register Bit
indicates if the internal comparator reference is active or not.
When adapter is present, the internal comparator reference is
always active.
FN8723 Rev.5.00
Nov 29, 2017
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ISL9237
TABLE 11. CONTROL0 REGISTER 0x39H
BIT
BIT NAME
DESCRIPTION
Not used
SMBus Timeout
The ISL9237 includes a timer to insure the SMBus master is active and to prevent overcharging the battery.
If the adapter is present and if the ISL9237 does not receive a write to the MaxChargeVoltage or
ChargeCurrentLimit register within 175s, ISL9237 will terminate charging. If a timeout occurs, writing the
MaxChargeVoltage or ChargeCurrentLimit register will re-enable charging.
0 = Enable the SMBus timeout function (default).
1 = Disable the SMBus timeout function.
High-Side FET Short
Detection Threshold
Bit configures the high-side FET short detection PHASE node voltage threshold during low-side FET
turning on.
00 = 400mV (default)
01 = 500mV
10 = 600mV
11 = 800mV
DCProchot# Threshold in
Battery Only Low Power
Mode
Bit only configures the battery discharging current DCProchot# threshold in battery only Low Power
mode indicated by the Information register 0x3A Bit. If PSYS is enabled, battery discharge current
DCProchot# threshold is set by the DCProchot# register 0x48 setting.
BIT
Rs2 = 10mΩ
(A)
Rs2 = 20mΩ
(A)
Rs2 = 5mΩ
(A)
00
12 (Default)
6
24
01
10
5
20
10
8
4
16
11
6
3
12
Input Voltage Regulation
Loop
Bit disables or enables the input voltage regulation loop.
0 = Enable (default)
1 = Disable
Input Voltage Regulation
Reference
Bit configures the input voltage loop regulation reference.
00 = 3.9V (default)
01 = 4.2V
10 = 4.5V
11 = 4.8V
TABLE 12. CONTROL1 REGISTER 0x3CH
BIT
BIT NAME
DESCRIPTION
General Purpose
Comparator Assertion
Debounce Time
Bit configures the general purpose comparator assertion debounce time.
00 = 2µs (default)
01 = 12µs
10 = 2ms
11 = 5s
13
Exit Learn Mode Option
Bit provides the option to exit Learn mode when battery voltage is lower than MinSystemVoltage
register setting.
0 = Stay in Learn mode even if VBAT < MinSystemVoltage register setting (default)
1 = Exit Learn mode if VBAT < MinSystemVoltage register setting
12
Learn Mode
Bit enables or disables the Battery Learn mode.
0 = Disable (default)
1 = Enable
To enter Learn mode, BATGONE pin needs to be low, i.e., battery must be present.
11
OTG Function
Bit enables or disables OTG function.
0 = Disable (default)
1 = Enable
10
Audio Filter
Bit enables or disables the audio filter function.
0 = Disable (default)
1 = Enable
FN8723 Rev.5.00
Nov 29, 2017
Page 22 of 40
ISL9237
TABLE 12. CONTROL1 REGISTER 0x3CH
BIT
BIT NAME
DESCRIPTION
Switching Frequency
Bit configures the switching frequency and overrides the switching frequency set by PROG pin.
000 = Switching frequency set by PROG pin (default)
001 = 913kHz
010 = 839kHz
011 = 777kHz
100 = 723kHz
101 = 676kHz
110 = 635kHz
111 = 599kHz
To keep the switching frequency set by PROG pin resistor, leave Bit as it is or write code 000, which
sets the same frequency as the PROG pin resistor.
6
Turbo
Bit enables or disables Turbo mode. When the turbo function is enabled, BGATE FET turns on in Turbo
mode. Refer to Table 19 on page 30 for BGATE ON/OFF truth table.
0 = Enable (default)
1 = Disable
5
AMON/BMON Function
Bit enables or disables the current monitor function AMON and BMON.
0 = Enable AMON/BMON (default)
1 = Disable AMON/BMON
Bit is only valid in battery only mode. When adapter is present, AMON/BMON is automatically enabled
and Bit becomes invalid.
4
AMON or BMON
Bit selects AMON or BMON as the output of AMON/BMON pin.
0 = AMON (default)
1 = BMON
3
PSYS
Bit enables or disable system power monitor PSYS function.
0 = Disable (default)
1 = Enable
2
VSYS
Bit enables or disables the buck-boost charger switching VSYS output. When disabled, ISL9237 stops
switching and forces BGATE FET on.
0 = Enable (default)
1 = Disable
Low_VSYS_Prochot#
Reference
Bit configures the Low_VSYS_Prochot# assertion threshold.
00 = 6.0V (default)
01 = 6.3V
10 = 6.6V
11 = 6.9V
For 1-cell configuration, the Low_VSYS_Prochot# assertion threshold is fixed 2.4V.
TABLE 13. CONTROL2 REGISTER 0x3DH
BIT
BIT NAME
Trickle Charging Current
DESCRIPTION
Bit configures the charging current in trickle charging mode.
00 = 256mA (default)
01 = 128mA
10 = 64mA
11 = 512mA
13
OTG Function Enable
Debounce Time
Bit configures the OTG function debounce time from when ISL9237 receives the OTG enable command.
0 = 1.3s (default)
1 = 150ms
12
Two-Level Adapter Current
Limit Function
Bit enables or disables the two-level adapter current limit function.
0 = Disable (default)
1 = Enable
FN8723 Rev.5.00
Nov 29, 2017
Page 23 of 40
ISL9237
TABLE 13. CONTROL2 REGISTER 0x3DH (Continued)
BIT
11
BIT NAME
Adapter Insertion to
ASGATE Turning On
Debounce
DESCRIPTION
Bit configures the debounce time from adapter insertion to ASGATE turning on.
0 = 1.3s (default)
1 = 150ms
After VDD POR, for the first time adapter is plugged in, the ASGATE turn-on delay is always 150ms, regardless
of the Bit setting. This bit only sets the ASGATE turn-on delay after ASGATE turns off at least one time
when VDD is above the POR value and Bit default is 0 for 1.3s.
Prochot# Debounce
Bit configures the Prochot# debounce time before its assertion for ACProchot# and DCProchot#.
00: 10µs (default)
01: 100µs
10: 500µs
11: 1ms
The Low_VSYS_Prochot# has fixed 10µs debounce time.
Prochot# Duration
Bit configures the minimum duration of Prochot# signal once asserted.
000 = 10ms (default)
001 = 20ms
010 = 15ms
011 = 5ms
100 = 1ms
101 = 500µs
110 = 100µs
111 = 0s
5
ASGATE in OTG Mode
Bit turns on or off the ASGATE FET in OTG mode.
0 = Turn ON ASGATE in OTG mode (default)
1 = Turn OFF ASGATE in OTG mode
4
CMIN Reference
Bit configures the general purpose comparator reference voltage.
0 = 1.2V (default)
1 = 2V
3
General Purpose
Comparator
Bit enables or disabled the general purpose comparator.
0 = Enable (default)
1 = Disable
2
CMOUT Polarity
Bit configures the general purpose comparator output polarity once asserted. The comparator reference
voltage is connected at the inverting input node.
0 = CMOUT is high when CMIN is higher than reference (default)
1 = CMOUT is low when CMIN is higher than reference
1
WOCP Function
Bit enables or disables the WOC (Way Overcurrent) fault protection function.
0 = Enable WOCP (default)
1 = Disable WOCP
0
PSYS Gain
Bit configures the system power monitor PSYS output gain.
0 = 1.44µA/W (default)
1 = 0.36µA/W
OTGVoltage Register
To set the OTG mode output regulation voltage, write a 16-bit
OTGVoltage command (0x49H or 0b01001001) using the
Write-word protocol shown in Figure 24 on page 16 and the data
format as shown in Table 14.
The OTGVoltage register accepts any voltage command, however,
only the valid register bits will be written to the register, and the
maximum value is clamped at 5.376V and the minimum value is
clamped at 4.864V.
FN8723 Rev.5.00
Nov 29, 2017
TABLE 14. OTGVOLTAGE REGISTER 0x49H
BIT
DESCRIPTION
Not used
0 = Add 0mV of OTG voltage
1 = Add 128mV of OTG voltage
0 = Add 0mV of OTG voltage
1 = Add 256mV of OTG voltage
0 = Add 0mV of OTG voltage
1 = Add 512mV of OTG voltage
0 = Add 0mV of OTG voltage
1 = Add 1024mV of OTG voltage
Page 24 of 40
ISL9237
TABLE 14. OTGVOLTAGE REGISTER 0x49H (Continued)
BIT
DESCRIPTION
0 = Add 0mV of OTG voltage
1 = Add 2048mV of OTG voltage
0 = Add 0mV of OTG voltage
1 = Add 4096mV of OTG voltage
Range
Not used
Information Register
The Information Register contains SMBus readable information
about manufacturing and operating modes. Table 16 identifies
the bit locations of the information available.
TABLE 16. INFORMATION REGISTER 0x3AH
BIT
DESCRIPTION
Bit indicates the configuration set by PROG pin
resistor.
= 101010, maximum 5.376V
= 100110, minimum 4.864V
In battery only mode, Bit shows the PROG pin
programmed configuration only after PROG pin
resistor is read by enabling PSYS.
OTGCurrent Register
To set the OTG mode output current limit threshold, write a 16-bit
OTGVoltage command (0x4AH or 0b01001010) using the
Write-word protocol shown in Figure 24 on page 16 and the data
format as shown in Table 15.
= Cell number, Default fSW, default
AdapterCurrentLimit1 register setting.
0000 = 3-cell, 1MHz, 1.5A,
0001 = 3-cell, 1MHz, 0.476A,
0010 = 3-cell, 723kHz, 1.5A
0011 = 3-cell, 723kHz, 0.476A
0100 = 3-cell, 723kHz, 0.1A
The OTGCurrent register accepts any current command, however,
only the valid register bits will be written to the register, and the
maximum value is clamped at 4096mA for Rs1 = 20mΩ.
0101 = 2-cell, 1MHz, 1.5A
0110 = 2-cell, 1MHz, 0.476A
0111 = 2-cell, 723kHz, 1.5A
1000 = 2-cell, 723kHz, 0.476A
1001 = 2-cell, 723kHz, 0.1A
TABLE 15. OTGCURRENT 0x4AH
BIT
DESCRIPTION
Not used
0 = Add 0mA of OTG current
1 = Add 128mA of OTG current
0 = Add 0mA of OTG current
1 = Add 256mA of OTG current
0 = Add 0mV of OTG current
1 = Add 512mA of OTG current
0 = Add 0mV of OTG current
1 = Add 1024mA of OTG current
0 = Add 0mV of OTG current
1 = Add 2048mA of OTG current
0 = Add 0mV of OTG current
1 = Add 4096mA of OTG current
Not used
Maximum
= 100000, 4096mA
FN8723 Rev.5.00
Nov 29, 2017
1010 = 1-cell, 1MHz, 0.1A
1011 = 1-cell, 1MHz, 1.5A
1100 = 1-cell, 1MHz, 0.476A
1101 = 1-cell, 723kHz, 1.5A
1110 = 1-cell, 723kHz, 0.476A
1111 = 1-cell, 723kHz, 0.1A
Bit indicates if the trickle charging mode is active
or not.
0 = Trickle charging mode is not active
1 = Trickle charging mode is active
Bit indicates the ISL9237 operation mode.
00 = Buck mode
01 = Boost mode
10 = Buck-boost mode
11 = OTG mode
Bit indicates the ISL9237 state machine status
000 = OFF
001 = BATTERY
010 = ADAPTER
011 = ACOK
100 = VSYS
101 = CHARGE
110 = ENOTG
111 = OTG
Bit indicates if the Low_VSYS_Prochot# is
tripped or not.
0 = Low_VSYS Prochot# is not tripped
1 = Low_VSYS Prochot# is tripped
Bit indicates if the battery discharging Prochot#
signal DCProchot# is tripped or not.
0 = DCProchot# is not tripped
1 = DCProchot# is tripped
Page 25 of 40
ISL9237
TABLE 16. INFORMATION REGISTER 0x3AH (Continued)
BIT
DESCRIPTION
PWM
Bit indicates if the adapter current Prochot#
signal ACProchot# is tripped or not.
0 = ACProchot# is not tripped
1 = ACProchot# is tripped
VW
Bit indicates the active control loop.
00 = MaxSystemVoltage control loop is active
01 = Charging current loop is active
10 = Adapter current limit loop is active
11 = Input voltage loop is active
COMP
VCR
Bit indicates if the internal reference circuit is
active or not. Bit = 0 indicates that ISL9237 is in
Low Power mode.
0 = Reference is not active
1 = Reference is active
Application Information
FIGURE 27. R3™ MODULATOR OPERATION PRINCIPLES IN DYNAMIC
RESPONSE
PHASE
R3™ Modulator
UGATE
COMP
+
LG ATE
S
VCR
+
VW
Q
PWM
L
R
PHASE
-
IL
VO
IL
CO
FIGURE 28. DIODE EMULATION
+
GM
-
CR
CCM/DCM BOUNDARY
VW
FIGURE 25. R3™ MODULATOR
V CR
CCM
IL
PWM
VW
VW
LIGHT DCM
V CR
HYSTERETIC
WINDOW
VCR
COMP
FIGURE 26. R3™ MODULATOR OPERATION PRINCIPLES IN STEADY
STATE
IL
VW
DEEP DCM
V CR
IL
FIGURE 29. PERIOD STRETCHING
The ISL9237 uses the Intersil patented R3™ (Robust Ripple
Regulator) modulation scheme. The R3™ modulator combines
the best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. Figure 25
FN8723 Rev.5.00
Nov 29, 2017
Page 26 of 40
ISL9237
conceptually shows the R3™ modulator circuit and Figure 26
shows the operation principles in steady state.
There is a fixed voltage window between VW and COMP. This
voltage window is called the VW window in the following
discussion. The modulator charges the ripple capacitor CR with a
current source equal to gm(VIN - VO) during PWM on-time and
discharges the ripple capacitor CR with a current source equal to
gmVO, during PWM off-time, where gm is a gain factor. The Cr
voltage VCR therefore emulates the inductor current waveform.
The modulator turns off the PWM pulse when VCR reaches VW
and turns on the PWM pulse when it reaches COMP.
Since the modulator works with Vcr, which is a large amplitude
and noise free synthesized signal, it achieves lower phase jitter
than conventional hysteretic mode modulator.
Figure 27 shows the operation principles during dynamic
response. The COMP voltage rises during dynamic response,
turning on PWM pulses earlier and more frequently temporarily,
which allows for higher control loop bandwidth than conventional
fixed frequency PWM modulator at the same steady state
switching frequency.
The R3™ modulator can operate in Diode Emulation (DE) mode
to increase light-load efficiency. In DE mode the low-side MOSFET
conducts when the current is flowing from source-to-drain and
does not allow reverse current, emulating a diode. As shown in
Figure 28, when LGATE is on, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. The IC monitors the
current by monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the
inductor current from reversing the direction and creating
unnecessary power loss.
If the load current is light enough, as Figure 28 shows, the
inductor current will reach and stay at zero before the next phase
node pulse and the regulator is in Discontinuous Conduction
Mode (DCM). If the load current is heavy enough, the inductor
current will never reach 0A and the regulator is in CCM although
the controller is in DE mode.
Figure 29 shows the operation principle in diode emulation
mode at light load. The load gets incrementally lighter in the
three cases from top to bottom. The PWM on-time is determined
by the VW window size, therefore is the same, making the
inductor current triangle the same in the three cases. The R3™
modulator clamps the ripple capacitor voltage VCR in DE mode to
make it mimic the inductor current. It takes the COMP voltage
longer to hit VCR, naturally stretching the switching period. The
inductor current triangles move further apart from each other,
such that the inductor current average value is equal to the load
current. The reduced switching frequency helps increase
light-load efficiency.
connected to the same inductor’s “output” as is the case with a
boost converter. This arrangement supports bucking from a
voltage input higher than the battery and also boosting from a
voltage input lower than the battery.
In Buck mode, Q1 and Q2 turn on and off alternatively, while Q3
remains off and Q4 remains on.
In Boost mode, Q3 and Q4 turn on and off alternatively, while Q1
remains on and Q2 remains off.
In Buck-boost mode, Q1 and Q3 is turned on and off at the same
time and alternatively with Q2 and Q4, which turned off and on at
the same time.
In OTG mode, Q3 and Q4 turn on and off alternatively as a buck
regulator with VBAT as the input, while Q1 remains on and Q2
remains off with the CSIP pin as the output sensing point.
TABLE 17. OPERATION MODE
MODE
Q1
Q2
Buck
Control FET
Sync. FET
OFF
ON
Boost
ON
OFF
Control FET
Sync. FET
Control FET
Sync. FET
Control FET
Sync. FET
ON
OFF
Sync. FET
Control FET
Buck-Boost
OTG
VADP
Q3
RS1
Q4
VSYS
CSOP
CSIP
CSIN
Q4
Q1
L1
Q2
RS2
SYSTEM
LOAD
CSON
Q3
BGATE
FET
VBAT
BATTERY
FIGURE 30. BUCK-BOOST CHARGER TOPOLOGY
The ISL9237 optimizes the operation mode transition algorithm
by considering the input and output voltage ratio and the load
condition. When adapter voltage VADP is rising and is higher than
94% of the system bus voltage VSYS, ISL9237 will transit from
Boost mode to Buck-boost mode; if VADP is higher than 120% of
VSYS, ISL9237 will forcedly transit from Buck-boost mode to
Buck mode at any circumstance. At heavier load, the mode
transition point changes accordingly to accommodate the duty
cycle change due to the power loss on the charger circuit.
When the adapter voltage VADP is falling and is lower than 106%
of the system bus voltage VSYS, ISL9237 will transit from Buck
mode to Buck-boost mode; if VADP is lower than 80% of VSYS,
ISL9237 will transit from Buck-boost mode to Boost mode.
ISL9237 Buck-Boost Charger with USB OTG
The ISL9237 buck-boost charger drives an external N-channel
MOSFET bridge comprised of two transistor pairs as shown in
Figure 30. The first pair, Q1 and Q2, is a buck arrangement with
the transistor center tap connected to an inductor “input” as is
the case with a buck converter. The second transistor pair, Q3
and Q4, is a boost arrangement with the transistor center tap
FN8723 Rev.5.00
Nov 29, 2017
Page 27 of 40
ISL9237
VADP
BUCK
120%
BUCK
B U C K -B O O S T
106%
B U C K -B O O S T
VSYS
94%
BOOST
80%
BOOST
ACOK is an open-drain output pin indicating the presence of the
adapter and readiness of the adapter to supply power to the
system bus. The ISL9237 actively pulls ACOK low in the absence of
the adapter.
Before ASGATE turns ON, the ISL9237 will source 10µA of current
out of the PROG pin and read the pin voltage to determine the
PROG resistor value. The PROG resistor programs the
configurations of the ISL9237.
In battery only mode, ISL9237 enters Low Power mode if only
battery is present. VDD is 4V from the low power LDO to minimize
the power consumption. VDD becomes 5V once it exits the Low
Power mode such as when PSYS is enabled.
Programming Charger Option
VADP
FIGURE 31. OPERATION MODE
When the OTG function is enabled with SMBus command and
OTGEN pin, and if battery voltage VBAT is higher than 5.8V,
ISL9237 operates in the reverse Buck mode, Q4, Q3 and L1
consists of the reverse buck regulator, Q1 is turned on and Q2 is
turned off. For reverse buck, there is one digital bit to control
ASGATE. OTG mode is not available for 1-cell battery systems.
The ISL9237 connects the system voltage rail to either the
output of the buck-boost switcher or the battery. In Turbo event,
the ISL9237 will turn on the BGATE FET to discharge the battery
so the battery works with the adapter together to supply the
system power.
Soft-Start
The ISL9237 includes a low power LDO with nominal 4V output,
which input is OR-ed from pins VBAT and ADP. The ISL9237 also
includes a high power LDO with nominal 5V output, which input is
from the DCIN pin connected to the adapter and the system bus
through an external OR-ing diode circuit. Both LDO outputs are tied
to the VDD pin to provide the bias power and gate drive power for
ISL9237. VDDP pin is the ISL9237 gate drive power supply input.
Use an R-C filter to generate the VDDP pin voltage from the VDD
pin voltage.
When VDD > 2.7V, the ISL9237 digital block is activated and the
SMBus register is ready to communicate with the master
controller.
When VADP > 3.2V, after 1.3s or 150ms debounce time set by
Control2 register Bit (after VDD POR, for the first time
adapter plugged in, the ASGATE turn on delay is always 150ms),
ASGATE starts turning on with 10µA sink current. During the 1.3s
or 150ms debounce time, ISL9237 uses ‘Intersil’s patent pending
technique to check if the input bus is short or not; if CSIP < 2V or
ACIN < 0.8V, ASGATE will not turn on. The soft-start scheme will
carefully bias up the input capacitors and protect the back-to-back
ASGATE FETs against potential damage caused by the inrush
current.
Use a voltage divider from the adapter voltage to set the ACIN pin
voltage. The ISL9237 monitors the ACIN pin voltage to determine
the presence of the adapter. Once VDD > 3.8V, the ACIN pin
voltage exceeds 0.8V and ASGATE is fully turned on, the ISL9237
will allow the external circuit to pull up the ACOK pin. Once ACOK is
asserted, ISL9237 will start switching.
FN8723 Rev.5.00
Nov 29, 2017
The resistor from the PROG pin to GND programs the configuration
of the ISL9237 for the default number of battery cells in series, the
default switching frequency and the default AdapterCurrentLimit1
register value. AdapterCurrentLimit2 register default value is 1.5A.
Table 18 shows the programing options.
TABLE 18. PROG PIN PROGRAMMING OPTIONS
PROG-PIN
RESISTOR (kΩ)
MIN
VALUE
1%
MAX
0
DEFAULT
DEFAULT AdapterCurrent
BATTERY
SWITCHING Limit1 Register
CELL
(A)
NUMBER FREQUENCY
1-cell
733kHz
0.1
16.6
16.9
17.2
0.476
31.1
31.6
32.1
1.5
43.5
44.2
44.9
58.1
59
59.9
1.5
72.1
73.2
74.3
0.1
85.3
86.6
87.9
101
102
103
0.476
113.9
115
116.2
1.5
128.7
130
131.3
141.6
143
144.4
156.4
158
159.6
172.3
174
175.7
0.476
185.1
187
188.9
1.5
201
203
(Note 8)
205
218.8
221
223.2
1MHz
2-cell
733kHz
1MHz
0.476
0.1
0.476
1.5
3-cell
733kHz
1MHz
0.1
0.476
1.5
NOTE:
8. 203kΩ is not standard resistor; use two resistors in series or in parallel
to get the closest value.
ISL9237 will use the default number of cells in series as Table 18
shows and sets the default MaxSystemVoltage register value and
default MinSystemVoltage register value accordingly.
Page 28 of 40
ISL9237
The switching frequency can be changed through SMBus
Control1 register Bit after POR. Refer to the SMBus
Control1 register programming table for detailed description.
Before ASGATE turns on, ISL9237 will source 10µA current out of
the PROG pin and read the PROG pin voltage to determine the
resistor value. However, application environmental noise may
pollute the PROG pin voltage and cause incorrect reading. If noise
is a concern, it is recommended to connect a capacitor from the
PROG pin to GND to provide filtering. The resistor and the capacitor
RC time constant should be less than 40µs so the PROG pin
voltage can rise to steady state before the ISL9237 reads it.
If ISL9237 is powered up from battery, it will not read the PROG
resistor unless PSYS is enabled through SMBus Control1 register
Bit. In battery only mode, whenever PSYS is enabled,
ISL9237 will read the PROG pin resistor and reset the
configuration to the default.
Whenever the adapter is plugged in, ISL9237 will reset the
AdapterCurrentLimit1 register to the default by reading PROG pin
resistor if it is not read before or by loading the previous reading
result.
If PSYS is not enabled, ISL9237 will reset MaxSystemVoltage
register and MinSystemVoltage register to their default values
according to the PROG pin cell number setting. If PSYS is
enabled, ISL9237 will keep the values in these two registers.
By default, the adapter current sensing resistor, Rs1, is 20mΩ
and the battery current sensing resistor, Rs2, is 10mΩ. Using this
Rs1 = 20mΩand Rs2 = 10mΩ option would result in 1mA/LSB
correlation in the SMBus current commands.
If Rs1 and Rs2 values are different from this Rs1 = 20mΩand
Rs2 = 10mΩ option, the SMBus command needs to be scaled
accordingly to obtain the correct current. Smaller current sense
resistor values reduce the power loss while larger current sense
resistor values give better accuracy.
If different current sensing resistors are used, the Rs1:Rs2 ratio
should be kept as 2:1, then PSYS output can be scaled
accordingly to reflect the total system power correctly.
The illustration in this datasheet is based on current sensing
resistors Rs1 = 20mΩ and Rs2 = 10mΩ unless specified
otherwise.
DE Operation
In DE mode of operation, the ISL9237 employs a phase
comparator to monitor the PHASE node voltage during the
low-side switching FET on-time in order to detect the inductor
current zero crossing. The phase comparator needs a minimum
on-time of the low-side switching FET for it to recognize inductor
current zero crossing. If the low-side switching FET on-time is too
short for the phase comparator to successfully recognize the
inductor zero crossing, the ISL9237 may lose diode emulation
ability. To prevent such a scenario, the ISL9237 employs a
minimum low-side switching FET on-time. When the intended
low-side switching FET on-time is shorter than the minimum
value, the ISL9237 stretches the switching period in order to
keep the low-side switching FET on-time at the minimum value,
which causes the CCM switching frequency to drop below the set
point.
FN8723 Rev.5.00
Nov 29, 2017
Power Source Selection
The ISL9237 automatically selects the adapter and/or the
battery as the source for system power.
The BGATE pin drives a P-channel MOSFET gate that
connects/disconnects the battery from the system and the
switcher.
The ASGATE pin drives a pair of back-to-back common source
PFETs to connect/disconnect the adapter from the system and
the battery. Use of the ASGATE pin is optional.
When battery voltage VBAT is higher than 2.4V and adapter
voltage VADP is less than 3.2V, ISL9237 operates in battery only
mode. During the battery only mode, ISL9237 turns on the
BGATE FET to connect the battery to the system. In battery only
mode, the ISL9237 consumes very low power, less than 20µA
during this mode. The battery discharging current monitor BMON
can be turned on during this mode to monitor the battery
discharging current. If the battery voltage VBAT is higher than
5.8V, the system power monitor PSYS function also can be
turned on during this mode to monitor system power.
In battery only mode, the USB OTG function can be enabled, see
“USB OTG (On-the-Go)” on page 31 for details.
When adapter voltage, VADP, is more than 3.2V, ISL9237 turns
on ASGATE. If VDD is higher than 3.8V, ISL9237 enters in the
forward buck, forward boost or forward Buck-boost mode
depending upon the adapter and system voltage, VSYS, duty
cycle ratio. The system bus voltage is regulated at the voltage set
on the MaxSystemVoltage register. If the charge current register
is programmed (non-zero), ISL9237 charges the battery either in
trickle charging mode or fast charging mode, as long as
BATGONE is low.
Battery Learn Mode
The ISL9237 supports battery Learn mode. The ISL9237 enters
Battery Learn mode when it receives SMBus Control command.
This mode of operation is used when it is desired to supply the
system power from the battery even when the adapter is plugged
in, such as calibration of the battery fuel gauge, hence the name
“Battery Learn mode”.
Upon entering Battery Learn mode the ISL9237 will turn on the
BGATE FET when the system bus voltage decays to the battery
voltage in order to avoid inrush current from the system bus to
the battery.
In Battery Learn mode, the ISL9237 turns on BGATE, keeps
ASGATE on, however, turns off the buck-boost switcher
regardless of whether the adapter is present or not.
There are three ways of exiting Battery Learn mode:
1. Receive Battery Learn mode exit command through SMBus.
2. Battery voltage is less than MinSystemVoltage register setting
(according to Control1 register Bit setting).
3. BATGONE pin voltage goes from logic LOW to HIGH.
In all these cases, the ISL9237 resumes switching immediately
to supply power to the system bus from the adapter in order to
prevent system voltage collapse.
Page 29 of 40
ISL9237
Turbo Mode Support
Turbo mode refers to the scenario when the system draws more
power than the adapter’s power rating.
If the adapter current reaches the AdapterCurrentLimit1 register
set value (or AdapterCurrentLimit2 register set value, if two-level
adapter current limit function is enabled), or the adapter input
voltage drops to the input voltage regulation reference set by
Control0 register 0x39H Bit, the ISL9237 will limit the
input power by regulating the adapter current at
AdapterCurrentLimit1/2 register set value, or by regulating the
adapter voltage at the input voltage regulation reference point.
In Turbo mode, the system bus voltage VSYS will drop
automatically or the charging current will drop automatically to
limit the adapter input power. If the VSYS pin voltage is 150mV
lower than the VBAT pin voltage, BGATE FET will turn on, such
that the battery supplies the rest of the power required by the
system.
If the ISL9237 detects 150mA charging current or if the battery
discharging current is less than 300mA for longer than 20ms, it
will turn off BGATE to exit Turbo mode. Refer to Table 19 for
BGATE control logic.
CHARGECURRENT
REGISTER
The two-level adapter current limit function can be enabled and
disabled through SMBus Control2 register Bit. When the
two-level adapter current limit function is disabled, only
AdapterCurrentLimit1 value is used as the adapter current limit
and AdapterCurrentLimit2 value is ignored.
I
t2
t1
t2
t1
AdapterCurrentLimit2
AdapterCurrentLimit1
I_Adapter
I
T
I_System
I_Battery
T
Current Monitor
BGATE ON/OFF
SYSTEM LOAD NOT
IN TURBO MODE
RANGE
AdapterCurrentLimit1 register value can be higher or lower than
AdapterCurrentLimit2 value.
FIGURE 32. TWO LEVEL ADAPTER CURRENT LIMIT
TABLE 19. BGATE ON/OFF TRUTH TABLE
TURBO
(CONTROL
BIT)
output surge current without requiring the charger to enter Turbo
mode. Such operation maximizes battery life.
SYSTEM
LOAD IN
TURBO
MODE
RANGE
The ISL9237 provides an adapter current monitor or a battery
discharging current monitor through the AMON/BMON pin. The
AMON output voltage is 18x the (CSIP-CSIN) voltage and the BMON
output voltage is 18x the (CSON-CSOP) voltage.
AMON and BMON function can be enabled or disabled through
SMBus Control1 register Bit and Bit as Table 12 on
page 22 shows.
0 = ENABLE
1 = DISABLE
0 = ZERO
1 = NONZERO
0
0
OFF
ON
0
1
ON for fast charge;
Trickle charge is
enabled
ON
PSYS Monitor
The ISL9237 PSYS pin provides a measure of the instantaneous
power consumption of the entire platform. The PSYS pin outputs a
current source described by Equation 1.
1
0
OFF
OFF
1
1
ON for fast charge;
Trickle charge is
enabled
ON
Two-Level Adapter Current Limit
In a real system, Turbo event usually does not last very long. It is
often no longer than milliseconds, a time length during which the
adapter can supply current higher than its DC rating. The
ISL9237 employs two-level adapter current limit in order to fully
take advantage of adapter’s surge capability and minimize the
power drawn from the battery.
Figure 32 shows the two SMBus programmable adapter current
limit levels, AdapterCurrentLimit1 and AdapterCurrentLimit2, as
well as the durations t1 and t2. The two-level adapter current
limit function is initiated when the adapter current is less than
100mA lower than the AdapterCurrentLimit1 register setting and
it starts at AdapterCurrentLimit2 for t2 duration and then
changes to AdapterCurrentLimit1 for t1 duration before
repeating the pattern. These parameters can set adapter current
limit with an envelope that allows the adapter to temporarily
FN8723 Rev.5.00
Nov 29, 2017
I PSYS = K PSYS V ADP I ADP + V BAT I BAT
(EQ. 1)
KPSYS is based on current sensing resistor Rs1 = 20mΩ and
Rs2 = 10mΩ. VADP is the adapter voltage in volts, IADP is the
adapter current in amperes, VBAT is the battery voltage and IBAT
is the battery discharging current. When the battery is
discharging, IBAT is a positive value; when the battery is being
charged, IBAT is a negative value. The battery voltage VBAT is
detected through the CSON pin to maximize the power monitor
accuracy in NVDC configuration trickle charge mode.
The Rs1 to Rs2 ratio must be 2:1 for a valid power calculation to
occur. If the resistance values are higher (or lower) than the
suggested values above, KPSYS will be proportionally higher (or
lower). As an example, if Rs1 = 10mΩ and Rs2 = 5mΩ, then the
output current will be half the value for the same power. If the
PSYS information is not needed then any Rs1:Rs2 ratio is
acceptable.
The PSYS information includes the power loss of the charger
circuit and the actual power delivered to the system. Resistor
Page 30 of 40
ISL9237
RPSYS connected between the PSYS pin and GND converts the
PSYS information from current to voltage.
PSYS accuracy limits and a typical accuracy scan are shown in
Figure 33 on page 31.
its value instead of resetting to zero. If a timeout occurs,
MaxSystemVoltage or ChargeCurrent register must be written to
re-enable charging.
The ISL9237 allows users to disable the charger timeout function
through SMBus Control0 register Bit as Table 11 on page 22
shows.
USB OTG (On-the-Go)
When the OTG function is enabled with SMBus command and
OTGEN pin, and if battery voltage VBAT is higher than 5.8V,
ISL9237 operates in the reverse Buck mode, Q4, Q3 and L1
consists of the reverse buck regulator and Q1 remains on and Q2
remains off.
FIGURE 33. PSYS ACCURACY AND LIMITS
The PSYS function can be enabled or disabled through SMBus
Control1 register Bit as shown in Table 12 on page 22.
In battery only mode, the PSYS function cannot work if the
battery voltage is less than 5.8V.
Trickle Charging
The ISL9237 supports trickle charging to an overly discharged
battery. It can activate the trickle charging function when the
battery voltage is lower than MinSystemVoltage setting. VBAT pin
is the battery voltage sense point for trickle charge mode.
To enable trickle charging, set ChargeCurrent register to a
non-zero value. To disable trickle charging, set ChargeCurrent
register to 0. Refer to Table 19 for trickle charging control logic.
The trickle charging current can be programmed to be 256mA,
128mA or 64mA through SMBus Control2 register Bit in
Table 13 on page 23.
In trickle charging mode, the ISL9237 regulates the trickle
charging current through the buck-boost switcher. Another
independent control loop controls the BGATE FET such that the
system voltage is maintained at the voltage set in the
MinSystemVoltage register. The VSYS pin is the system voltage
sensing point in trickle charging mode.
Once the battery voltage is charged the MinSystemVoltage register
value, the ISL9237 enters fast charging mode by limiting the
charging current at the ChargeCurrentLimit register setting.
System Voltage Regulation
If the battery is absent, or if a battery is present, however, BGATE
is turned off, the ISL9237 will regulate the system bus voltage at
the MaxSystemVoltage register setting. The VSYS pin is used to
sense the system bus voltage.
Charger Timeout
The ISL9237 includes a timer to insure the SMBus master is active
and to prevent overcharging the battery. The ISL9237 will
terminate charging by turning off BGATE FET if the charger has not
received a write command to the MaxSystemVoltage or
ChargeCurrent register within 175s. When the charging is
terminated by the timeout, the ChargeCurrent register will retain
FN8723 Rev.5.00
Nov 29, 2017
Once ISL9237 receives the command to enable the OTG
function, it will start switching after the 1.3s or 150ms debounce
time set by Control2 register Bit. Once the OTG output
voltage is between 4.2V and 6V, OTG power-good OTGPG will
assert to High. Moreover, Control2 register Bit can be used to
turn ASGATE FET off to cut off the OTG output.
Before OTG mode starts switching, the CSIP pin voltage needs to
drop below the OTG output overvoltage protection threshold of
6V first.
The default OTG output voltage is 5.12V. The OTGVoltage register
0x49H can be used to configure the OTG output voltage.
The default OTG output current is limited at 512mA through Rs1.
The OTGCurrent register 0x4AH can be used to adjust the OTG
output current limit.
ISL9237 includes the OTG output undervoltage and overvoltage
protection functions. The UVP threshold is 4.2V and the OVP
threshold is 6V.
Once UV is detected, ISL9237 will stop switching and turn off
ASGATE and deassert OTGPG. Once OTG output increases above
4.5V, after 1.3s or 150ms debounce time set by Control2 register
Bit, it will resume switching.
Once OV is detected, ISL9237 will stop switching and deassert
OTGPG. It will resume switching after 100µs once OTG voltage
drops below 5.7V.
BATGONE needs to be low to enable OTG mode. OTG mode is not
available for 1-cell battery systems.
Stand-Alone Comparator
The ISL9237 includes a general purpose stand-alone
comparator. OTGEN/CMIN pin is the comparator input. The
internal comparator reference is connected to the inverting input
of the comparator and can be configured as 1.2V or 2V through
SMBus Control2 register Bit. The comparator output is the
OTGPG/CMOUT pin and the output polarity when the comparator
is tripped can be configured through SMBus register bit.
When Control2 register Bit = 0 for normal comparator output
polarity, if CMIN > Reference then CMOUT = High; if
CMIN < Reference then CMOUT = Low.
When Control2 register Bit = 1 for inversed comparator
output polarity, if CMIN > Reference then CMOUT = Low; if
CMIN < Reference then CMOUT = High.
Page 31 of 40
ISL9237
In battery only mode, the stand-alone comparator is disabled
unless PSYS is enabled through SMBus Control1 register Bit
to enable the internal reference, which is indicated through
Information register Bit.
Table 20 shows the OTG mode and the stand-alone comparator
truth table.
TABLE 20. OTG AND COMPARATOR TRUTH TABLE
CONTROL1
REGISTER 0x3C
CONTROL2
REGISTER 0x3D
BIT
BIT
COMPARATOR
OTG FUNCTION
ENABLE/DISABLE ENABLE/DISABLE
PIN-2O
PIN-26
OTGEN/CMIN
OTGPG/CMOUT
DESCRIPTION
0
0
Comparator
input pin CMIN
Comparator output
pin CMOUT
OTG function is disabled.
Comparator is enabled.
0
1
X
X
Both OTG function and comparator are disabled.
1
0
Comparator
input pin CMIN
Comparator output
pin CMOUT
Both OTG function and comparator are enabled.
OTG function is enabled when VBAT > 5.8V and Control1 register
Bit = 1 without OTG power-good pin indication. While the
Information register 0x3A Bit = 11 indicates it is in OTG mode.
1
1
OTG enable
OTG power-good
input pin OTGEN indication pin
OTGPG
FN8723 Rev.5.00
Nov 29, 2017
Comparator is disabled.
OTG function is enabled when VBAT > 5.8V and ENOTG pin = High and
Control1 register Bit = 1
Page 32 of 40
ISL9237
Adapter Overvoltage Protection
Switching Power MOSFET Gate Capacitance
If the ADP pin voltage exceeds 23.4V for more than 10µs, the
ISL9237 will consider an adapter overvoltage condition has
occurred. It will turn off the ASGATE MOSFETs to isolate the
adapter from the system, deassert the ACOK signal by pulling it
low and stop switching. BGATE will turn on for the battery to
support the system load. Once ADP voltage drops below 23.04V
from more than 100µs, it will start to turn on ASGATE and start
switching.
The ISL9237 includes an internal 5V LDO output at VDD pin,
which can be used to provide the switching MOSFET gate driver
power through VDDP pin with an R-C filter. The 5V LDO output
overcurrent protection threshold is 70mA nominal. When
selecting the switching power MOSFET, the MOSFET gate
capacitance should be considered carefully to avoid overloading
the 5V LDO, specially in Buck-boost mode when four MOSFETs
switching at the same time. For one MOSFET, the gate drive
current can be estimated by Equation 2:
System Overvoltage Protection
The ISL9237 provides system rail overvoltage protection. If the
system voltage VSYS is 600mV higher than MaxSystemVoltage
register set value, it will declare the system overvoltage and stop
switching. It will resume switching without the 1.3s or 150ms
debounce once VSYS drops 300mV below the system
overvoltage threshold.
Way Overcurrent Protection (WOCP)
In the case that the system bus is shorted, either a MOSFET short
or an inductor short, the input current could be high. ISL9237
includes input overcurrent protection to turn off the ASGATE and
stop switching.
The ISL9237 provides adapter current and battery discharging
current WOCP (Way Overcurrent Protection) function against the
MOSFET short, system bus short and inductor short scenarios.
ISL9237 monitors the CSIP-CSIN voltage and CSON-CSOP
voltage, compares them with the WOCP threshold 12A for
adapter current and 16A for battery discharge current.
When the WOC comparator is tripped, ISL9237 counts one time
within each 20µs. Whenever ISL9237 counts WOC to 7 times in
656ms, it turns off ASGATE, deasserts ACOK and stops switching
immediately. After the 1.3s or 150ms debounce time set by
Control2 register Bit, it goes through the start-up sequence
to retry.
The WOCP function can be disabled through Control2 register
Bit.
Over-Temperature Protection
The ISL9237 turns off the internal LDO for self protection when
the junction temperature exceeds +140°C. The internal LDO
stays off until the junction temperature falls below +120°C.
I driver = Q g f
SW
(EQ. 2)
Where:
• Qg is the total gate charge, which can be found in the MOSFET
datasheet
• fSW is switching frequency
Adapter Input Filter
The adapter cable parasitic inductance and capacitance could
cause some voltage ringing or an overshoot spike at the adapter
connector node when the adapter is hot plugged in. This voltage
spike could damage the ASGATE MOSFET or the ISL9237 pins
connecting to the adapter connector node. One low cost solution
is to add an RC snubber circuit at the adapter connector node to
clamp the voltage spike as shown in Figure 34. A practical value
of the RC snubber is 2.2Ω to 2.2µF while the appropriate values
and power rating should be carefully characterized based on the
actual design. Meanwhile, it is not recommended to add a pure
capacitor at the adapter connector node, which can cause an
even bigger voltage spike due to the adapter cable or the adapter
current path parasitic inductance.
ADAPTER
CONNECTOR
Ri
2 .2
ASG ATE
Ci
2 .2 µ F
RC SNUBBER
A C IN
IS L 9 2 3 7
The ISL9237 stops switching after declaring over-temperature
protection.
Once the temperature falls below +120°C, and after a 100µs
delay, the ISL9237 will enable the internal LDO and the ISL9237
will resume operation.
FN8723 Rev.5.00
Nov 29, 2017
FIGURE 34. ADAPTER INPUT RC SNUBBER CIRCUIT
Page 33 of 40
ISL9237
General Application Information
This design guide is intended to provide a high-level explanation of
the steps necessary to design a single-phase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following section. In addition to
this guide, Intersil provides complete reference designs that
include schematics, bill of materials and example board layouts.
Select the LC Output Filter
The duty cycle of an ideal buck converter in CCM is a function of
the input and the output voltage. This relationship is written by
Equation 3:
V OUT
D = --------------V IN
(EQ. 3)
capacitor can fade as much as 50% as the DC voltage across it
increases.
Select the Input Capacitor
The important parameters for the input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 35 is a graph of the input capacitor RMS ripple current,
normalized relative to output load current, as a function of duty
cycle and is adjusted for converter efficiency. The normalized RMS
ripple current calculation is written as Equation 8:
2
V OUT 1 – D
I P-P = -------------------------------------f SW L
(EQ. 4)
A typical step-down DC/DC converter will have an IP-P of 20% to
40% of the maximum DC output load current for a practical
design. The value of IP-P is selected based upon several criteria
such as MOSFET switching loss, inductor core loss and the
resistive loss of the inductor winding.
The DC copper loss of the inductor can be estimated by
Equation 5:
P COPPER = I LOAD
2
DCR
(EQ. 5)
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given to the
DCR selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated temperatures. A
saturated inductor could cause destruction of circuit components.
A DC/DC buck regulator must have output capacitance CO into
which ripple current IP-P can flow. Current IP-P develops a
corresponding ripple voltage VP-P across CO, which is the sum of
the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are written by Equations 6 and 7:
V ESR = I P-P E SR
(EQ. 6)
I P-P
V C = ----------------------------8 CO f
(EQ. 7)
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered in this scenario. A capacitor
dissipates heat as a function of RMS current and frequency. Be
sure that IP-P is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated RMS
current at fSW. Take into account that the rated value of a
FN8723 Rev.5.00
Nov 29, 2017
Dk
I MAX D 1 – D + -------------12
---------------------------------------------------------------------I C RMS ,NORMALIZED =
I MAX
IN
(EQ. 8)
Where:
• IMAX is the maximum continuous ILOAD of the converter
• k is a multiplier (0 to 1) corresponding to the inductor
peak-to peak ripple amplitude expressed as a ratio of IMAX
(0 to 1)
• D is the duty cycle that is adjusted to take into account the
efficiency of the converter, which is written as Equation 9:
V OUT
D = -------------------------V IN EFF
(EQ. 9)
In addition to the capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
NORMALIZED INPUT RMS RIPPLE CURRENT
The output inductor peak-to-peak ripple current is written by
Equation 4:
0.60
0.48
k = 0.25
k = 0.5
k=0
0.36
k=1
k = 0.75
0.24
VS = ±2.5V
0.12
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
DUTY CYCLE
FIGURE 35. NORMALIZED RMS INPUT CURRENT AT EFF = 1
Page 34 of 40
1.0
ISL9237
Select the Switching Power MOSFET
Select the Bootstrap Capacitor
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain-to-source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum VDS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFET switches off.
The selection of the bootstrap capacitor is written by
Equation 13:
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear
region. Unlike the low-side MOSFET which has the drain-to-source
voltage clamped by its body diode during turn off, the high-side
MOSFET turns off with a VDS of approximately VIN - VOUT , plus
the spike across it. The preferred low-side MOSFET emphasizes
low rDS(ON) when fully saturated to minimize conduction loss. It
should be noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For higher
output, low input voltage solutions, a more balanced MOSFET
selection for high- and low-side devices may be warranted.
Qg
C BOOT = -----------------------V BOOT
(EQ. 13)
Where:
• Qg is the total gate charge required to turn on the high-side
MOSFET.
• VBOOT, is the maximum allowed voltage decay across the
boot capacitor each time the high-side MOSFET is switched on.
As an example, suppose the high-side MOSFET has a total gate
charge Qg, of 25nC at VGS = 5V and a VBOOT of 200mV. The
calculated bootstrap capacitance is 0.125µF; for a comfortable
margin, select a capacitor that is double the calculated
capacitance. In this example, 0.22µF will suffice. Use an X7R or
X5R ceramic capacitor.
For the low-side (LS) MOSFET, the power loss can be assumed to
be conductive only and is written as Equation 10:
2
P CON_LS I LOAD r DS ON _LS 1 – D
(EQ. 10)
For the high-side (HS) MOSFET, or conduction loss is written by
Equation 11:
P CON_HS = I LOAD
2
r DS ON _HS D
(EQ. 11)
For the high-side MOSFET, the switching loss is written as
Equation 12:
V IN I PEAK t SWOFF f
V IN I VALLEY t SWON f
SW
SW
P SW_HS = -------------------------------------------------------------------------- + ----------------------------------------------------------------------2
2
(EQ. 12)
Where:
• IVALLEY is the difference of the DC component of the inductor
current minus 1/2 of the inductor ripple current.
• IPEAK is the sum of the DC component of the inductor current
plus 1/2 of the inductor ripple current.
• tSW(ON) is the time required to drive the device into saturation.
• tSW(OFF) is the time required to drive the device into cut-off.
FN8723 Rev.5.00
Nov 29, 2017
Page 35 of 40
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