ISL98002CRZ-EVALZ

DATASHEET ISL98002 FN6535 Rev. 1.0 Jul 6, 2021 Triple Video Digitizer with Digital PLL Triple Video Digitizer with Digital PLL Features The ISL98002 3-Channel, 8-bit Analog Front End (AFE) contains all the functions necessary to digitize analog YPbPr video signals and RGB graphics signals from DVD players, digital VCRs, video set-top boxes, and personal computers. This product family’s conversion rates support HDTV resolutions up to 1080p and PC monitor resolutions up to UXGA, while the front end's programmable input bandwidth ensures sharp, clear images at all resolutions. • 170MSPS maximum conversion rates To maximize performance with the widest variety of video sources, the ISL98002 features a fast-responding digital PLL (DPLL), providing extremely low jitter with PC graphics signals and quick recovery from VCR head switching with video signals. Integrated HSYNC and SOG processing eliminate the need for external slicers, sync separators, Schmitt triggers, and filters. • Programmable bandwidth (100MHz to 780MHz) Glitchless, automatic Macrovision®- compliance is obtained by a digital Macrovision® detection function that detects and automatically removes Macrovision® from the HSYNC signal. • Pb-free (RoHS Compliant) Ease of use is also emphasized with features such as the elimination of PLL charge pump current/VCO range programming and single-bit switching between RGB and YPbPr signals. Automatic Black Level Compensation (ABLC™) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. • Projectors • Glitchless Macrovision®-compliant sync separator • Extremely fast recovery from VCR head switching • Low PLL clock jitter (250ps peak-to-peak @ 170MSPS) • 64 interpixel sampling positions • 0.35VP-P to 1.4VP-P video input range • RGB 4:4:4 and YUV 4:2:2 output formats • Low power (535mW @ 170MSPS) • Small 10mmx10mm 72 Ld QFN package • Completely independent 8-bit gain/10-bit offset control Applications • Digital TVs • Multifunction Monitors • Digital KVM • RGB Graphics Processing Simplified Block Diagram OFFSET DAC ABLC™ VOLTAGE CLAMP RGB/YPBPRIN 3 PGA + 8-BIT ADC 8 RGB/YUVOUT X3 HSYNCOUT VSYNCOUT SOGIN HSYNCIN HSOUT SYNC PROCESSING DIGITAL PLL PIXELCLKOUT VSYNCIN AFE CONFIGURATION AND CONTROL FN6535 Rev. 1.0 Jul 6, 2021 Page 1 of 28 © 2008 Renesas Electronics ISL98002 Ordering Information PART NUMBER (Note 1, 2) ISL98002CRZ-170 PART MARKING ISL98002CRZ -170 MAXIMUM PIXEL RATE PACKAGE DESCRIPTION (RoHS Compliant) PKG. DWG. # 170MHz 72 Ld QFN L72.10x10H CARRIER TYPE TEMP RANGE Tray 0°C to +70°C NOTE: 1. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. For Moisture Sensitivity Level (MSL), see the ISL98002 device page. For more information about MSL, see TB363. Block Diagram VCLAMP OFFSET DAC RIN2 VIN+ 8 PGA VIN- 8-BIT ADC + VCLAMP OFFSET DAC GIN1 GIN2 PGA VIN- 8-BIT ADC + 10 8 ABLC™ VIN+ VIN- PGA + R[7:0] ABLC™ 8 OFFSET DAC BIN2 10 8 VIN+ VCLAMP BIN1 ABLC™ 8-BIT ADC 8 OUTPUT DATA FORMATTER RIN1 10 8 G[7:0] B[7:0] DATACLK SOGIN1 DATACLK SOGIN2 HSYNCIN1 SYNC PROCESSING AFE CONFIGURATION AND CONTROL HSOUT VSYNCIN1 HSYNCOUT VSYNCOUT CLOCKINV XTALIN DIGITAL PLL XTALOUT XCLKOUT SCL SDA SADDR FN6535 Rev. 1.0 Jul 6, 2021 SERIAL INTERFACE Page 2 of 28 ISL98002 Absolute Maximum Ratings Thermal Information Voltage on VA, VD, or VX (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V Voltage on VADC, VCOREADC, VPLL, or VCORE (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Voltage on any analog input pin (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VA Voltage on any digital input pin (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Current into any output pin. . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Thermal Resistance JA (°C/W) 27 QFN Package (Note 3). . . . . . . . . . . . . . . . . . . . . . . Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . 3.3V ±10%, 1.8V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See TB379 for details. Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 170MHz, fXTAL = 25MHz, TA = +25°C, unless otherwise noted. SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT 170 MHz FULL CHANNEL CHARACTERISTICS Conversion Rate Per Channel ADC Resolution Missing Codes 10 8 Bits Guaranteed monotonic None DNL Differential Non-Linearity (Full-Channel) (Note 5) ±0.5 +1.0/-0.9 LSB INL Integral Non-Linearity (Full-Channel) (Note 5) ±1.1 ±3.25 LSB Gain Adjustment Range Gain Adjustment Resolution Gain Matching Between Channels Percent of full-scale Full Channel Offset Error, ABLC™ Enabled ADC LSBs, over time and temperature Offset Adjustment Range (ABLC™ Enabled or Disabled) ADC LSBs (See “Automatic Black Level Compensation (ABLC™) and Gain Control” on page 16) ±6 dB 8 Bits ±1 % ±0.125 ±0.5 ±127 LSB LSB ANALOG VIDEO INPUT CHARACTERISTICS (RIN, GIN, BIN) Input Range Input Bias Current 0.35 DC restore clamp off Input Capacitance Full Power Bandwidth Programmable 0.7 1.4 VP-P ±0.01 ±1 µA 5 pF 780 MHz 0 to 0.3 V 40 mV 5 pF 0.4 to 3.2 V 240 mV 1.2 k INPUT CHARACTERISTICS (SOGIN) VIH/VIL Input Threshold Voltage Programmable - see “Register Listing” on page 10 Hysteresis Centered around threshold Input Capacitance INPUT CHARACTERISTICS (HSYNCIN) VIH/VIL RIN Input Threshold Voltage Programmable - see “Register Listing” on page 10 Hysteresis Centered around threshold voltage Input Impedance FN6535 Rev. 1.0 Jul 6, 2021 Page 3 of 28 ISL98002 Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 170MHz, fXTAL = 25MHz, TA = +25°C, unless otherwise noted. (Continued) SYMBOL CIN PARAMETER COMMENT MIN Input Capacitance TYP MAX 5 UNIT pF DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINVIN, RESET) VIH Input HIGH Voltage VIL Input LOW Voltage I Input Leakage Current 2.0 V 0.8 RESET has a 70k pull-up to VD Input Capacitance V ±10 nA 5 pF SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNCIN) VT+ Low to High Threshold Voltage VT- High to Low Threshold Voltage I 1.45 V 0.95 Input Leakage Current Input Capacitance V ±10 nA 5 pF DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK) VOH Output HIGH Voltage, IO = 16mA VOL Output LOW Voltage, IO = -16mA 2.4 V 0.4 V DIGITAL OUTPUT CHARACTERISTICS (R, G, B, HSOUT, HSYNCOUT, VSYNCOUT) VOH Output HIGH Voltage, IO = 8mA VOL Output LOW Voltage, IO = -8mA RTRI Pull-down to GNDD When Three-state 2.4 V 0.4 RP, GP, BP, RS, GS, BS only 56 V k DIGITAL OUTPUT CHARACTERISTICS (SDA) VOH Output HIGH Voltage, IO = 4mA VOL Output LOW Voltage, IO = -4mA XCLKOUT only; SDA is open-drain 2.4 V 0.4 V POWER SUPPLY REQUIREMENTS VA Analog 3.3V Supply Voltage 3 3.3 3.6 V VD Digital 3.3V Supply Voltage 3 3.3 3.6 V VX Crystal Oscillator 3.3V Supply Voltage 3 3.3 3.6 V IA Analog 3.3V Supply Current 45 55 mA ID Digital 3.3V Supply Current 5 22 mA IX Crystal Oscillator 3.3V Supply Current 0.8 1.2 mA 1.8 2.0 V VADC VCORE With grayscale ramp input ADC Analog 1.8V Supply Voltage 1.65 Digital 1.8V Supply Voltage 1.65 1.8 2.0 V ADC Digital 1.8V Supply Voltage 1.65 1.8 2.0 V VPLL PLL 1.8V Supply Voltage 1.65 1.8 2.0 V IADC ADC Analog 1.8V Supply Current 110 120 mA Digital 1.8V Supply Current 70 80 mA ADC Digital 1.8V Supply Current 11 20 mA 2.25 3 mA VCOREADC ICORE ICOREADC IPLL PLL 1.8V Supply Current PD Total Power Dissipation ISL98002-170 With grayscale ramp input 535 600 mW Standby Mode ADCs, PLL powered down 35 80 mW PLL Jitter (Note 6) 250 450 ps p-p Sampling Phase Steps 5.6° per step 64 AC TIMING CHARACTERISTICS Sampling Phase Tempco FN6535 Rev. 1.0 Jul 6, 2021 ±1 ps/°C Page 4 of 28 ISL98002 Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 170MHz, fXTAL = 25MHz, TA = +25°C, unless otherwise noted. (Continued) SYMBOL PARAMETER Sampling Phase Differential Nonlinearity COMMENT MIN Degrees out-of-phase 360° TYP MAX UNIT ±3 ° HSYNC Frequency Range 10 150 kHz Crystal Frequency Range 23 25 27 MHz fXTALIN Frequency Range with External 3.3V Clock Signal Driving XTALIN 23 25 33.5 MHz tSETUP DATA Valid Before Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 4) 1.3 ns tHOLD DATA Valid After Rising Edge of DATACLK 2.0 ns fXTAL 15pF DATACLK load, 15pF DATA load (Note 4) AC TIMING CHARACTERISTICS (2-WIRE INTERFACE) fSCL SCL Clock Frequency 0 Maximum Width of a Glitch on SCL That Will 2 XTAL periods min Be Suppressed 80 400 kHz ns tAA SCL LOW to SDA Data Out Valid tBUF Time the Bus Must Be Free Before a New Transmission Can Start 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH 5 XTAL periods plus SDA’s RC time constant See comment µs Clock HIGH Time 0.6 µs tSU:STA Start Condition Set-up Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs 100 ns 0 ns 0.6 µs 160 ns tSU:DAT Data In Set-up Time tHD:DAT Data In Hold Time tSU:STO Stop Condition Set-up Time tDH Data Output Hold Time 4 XTAL periods min NOTES: 4. Setup and hold times are specified for a 170MHz DATACLK rate. 5. Linearity tested at room temperature and guaranteed across commercial temperature range by correlation to characterization. 6. Jitter tested at rated frequency (170MHz) and at minimum frequency (10MHz). FN6535 Rev. 1.0 Jul 6, 2021 Page 5 of 28 ISL98002 tHIGH tF SCL tLOW tR tSU:DAT tSU:STA SDA IN tHD:DAT tHD:STA tSU:STO tAA tDH tBUF SDA OUT FIGURE 1. 2-WIRE INTERFACE TIMING DATACLK DATACLK tHOLD tSETUP Pixel Data FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals HSYNCIN tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL Analog Video In P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 DATACLK 8 DATACLK Pipeline Latency RP/GP/BP[7:0] D0 D1 D2 D3 RS/GS/BS[7:0] HSOUT Programmable Width and Polarity FIGURE 3. OUTPUT MODE FN6535 Rev. 1.0 Jul 6, 2021 Page 6 of 28 ISL98002 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals HSYNCIN tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL Analog Video In P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 DATACLK 8.5 DATACLK Pipeline Latency GP[7:0] G0 (Yo) G1 (Y1) G2 (Y2) RP[7:0] B0 (Uo) R1 (V1) B2 (U2) BP[7:0] HSOUT Programmable Width and Polarity FIGURE 4. 4:2:2 OUTPUT MODE (FOR YUV SIGNALS) FN6535 Rev. 1.0 Jul 6, 2021 Page 7 of 28 P12 ISL98002 Pinout VSYNCOUT HSYNCOUT HSOUT VD DATACLK DATACLK R0 R1 R2 R3 R4 R5 R6 R7 VD VCORE VD NC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 ISL98002 (72 LD QFN) TOP VIEW VA 10 45 VD B IN 1 11 44 VD VA 12 43 B0 R IN 2 13 42 B1 G IN 2 14 41 B2 SOG IN 2 15 40 B3 B IN 2 16 39 B4 V COREADC 17 38 B5 HSYNC IN 1 18 37 B6 FN6535 Rev. 1.0 Jul 6, 2021 36 G7 B7 46 35 9 VD V ADC 34 G6 GND 47 33 8 NC SOG IN 1 32 G5 VCORE 48 31 7 SCL G IN 1 30 G4 SDA 49 29 6 SADDR VA 28 G3 RESET 50 27 5 VSYNCIN1 V ADC 26 G2 VPLL 51 25 4 CLOCKINVIN R IN 1 24 G1 XTALOUT 52 23 3 GND VA 22 NC XTALIN 53 21 2 VX NC 20 G0 NC 54 19 1 VA V ADC Page 8 of 28 ISL98002 Pin Descriptions SYMBOL QFN PIN #(s) DESCRIPTION RIN1 4 Analog input. Red channel. DC couple or AC couple through 0.1µF. GIN1 7 Analog input. Green channel. DC couple or AC couple through 0.1µF. BIN1 11 Analog input. Blue channel. DC couple or AC couple through 0.1µF. SOGIN1 8 Analog input. Sync on Green. Connect to GIN through a 0.01µF capacitor in series with a 500 resistor. HSYNCIN1 18 Digital input, 5V tolerant, 240mV hysteresis, 1.2k impedance to GND. Connect to HSYNC signal through a 680 series resistor. VSYNCIN1 27 Digital input, 5V tolerant, 500mV hysteresis. Connect to VSYNC signal. RIN2 13 Analog input. Red channel. DC couple or AC couple through 0.1µF. GIN2 14 Analog input. Green channel. DC couple or AC couple through 0.1µF. BIN2 16 Analog input. Blue channel. DC couple or AC couple through 0.1µF. SOGIN2 15 Analog input. Sync on Green. Connect to GIN through a 0.01µF capacitor in series with a 500 resistor. CLOCKINVIN 25 Digital input, 5V tolerant. When high, inverts the pixel sampling phase by 180°. Tie to GND if unused. RESET 28 Digital input, 5V tolerant, active low, 70k pull-up to VD. Take low for at least 1µs and then high again to reset the ISL98002. This pin is not necessary for normal use and may be tied directly to the VD supply. XTALIN 22 Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical Specifications” table on page 5 for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. XTALOUT 24 Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical Specifications” table on page 5 for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. SADDR 29 Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high. SCL 31 Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface. SDA 30 Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface. R7 thru R0 59 thru 66 G7 thru G0 46 thru 52, 54 B7 thru B0 36 thru 43 3.3V digital output. Red channel, primary pixel data. 56k pull-down when three-stated. 3.3V digital output. Green channel, primary pixel data. 56k pull-down when three-stated. 3.3V digital output. Blue channel, primary pixel data. 56k pull-down when three-stated. DATACLK 67 3.3V digital output. Data clock output. Equal to pixel clock rate. DATACLK 68 3.3V digital output. Inverse of DATACLK. HSOUT 70 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals). HSYNCOUT 71 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This output will pass composite sync signals and Macrovision signals if present on HSYNCIN or SOGIN. VSYNCOUT 72 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period. VA 3, 6, 10, 12, 19 Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1µF. VD 35, 44, 45, 56, 58, 69 Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1µF. VX 21 GND PAD, 23, 34 VADC 1, 5, 9 VCOREADC 17 VCORE 32, 57 26 VPLL NC Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GNDX with 0.1µF. Ground return. Internal power for the ADC’s analog. Connect to a 1.8V supply and bypass to GND with 0.1µF. Internal power for the ADC’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1µF. Internal power for core logic. Connect to a 1.8V supply and bypass each pin to GND with 0.1µF. Internal power for the PLL’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1µF. 2, 20, 33, 53, 55 Reserved. Do not connect anything to these pins. FN6535 Rev. 1.0 Jul 6, 2021 Page 9 of 28 ISL98002 Register Listing ADDRESS 0x00 0x01 0x02 0x03 REGISTER (DEFAULT VALUE) Device ID (read only) SYNC Status (read only) SYNC Polarity (read only) HSYNC Slicer (0x33) BIT(S) SOG Slicer (0x16) Device Revision 1 = initial silicon, 2 = second revision, etc. 7:4 Device ID 1 = ISL98002 0 HSYNC1 Active 0: HSYNC is Inactive 1: HSYNC is Active 1 N/A Returns 0 2 VSYNC1 Active 0: VSYNC is Inactive 1: VSYNC is Active 3 N/A Returns 0 4 SOG1 Active 0: SOG is Inactive 1: SOG is Active 5 SOG2 Active 0: SOG is Inactive 1: SOG is Active 6 PLL Locked 0: PLL is unlocked 1: PLL is locked to incoming HSYNC 7 CSYNC Detect at Sync Splitter 0: Composite Sync signal not detected 1: Composite Sync signal is detected 0 HSYNC Polarity 0: HSYNC is Active High 1: HSYNC is Active Low 1 N/A Returns 0 2 VSYNC Polarity 0: VSYNC is Active High 1: VSYNC is Active Low 3 N/A Returns 0 4 SOG1 TriLevel 0: SOG is BiLevel Sync 1: SOG is TriLevel Sync 5 SOG2 TriLevel 0: SOG is BiLevel Sync 1: SOG is TriLevel Sync 7:6 N/A Returns 0 2:0 HSYNC Threshold 000 = lowest (0.4V) 011 = default (1.6V) 111 = highest (3.2V) Note: All values referred to voltage at HSYNC input pin, 240mV hysteresis 6:3 Reserved Set to 0 Disable Glitch Filter 0: HSYNC/VSYNC Glitch Filter Enabled (default) 1: HSYNC/VSYNC Glitch Filter Disabled 3:0 SOG Threshold 0x0 = lowest (0mV) 0x6 = default (120mV) 20mV step size 0xF = highest (300mV) 4 SOG Filter Enable 0: SOG low pass filter disabled 1: SOG low pass filter enabled, 14MHz corner (default) 5 SOG Hysteresis Disable 0: 40mV SOG hysteresis enabled (default) 1: 40mV SOG hysteresis disabled Reserved Set to 00. 7:6 FN6535 Rev. 1.0 Jul 6, 2021 DESCRIPTION 3:0 7 0x04 FUNCTION NAME Page 10 of 28 ISL98002 Register Listing (Continued) ADDRESS 0x05 REGISTER (DEFAULT VALUE) Input configuration (0x00) BIT(S) FUNCTION NAME DESCRIPTION 0 Reserved Set to 0. 1 Input Coupling 0: AC coupled (positive input connected to clamp DAC during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DAC) 1: DC coupled (+ and - inputs are brought to pads and never connected to clamp DACs). Analog clamp signal is turned off in this mode. 2 RGB/YPbPr 0: RGB inputs Base ABLC target code = 0x00 for R, G, and B) 1: YPbPr inputs Base ABLC target code = 0x00 for G (Y) Base ABLC target code = 0x80 for R (Pr) and B (Pb) 3 Sync Type 0: Separate HSYNC/VSYNC 1: Composite (from SOG or CSYNC on HSYNC) 4 Composite Sync Source 0: SOGIN 1: HSYNCIN Note: If Sync Type = 0, the multiplexer will pass HSYNCIN regardless of the state of this bit. 5 COAST CLAMP enable 0: DC restore clamping and ABLC™ suspended during COAST 1: DC restore clamping and ABLC™ continue during COAST 6 Sync Mask Disable 0: Interval between HSYNC pulses masked (preventing PLL from seeing Macrovision and any spurious glitches) 1: Interval between HSYNC pulses not masked (Macrovision will cause PLL to lose lock) 7 HSYNCOUT Mask Disable 0: HSYNCOUT signal is masked (any Macrovision, sync glitches on incoming SYNC are stripped from HSYNCOUT) 1: HSYNCOUT signal is not masked (any Macrovision, sync glitches on incoming SYNC appear on HSYNCOUT) If Sync Mask Disable = 1, HSYNCOUT is not masked. Channel gain, where: gain (V/V) = 0.5 + [7:0]/170 0x06 Red Gain (0x55) 7:0 Red Gain 0x07 Green Gain (0x55) 7:0 Green Gain 0x08 Blue Gain (0x55) 7:0 Blue Gain 0x00: gain = 0.5V/V (1.4VP-P input = full range of ADC) 0x55: gain = 1.0V/V (0.7VP-P input = full range of ADC) 0xFF: gain = 2.0V/V (0.35VP-P input = full range of ADC) FN6535 Rev. 1.0 Jul 6, 2021 Page 11 of 28 ISL98002 Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME 0x09 Red Offset (0x80) 7:0 Red Offset 0x0A Green Offset (0x80) 7:0 Green Offset 0x0B Blue Offset (0x80) 7:0 Blue Offset 0x0C Offset DAC Configuration (0x00) 0x0D AFE Bandwidth (0x2E) DESCRIPTION ABLC™ enabled: digital offset control. A 1 LSB change in this register will shift the ADC output by 1 LSB. ABLC™ disabled: analog offset control. These bits go to the upper 8-bits of the 10-bit offset DAC. A 1 LSB change in this register will shift the ADC output approximately 1 LSB (Offset DAC range = 0) or 0.5LSBs (Offset DAC range = 1). 0x00 = min DAC value or -0x80 digital offset, 0x80 = mid DAC value or 0x00 digital offset, 0xFF = max DAC value or +0x7F digital offset 0 Offset DAC Range 0: ±½ ADC full-scale (1 DAC LSB ~ 1 ADC LSB) 1: ±¼ ADC full-scale (1 DAC LSB ~ ½ ADC LSB) 1 Reserved Set to 0. 3:2 Red Offset DAC LSBs 5:4 Green Offset DAC LSBs These bits are the LSBs necessary for 10-bit manual offset DAC control. Combine with their respective MSBs in registers 0x09, 0x0A, and 0x0B to achieve 10-bit offset DAC control. 7:6 Blue Offset DAC LSBs 0 Unused Value doesn’t matter 3:1 AFE BW 3dB point for AFE lowpass filter 000b: 100MHz 111b: 780MHz (default) 7:4 Peaking 0x0: Peaking off 0x1: Moderate peaking 0x2: Maximum recommended peaking (default) Values above 2 are not recommended. 14-bit HTOTAL (number of active pixels) value The minimum HTOTAL value supported is 0x200. HTOTAL to PLL is updated on LSB write only. 0x0E PLL Htotal MSB (0x03) 5:0 PLL Htotal MSB 0x0F PLL Htotal LSB (0x20) 7:0 PLL Htotal LSB 0x10 PLL Sampling Phase (0x00) 5:0 PLL Sampling Phase Used to control the phase of the ADC’s sample point relative to the period of a pixel. Adjust to obtain optimum image quality. One step = 5.625° (1.56% of pixel period). 0x11 PLL Pre-coast (0x04) 7:0 Pre-coast Number of lines the PLL will coast prior to the start of VSYNC. 0x12 PLL Post-coast (0x04) 7:0 Post-coast Number of lines the PLL will coast after the end of VSYNC. FN6535 Rev. 1.0 Jul 6, 2021 Page 12 of 28 ISL98002 Register Listing (Continued) ADDRESS 0x13 REGISTER (DEFAULT VALUE) PLL Misc (0x04) BIT(S) FUNCTION NAME DESCRIPTION 0 PLL Lock Edge HSYNC 0: Lock on trailing edge of HSYNC (default) 1: Lock on leading edge of HSYNC 1 Reserved Set to 0 2 Reserved Set to 0 3 CLKINVIN Pin Disable 0: CLKINVIN pin enabled (default) 1: CLKINVIN pin disabled (internally forced low) 5:4 CLKINVIN Pin Function 00: CLKINV (default) 01: External CLAMP (See Note) 10: External COAST 11: External PIXCLK Note: the CLAMP pulse is used to - perform a DC restore (if enabled) - start the ABLC™ function (if enabled), and - update the data to the Offset DACs (always). In the default internal CLAMP mode, the ISL98002 automatically generates the CLAMP pulse. If External CLAMP is selected, the Offset DAC values only change on the leading edge of CLAMP. If there is no internal clamp signal, there will be up to a 100ms delay between when the PGA gain or offset DAC register is written to, and when the PGA or offset DAC is actually updated. 6 Reserved Set to 0 7 Reserved Set to 1 Pixel after HSYNCIN trailing edge to begin DC restore and ABLC™ functions. 13-bits. Set this register to the first stable black pixel following the trailing edge of HSYNCIN. 0x14 DC Restore and ABLC™ starting pixel MSB (0x00) 4:0 DC Restore and ABLC™ starting pixel (MSB) 0x15 DC Restore and ABLC™ starting pixel LSB (0x03) 7:0 DC Restore and ABLC™ starting pixel (LSB) 0x16 DC Restore Clamp Width (0x10) 7:0 DC Restore clamp width (pixels) Width of DC restore clamp used in AC-coupled configurations. Has no effect on ABLC™. Minimum value is 0x02 (a setting of 0x01 or 0x00 will not generate a clamp pulse). 0x17 ABLC™ Configuration (0x40) 0 ABLC™ disable 0: ABLC™ enabled (default) 1: ABLC™ disabled 1 Reserved Set to 0. 3:2 ABLC™ pixel width Number of black pixels averaged every line for ABLC™ function 00: 16 pixels [default] 01: 32 pixels 10: 64 pixels 11: 128 pixels 6:4 ABLC™ bandwidth ABLC™ Time constant (lines) = 2(5+[6:4]) 000 = 32 lines 100 = 256 lines (default) 111 = 4096 lines Reserved Set to 0. 7 FN6535 Rev. 1.0 Jul 6, 2021 Page 13 of 28 ISL98002 Register Listing (Continued) ADDRESS 0x18 REGISTER (DEFAULT VALUE) Output Format (0x00) 0x19 HSOUT Width (0x10) 0x1A Output Signal Disable (0x00) 0x1B 0x1C Power Control (0x00) PLL Tuning (0x49) FN6535 Rev. 1.0 Jul 6, 2021 BIT(S) FUNCTION NAME DESCRIPTION 0 Reserved Set to 0 1 Reserved Set to 0 2 Reserved Set to 0 3 UV order (422 mode only) 0: U0 V0 U2 V2 U4 V4 U6 V6… (default) 1: U0 V1 U2 V3 U4 V5 U6 V7… (X980xx) 4 422 mode 0: Data is formatted as 4:4:4 (RGB, default) 1: Data is decimated to 4:2:2 (YUV), blue channel is driven low 5 DATACLK Polarity 0: HSOUT and Pixel Data changes on falling edge of DATACLK (default) 1: HSOUT and Pixel Data changes on rising edge of DATACLK 6 Reserved Set to 0 7 HSOUT Polarity 0: Active High (default) 1: Active Low HSOUT Width HSOUT width, in pixels. Minimum value is 0x01 0 Three-state R[7:0] 0 = Output byte enabled 1 = Output byte three-stated These bits override all other I/O settings Output data pins have 56k pull-down resistors to GND. 1 Reserved Set to 1 2 Three-state G[7:0] 3 Reserved 4 Three-state B[7:0] 5 Reserved Set to 1 6 Three-state DATACLK 0 = DATACLK enabled 1 = DATACLK three-stated 7 Three-state DATACLK 0 = DATACLK enabled 1 = DATACLK three-stated 0 Red Power-down 0 = Red ADC operational (default) 1 = Red ADC powered down 1 Green Power-down 0 = Green ADC operational (default) 1 = Green ADC powered down 2 Blue Power-down 0 = Blue ADC operational (default) 1 = Blue ADC powered down 3 PLL Power-down 0 = PLL operational (default) 1 = PLL powered down 7:4 Reserved Set to 0 7:0 Reserved Use default setting of 0x49 for all PC and video modes except signals coming from an analog VCR. Set to 0x4C for analog videotape compatibility. 7:0 Set to 1 Page 14 of 28 ISL98002 Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION 0x1D Red ABLC Target (0x00) 7:0 Reserved This is a 2's complement number controlling the target code of the Red ADC output when ABLC is enabled. In RGB mode, the Red ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F). In YPbPr mode, the Red ADC output will be servoed to 0x80 + the number in this register (-0x80 to +0x7F). Note: This register does NOT disable the digital offset adder. Both functions can be used simultaneously. 0x1E Green ABLC Target (0x00) 7:0 Reserved This is a 2's complement number controlling the target code of the Green ADC output when ABLC is enabled. In RGB and YPbPr modes, the Green ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F). Note: This register does NOT disable the digital offset adder. Both functions can be used simultaneously. 0x1F Blue ABLC Target (0x00) 7:0 Reserved This is a 2's complement number controlling the target code of the Blue ADC output when ABLC is enabled. In RGB mode, the Blue ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F). In YPbPr mode, the Blue ADC output will be servoed to 0x80 + the number in this register (-0x80 to +0x7F). Note: This register does NOT disable the digital offset adder. Both functions can be used simultaneously. 0x23 DC Restore Clamp (0x18) 3:0 Reserved Set to 1000 6:4 DC Restore Clamp Impedance DC Restore clamp's ON-resistance. Shared for all three channels 0: Infinite (clamp disconnected) (default) 1: 1600 2: 800 3: 533 4: 400 5: 320 6: 267 7: 228 Reserved Set to 0 7 FN6535 Rev. 1.0 Jul 6, 2021 Page 15 of 28 ISL98002 Register Listing (Continued) ADDRESS 0x25 REGISTER (DEFAULT VALUE) Sync Separator Control (0x00) BIT(S) DESCRIPTION 0 Three-state Sync Outputs 0: VSYNCOUT, HSYNCOUT, HSOUT are active (default) 1: VSYNCOUT, HSYNCOUT, HSOUT are in three-state 1 COAST Polarity 0: Coast active high (default) 1: Coast active low Set to 0 for internal VSYNC extracted from CSYNC. Set to 0 or 1 as appropriate to match external VSYNC or external COAST. 2 HSOUT Lock Edge 0: HSOUT's trailing edge is locked to selected HSYNCIN's lock edge. Leading edge moves backward in time as HSOUT width is increased (X980xx default) 1: HSOUT's leading edge is locked to selected HSYNCIN's lock edge. Trailing edge moves forward in time as HSOUT width is increased 3 Reserved Set to 0 4 VSYNCOUT Mode 0: VSYNCOUT is aligned to HSYNCOUT edge, providing “perfect” VSYNC signal (default) 1: VSYNCOUT is “raw” integrator output 5 Reserved Set to 0 6 Reserved Set to 0 7 Reserved Set to 0 Technical Highlights The ISL98002 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL All video AFEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green). Historically, this has been implemented as a traditional analog PLL. At SXGA and lower resolutions, an analog PLL solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, VCO ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). As display resolutions and refresh rates have increased, however, the pixel period has shrunk. An XGA pixel at a 60Hz refresh rate has 15.4ns to change and settle to its new value. But at UXGA 75Hz, the pixel period is 4.9ns. Most consumer graphics cards (even the ones with “350MHz” DACs) spend most of that time slewing to the new pixel value. The pixel may settle to its final value with 1ns or less before it begins slewing to the next pixel. In many cases, it rings and never settles at all. Thus precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The ISL98002's DPLL has less than 250ps of jitter, peak-to-peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs the industry standard FN6535 Rev. 1.0 Jul 6, 2021 FUNCTION NAME 32), for fine, accurate positioning of the sampling point. The crystal-locked NCO inside the DPLL completely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. An intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (10MHz or higher) to UXGA 60Hz (170MHz, with the ISL98002-170). The DPLL eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals. Automatic Black Level Compensation (ABLC™) and Gain Control Traditional video AFEs have an offset DAC prior to the ADC, to both correct for offsets on the incoming video signals and add/subtract an offset for user “brightness control” without sacrificing the 8-bit dynamic range of the ADC. This solution is adequate, but it places significant requirements on the system's firmware, which must execute a loop that detects the black portion of the signal and then serves the offset DACs until that offset is nulled (or produces the desired ADC output code). Once this has been accomplished, the offset (both the offset in the AFE and the offset of the video card generating the signal) is subject to drift (the temperature inside a monitor or projector can easily change +50°C) between power-on/offset calibration on a cold morning and the temperature reached once the monitor and the monitor's environment has reached a steady state. Offset can drift significantly over +50°C, reducing image quality and Page 16 of 28 ISL98002 requiring that the user do a manual calibration once the monitor has warmed up. In addition to drift, many AFEs exhibit interaction between the offset and gain controls. When the gain is changed, the magnitude of the offset is changed as well. This again increases the complexity of the firmware as it tries to optimize gain and offset settings for a given video input signal. Instead of adjusting just the offset then the gain, both have to be adjusted interactively until the desired ADC output is reached. The ISL98002 simplifies offset and gain adjustment and completely eliminates offset drift using its Automatic Black Level Compensation (ABLC™) function. ABLC™ monitors the black level and continuously adjusts the ISL98002's 10-bit offset DACs to null out the offset. Any offset, whether due to the video source or the ISL98002's analog amplifiers, is eliminated with 10-bit (1/4 of an ADC LSB) accuracy. Any drift is compensated for well before it can have a visible effect. Manual offset adjustment control is still available (an 8-bit register allows the firmware to adjust the offset ±64 codes) in exactly 1 ADC LSB increments. Gain is now completely independent of offset (adjusting the gain no longer affects the offset) so there is no longer a need to program the firmware to cope with interactive offset and gain controls. Finally, there should be no concerns over ABLC™ itself introducing visible artifacts; it doesn't. ABLC™ functions at a very low frequency, changing the offset in 1/4 LSB increments, so it can't cause visible brightness fluctuations. Once ABLC™ is locked, if the offset doesn't drift, the DACs won't change. If desired, ABLC™ can be disabled, allowing the firmware to work in the traditional way, with 10-bit offset DACs under the firmware's control. Gain and Offset Control To simplify image optimization algorithms, the ISL98002 features fully-independent gain and offset adjustment. Changing the gain does not affect the DC offset, and the weight of an offset DAC LSB does not vary depending on the gain setting. The full-scale gain is set in the three 8-bit registers (0x06-0x08). The ISL98002 can accept input signals with amplitudes ranging from 0.35VP-P to 1.4VP-P. The offset controls shift the entire RGB input range, changing the input image brightness. Three separate registers provide independent control of the R, G, and B channels. Their nominal setting is 0x80, which forces the ADC to output code 0x00 (or 0x80 for the R (Pr) and B (Pb) channels in YPbPr mode) during the back porch period when ABLC™ is enabled. FN6535 Rev. 1.0 Jul 6, 2021 Functional Description Inputs The ISL98002 digitizes analog video inputs in both RGB and Component (YPbPr) formats, with or without embedded sync (SOG). RGB Inputs For RGB inputs, the black/blank levels are identical and equal to 0V. The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals. Component YPbPr Inputs In addition to RGB and RGB with SOG, the ISL98002 has an option that is compatible with the component YPbPr video inputs typically generated by DVD players. While the ISL98002 digitizes signals in these color spaces, it does not perform color space conversion; if it digitizes an RGB signal, it outputs digital RGB, while if it digitizes a YPbPr signal, it outputs digital YCbCr, also called YUV. The Luminance (Y) signal is applied to the Green Channel and is processed in a manner identical to the Green input with SOG described previously. The color difference signals Pb and Pr are bipolar and swing both above and below the black level. When the YPbPr mode is enabled, the black level output for the color difference channels shifts to a mid scale value of 0x80. Setting configuration register 0x05[2] = 1 enables the YPbPr signal processing mode of operation as shown in Table 1. TABLE 1. YUV MAPPING (4:4:4) INPUT SIGNAL ISL98002 INPUT CHANNEL ISL98002 OUTPUT ASSIGNMENT OUTPUT SIGNAL Y Green Green Y0Y1Y2Y3 Pb Blue Blue U0U1U2U3 Pr Red Red V0V1V2V3 The ISL98002 can optionally decimate the incoming data to provide a 4:2:2 output stream (configuration register 0x18[4] = 1), as shown in Table 2. TABLE 2. YUV MAPPING (4:2:2) INPUT SIGNAL ISL98002 INPUT CHANNEL ISL98002 OUTPUT ASSIGNMENT OUTPUT SIGNAL Y Green Green Y0Y1Y2Y3 Pb Blue Blue driven low Pr Red Red U0V0U2V2 There is also a “compatibility mode” (enabled by setting bit 3 of register 0x18 to a 1) that outputs the U and V data with the format used by the previous generation (“X980xx”) series of AFEs, shown in Table 3. Page 17 of 28 ISL98002 TABLE 3. YUV MAPPING (4:2:2) INPUT SIGNAL ISL98002 INPUT CHANNEL ISL98002 OUTPUT ASSIGNMENT OUTPUT SIGNAL Y Green Green Y0Y1Y2Y3 Pb Blue Blue driven low Pr Red Red U0V1U2V3 Input Coupling Inputs can be either AC-coupled (default) or DC-coupled (see register 0x05[1]). AC coupling is usually preferred since it allows video signals with substantial DC offsets to be accurately digitized. The ISL98002 provides a complete internal DC-restore function, including the DC restore clamp (see Figure 5) and programmable clamp timing (registers 0x14, 0x15, 0x16, and 0x23). When AC-coupled, the DC restore clamp is applied at every line, a programmable number of pixels after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the clamp will not be applied while the DPLL is coasting, preventing any clamp voltage errors from composite sync edges, equalization pulses, or Macrovision signals. After the trailing edge of HSYNC, the DC restore clamp is turned on after the number of pixels specified in the DC Restore and ABLC™ Starting Pixel registers (0x14 and 0x15) has been reached. The clamp is applied for the number of pixels specified by the DC Restore Clamp Width Register (0x16). The clamp can be applied to the back porch of the video, or to the front porch (by increasing the DC Restore and ABLC™ Starting Pixel registers so all the active video pixels are skipped). If DC-coupled operation is desired, the input to the ADC will be the difference between the input signal (RIN, for example) and that channel’s ground reference (RGBGND in that example). AUTOMATIC BLACK LEVEL COMPENSATION (ABLC™) LOOP DC RESTORATION CLAMP GENERATION DC RESTORE CLAMP DAC R(GB)IN R(GB)GND TO ABLC BLOCK OFFSET DAC FIXED OFFSET 10 ABLC™ 10 OFFSET CONTROL REGISTERS 10 0X00 VCLAMP 8 8 ABLC™ FIXED OFFSET ABLC™ 8 VIN+ PGA VIN- INPUT BANDWIDTH 8-BIT ADC 8 8 TO OUTPUT FORMATTER BANDWIDTH CONTROL FIGURE 5. VIDEO FLOW (INCLUDING ABLC™) FN6535 Rev. 1.0 Jul 6, 2021 Page 18 of 28 ISL98002 SOG The ISL98002 has SYNC activity detect functions to help the firmware determine which sync source is available. For component YPbPr signals, the sync signal is embedded on the Y-Channel’s video, which is connected to the green input, hence the name SOG (Sync on Green). The horizontal sync information is encoded onto the video input by adding the sync tip during the blanking interval. The sync tip level is typically 0.3V below the video black level. Macrovision The ISL98002 automatically detects the presence of Macrovision-encoded video. When Macrovision is detected, it generates a mask signal that is ANDed with the incoming SOG CSYNC signal to remove the Macrovision before the HSYNC goes to the PLL. No additional programming is required to support Macrovision. To minimize the loading on the Green channel, the SOG input for each of the Green channels should be AC-coupled to the ISL98002 through a series combination of a 10nF capacitor and a 500 resistor. Inside the ISL98002, a window comparator compares the SOG signal with an internal 4-bit programmable threshold level reference ranging from 0mV to 300mV below the minimum sync level. The SOG threshold level, hysteresis, and low-pass filter is programmed via register 0x04. If the Sync On Green function is not needed, the SOGIN pin(s) may be left unconnected. If desired (it is never necessary in normal operation), this function can be disabled by setting the Sync Mask Disable (register 0x05 bit 6) to a 1. The mask signal is also applied to the HSYNCOUT signal. When Sync Mask Disable = 0, any Macrovision present on the incoming sync will not be visible on HSYNCOUT. If the application requires the Macrovision pulses to be visible on HSYNCOUT, set the HSYNCOUT Mask Disable bit (register 0x05 bit 7). SYNC Processing The ISL98002 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync On Green (SOG) signal embedded on the Green video input. Due to the reduced number of pins in the 72 Ld QFN package, Channel-2 on the ISL98002 only accepts sync input on SOG. Headswitching from Analog Videotape Signals Occasionally this AFE may be used to digitize signals coming from analog videotape sources. The most common example of this is a Digital VCR (which for best signal quality would be connected to this AFE with a component YPbPr ACTIVITY 0X01[6:0] AND POLARITY 0X02[5:0] DETECT HSYNCOUT CSYNC SOURCE HSYNCIN SOGIN HSYNC1 SLICER 0X03[2:0] HSYNCIN SOG SLICER 0X1C SOGIN VSYNCIN 00, 10, 11: HSYNCIN SYNC TYPE SYNC SPLITTER 0X05[4:3 ] VSYNC 01: SOGIN 1: SYNC SPLTR 0X05[3] VSYNC IN VSYNC OUT 0: VSYNCIN COAST GENERATION 0X11, 0X12, 0X13[2] PIXEL DATA FROM AFE CLOCKINVIN PLL XTALIN HS 0X0E THROUGH 0X13 PIXCLK 0: ÷1 XTALOUT G[7:0] OUTPUT FORMATTER 0X18, 0X19, 0X1A B[7:0] DATACLK DATACLK 0X13 [6] ÷2 R[7:0] 24 HSOUT 1: ÷2 XTALCLOCKOUT FIGURE 6. SYNC FLOW FN6535 Rev. 1.0 Jul 6, 2021 Page 19 of 28 ISL98002 connection). If the digital VCR is playing an older analog VHS tape, the sync signals from the VCR may contain the worst of the traditional analog tape artifacts: headswitching. Headswitching is traditionally the enemy of PLLs with large capture ranges, because a headswitch can cause the HSYNC period to change by as much as ±90%. To the PLL, this can look like a frequency change of -50% to greater than +900%, causing errors in the output frequency (and obviously the phase) to change. Subsequent HSYNCs have the correct, original period, but most analog PLLs will take dozens of lines to settle back to the correct frequency and phase after a headswitch disturbance. This causes the top of the image to “tear” during normal playback. In “trick modes” (fast forward and rewind), the HSYNC signal has multiple headswitch-like discontinuities, and many PLLs never settle to the correct value before the next headswitch, rendering the image completely unintelligible. Renesas’ DPLL has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. This is done by changing the contents of register 0x1C to 0x4C. This increases the phase error gain to 100%. Because a phase setting this high will slightly increase jitter, the default setting (0x49) for register 0x1C is recommended for all other sync sources. PGA The ISL98002’s Programmable Gain Amplifier (PGA) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is calculated in Equation 1: V GainCode Gain  ---- = 0.5 + ---------------------------- V 170 (EQ. 1) where GainCode is the value in the Gain register for that particular color. Note that for a gain of 1V/V, the GainCode should be 85 (0x55). This is a different center value than the 128 (0x80) value used by some other AFEs, so the firmware should take this into account when adjusting gains. The PGAs are updated by the internal clamp signal once per line. In normal operation, this means that there is a maximum delay of one HSYNC period between a write to a Gain register for a particular color and the corresponding change in that channel’s actual PGA gain. If there is no regular HSYNC/SOG source, or if the external clamp option is enabled (register 0x13[5:4]) but there is no external clamp signal being generated, it may take up to 100ms for a write to the Gain register to update the PGA. This is not an issue in normal operation with RGB and YPbPr signals. Offset DAC The ISL98002 features a 10-bit Digital-to-Analog Converter (DAC) per channel to provide extremely fine control over the full channel offset. The DAC is placed after the PGA to eliminate interaction between the PGA (controlling “contrast”) and the Offset DAC (controlling “brightness”). In normal operation, the Offset DAC is controlled by the ABLC™ circuit, ensuring that the offset is always reduced to sub-LSB levels (see “ABLC™” for more information). When ABLC™ is enabled, the Offset registers (0x09, 0x0A, 0x0B) control a digital offset added to or subtracted from the output of the ADC. This mode provides the best image quality and eliminates the need for any offset calibration. If desired, ABLC™ can be disabled (0x17[0] = 1) and the Offset DAC programmed manually, with the 8 most significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least significant bits in register 0x0C[7:2]. The default Offset DAC range is ±127 ADC LSBs. Setting 0x0C[0] = 1 reduces the swing of the Offset DAC by 50%, making 1 Offset DAC LSB the weight of 1/8th of an ADC LSB. This provides the finest offset control and applies to both ABLC™ and manual modes. Automatic Black Level Compensation (ABLC™) ABLC™ is a function that continuously removes all offset errors from the incoming video signal by monitoring the offset at the output of the ADC and servoing the 10-bit analog DAC to force those errors to zero. When ABLC™ is enabled, the user offset control is a digital adder, with 8-bit resolution (see Table 4). When the ABLC™ function is enabled (0x17[0] = 0), the ABLC function is executed every line after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the ABLC™ function will be not be triggered while the DPLL is coasting, TABLE 4. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT OFFSET DAC RANGE 0X0C[0] 10-BIT OFFSET DAC RESOLUTION ABLC™ 0x17[0] USER OFFSET CONTROL RESOLUTION USING REGISTERS 0x09 - 0X0B ONLY (8-BIT OFFSET CONTROL) USER OFFSET CONTROL RESOLUTION USING REGISTERS 0X09 - 0x0B AND 0X0C[7:2](10-BIT OFFSET CONTROL) 0 0.25 ADC LSBs (0.68mV) 0 (ABLC on) 1.0 ADC LSB (digital offset control) N/A 1 0.125 ADC LSBs (0.34mV) 0 (ABLC on) 1.0 ADC LSB (digital offset control) N/A 0 0.25 ADC LSBs (0.68mV) 1 (ABLC off) 1.0 ADC LSB (analog offset control) 0.25 ADC LSB (analog offset control) 1 0.125 ADC LSBs (0.34mV) 1 (ABLC off) 0.5 ADC LSB (analog offset control) 0.125 ADC LSB (analog offset control) FN6535 Rev. 1.0 Jul 6, 2021 Page 20 of 28 ISL98002 preventing any composite sync edges, equalization pulses, or Macrovision signals from corrupting the black data and potentially adding a small error in the ABLC™ accumulator. Relative to a 5V input, the hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer step size will be 400mV*5V/3.3V = 600mV per step. After the trailing edge of HSYNC, the start of ABLC™ is delayed by the number of pixels specified in registers 0x14 and 0x15. After that delay, the number of pixels specified by register 0x17[3:2] are averaged together and added to the ABLC™’s accumulator. The accumulator stores the average black levels for the number of lines specified by register 0x17[6:4], which is then used to generate a 10-bit DAC value. SOG Slicer The default values provide excellent results with offset stability and absolute accuracy better than 1 ADC LSB for most input signals. SYNC Status and Polarity Detection ADC The ISL98002 features 3 fully differential, high-speed 8-bit ADCs. Clock Generation A Digital Phase Lock Loop (DPLL) is employed to generate the pixel clock frequency. The HSYNC input and the external XTAL provide a reference frequency to the PLL. The PLL then generates the pixel clock frequency that is equal to the incoming HSYNC frequency times the HTOTAL value programmed into registers 0x0E and 0x0F. The stability of the clock is very important and correlates directly with the quality of the image. During each pixel time transition, there is a small window where the signal is slewing from the old pixel amplitude and settling to the new pixel value. At higher frequencies, the pixel signal transitions at a faster rate, which makes the stable pixel time even smaller. Any jitter in the pixel clock reduces the effective stable pixel time and thus the sample window in which pixel sampling can be made accurately. Sampling Phase The ISL98002 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. The sampling phase register is 0x10. HSYNC Slicer To further minimize jitter, the HSYNC inputs are treated as analog signals, and brought into a precision slicer block with thresholds programmable in 400mV steps with 240mV of hysteresis, and a subsequent digital glitch filter that ignores any HSYNC transitions within 100ns of the initial transition. This processing greatly increases the AFE’s rejection of ringing and reflections on the HSYNC line and allows the AFE to perform well, even with pathological HSYNC signals. Voltages given previously and in the “HSYNC Slicer” on page 21 (register description), are with respect to a 3.3V sync signal at the HSYNCIN input pin. To achieve 5V compatibility, a 680 series resistor should be placed between the HSYNC source and the HSYNCIN input pin. FN6535 Rev. 1.0 Jul 6, 2021 The SOG input has programmable threshold, 40mV of hysteresis, and an optional low pass filter that can be used to remove high frequency video spikes (generated by overzealous video peaking in a DVD player, for example) that can cause false SOG triggers. The SOG threshold sets the comparator threshold relative to the sync tip (the bottom of the SOG pulse). The SYNC Status register (0x01) and the SYNC Polarity register (0x02) continuously monitor all 3 sync inputs (VSYNCIN, HSYNCIN, and SOGIN) and report their status. However, accurate sync activity detection is always a challenge. Noise and repetitive video patterns on the Green channel may look like SOG activity when there actually is no SOG signal, while non-standard SOG signals and trilevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected. As a consequence, not all of the activity detect bits in the ISL98002 are correct under all conditions. Table 5 on page 22 shows how to use the SYNC Status register (0x01) to identify the presence and type of sync source. The firmware should go through the table in the order shown, stopping at the first entry that matches the activity indicators in the SYNC Status register. Final validation of composite sync sources (SOG or Composite sync on HSYNC) should be done by setting the Input Configuration register (0x05) to the composite sync source determined by Table 5, and confirming that the CSYNC detect bit is set. The accuracy of the Trilevel Sync Detect bit can be increased by multiple reads of the Trilevel Sync detect bit. See “TriLevel Sync Detect” on page 22 for more details. For best SOG operation, the SOG low pass filter (register 0x04[4] should always be enabled to reject the high frequency peaking often seen on video signals. HSYNC and VSYNC Activity Detect Activity on these bits always indicates valid sync pulses, so they should have the highest priority and be used even if the SOG activity bit is also set. SOG Activity Detect The SOG Activity Detect bit monitors the output of the SOG slicer, looking for 64 consecutive pulses with the same period and duty cycle. If there is no signal on the Green (or Y) channel, the SOG slicer will clamp the video to a DC level and will reject any sporadic noise. There should be no false positive SOG detects if there is no video on Green (or Y-Channel). Page 21 of 28 ISL98002 If there is video on Green (or Y-Channel) with no valid SOG signal, the SOG activity detect bit may sometimes report false positives (it will detect SOG when no SOG is actually present). This is due to the presence of video with a repetitive pattern that creates a waveform similar to SOG. For example, the desktop of a PC operating system is black during the front porch, horizontal sync, and back porch, then increases to a larger value for the video portion of the screen. This creates a repetitive video waveform very similar to SOG that may falsely trigger the SOG Activity detect bit. However, in these cases where there is active video without SOG, the SYNC information will be provided either as separate H and V sync on HSYNCIN and VSYNCIN, or composite sync on HSYNCIN. HSYNCIN and VSYNCIN should therefore be used to qualify SOG. The SOG Active bit should only be considered valid if HSYNC Activity Detect = 0. Note: Some pattern generators can output HSYNC and SOG simultaneously, in which case both the HSYNC and the SOG activity bits will be set, and valid. Even in this case, however, the monitor should still choose HSYNC over SOG. TriLevel Sync Detect Unlike SOG detect, the TriLevel Sync Detect function does not check for 64 consecutive trilevel pulses in a row, and is therefore less robust than the SOG detect function. It will report false positives for SOG-less video for the same reasons the SOG activity detect does, and should therefore be qualified with both HSYNC and SOG. TriLevel Sync Detect should only be considered valid if HSYNC Activity Detect = 0 and SOG Activity Detect = 1. If there is a SOG signal, the TriLevel Detect bit will operate correctly for standard trilevel sync levels (600mVP-P). In some real-world situations, the peak-to-peak sync amplitude may be significantly smaller, sometimes 300mVp-p or less. In these cases the sync slicer will continue to operate correctly, but the TriLevel Detect bit may not be set. Trilevel detection accuracy can be enhanced by polling the trilevel bit multiple times. If HSYNC is inactive, SOG is present, and the TriLevel Sync Detect bit is read as a 1, there is a high likelihood there is trilevel sync. TABLE 5. SYNC SOURCE DETECTION TABLE HSYNC DETECT VSYNC DETECT SOG DETECT TRILEVEL DETECT 1 1 X X Sync is on HSYNC and VSYNC 1 0 X X Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on HSYNC and confirm that CSYNC detect bit is set. 0 0 1 0 Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude is too low to set TriLevel Detect bit. Use video mode table to determine if this video mode is likely to have TriLevel sync, and set clamp start, width values appropriately if it is. 0 0 1 1 Sync is composite sync on SOG. Sync is likely to be trilevel. 0 0 0 X No valid sync sources on any input. FN6535 Rev. 1.0 Jul 6, 2021 RESULT Page 22 of 28 ISL98002 CSYNC Present HSOUT If a composite sync source (either CSYNC on HSYNC or SOG) is selected through bits 3 and 4 of register 0x05, the CSYNC Present bit in register 0x01 should be set. CSYNC Present detects the presence of a low frequency, repetitive signal inside HSYNC, which indicates a VSYNC signal. The CSYNC Present bit should be used to confirm that the signal being received is a reliable composite sync source. HSOUT is generated by the ISL98002’s control logic and is synchronized to the output DATACLK and the digital pixel data on the output databus. Its trailing edge is aligned with pixel 0. Its width, in units of pixels, is determined by register 0x19, and its polarity is determined by register 0x18[7]. As the width is increased, the trailing edge stays aligned with pixel 0, while the leading edge is moved backwards in time relative to pixel 0. HSOUT is used by the scaler to signal the start of a new line of pixels. SYNC Output Signals The ISL98002 has 2 types of SYNC signals, HSYNCOUT and VSYNCOUT, and HSOUT. HSYNCOUT and VSYNCOUT are buffered versions of the incoming sync signals; no synchronization is done. These signals are used for mode detection. HSOUT is generated by the ISL98002’s logic and is synchronized to the output DATACLK and the digital pixel data on the output databus. HSOUT is used to signal the start of a new line of digital data. Both HSYNCOUT and VSYNCOUT (including the sync separator function) remain active in power-down mode. This allows them to be used in conjunction with the Sync Status registers to detect valid video without powering up the ISL98002. HSYNCOUT HSYNCOUT is an unmodified, buffered version of the incoming HSYNCIN or SOGIN signal of the selected channel, with the incoming signal’s period, polarity, and width to aid in mode detection. HSYNCOUT will be the same format as the incoming sync signal: either horizontal or composite sync. If a SOG input is selected, HSYNCOUT will output the entire SOG signal, including the VSYNC portion, pre- and post-equalization pulses if present, and Macrovision pulses if present. HSYNCOUT remains active when the ISL98002 is in power-down mode. HSYNCOUT is generally used for mode detection. VSYNCOUT VSYNCOUT is an unmodified, buffered version of the incoming VSYNCIN signal of the selected channel, with the original VSYNC period, polarity, and width to aid in mode detection. If a SOG input is selected, this signal will output the VSYNC signal extracted by the ISL98002’s sync slicer. Extracted VSYNC will be the width of the embedded VSYNC pulse plus pre- and post-equalization pulses (if present). Macrovision pulses from an NTSC DVD source will lengthen the width of the VSYNC pulse. Macrovision pulses from other sources (PAL DVD or videotape) may appear as a second VSYNC pulse encompassing the width of the Macrovision. See the “Macrovision” on page 19 for more information. VSYNCOUT (including the sync separator function) remains active in power-down mode. VSYNCOUT is generally used for mode detection, start of field detection, and even/odd field detection. FN6535 Rev. 1.0 Jul 6, 2021 The HSOUT Width register (0x19) controls the width of the HSOUT pulse. The pulse width is nominally 1 pixel clock period times the value in this register. Crystal Oscillator An external 22MHz to 27MHz crystal supplies the low-jitter reference clock to the DPLL. The absolute frequency of this crystal within this range is unimportant, as is the crystal’s temperature coefficient, allowing use of less expensive, lower-grade crystals. As an alternative to a crystal, the XTALIN pin can be driven with a 3.3V CMOS-level external clock source at any frequency between 22MHz and 33.5MHz. The ISL98002’s jitter specification assumes a low-jitter crystal source. If the external clock source has increased jitter, the sample clock generated by the DPLL may exhibit increased jitter as well. EMI Considerations There are two possible sources of EMI on the ISL98002 as explained in the following:: Crystal Oscillator - The EMI from the crystal oscillator is negligible. This is due to an amplitude-regulated, low voltage sine wave oscillator circuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics. Note: The crystal oscillator is not a significant source of EMI. Digital Output Switching - This is the largest potential source of EMI. However, the EMI is determined by the PCB layout and the loading on the databus. The way to control this is to put series resistors on the output of all the digital pins (as our demo board and reference circuits show). These resistors should be as large as possible, while still meeting the setup and hold timing requirements of the scaler. We recommend starting with 22. If the databus is heavily loaded (long traces, many other part on the same bus), this value may need to be reduced. If the databus is lightly loaded, it may be increased. Renesas’ recommendations to minimize EMI are: • Minimize the databus trace length • Minimize the databus capacitive loading. If EMI is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. This can only be done as long as the scaler’s setup and hold timing requirements continue to be met. Page 23 of 28 ISL98002 Reducing Power Dissipation Communication is accomplished in three steps: It is possible to reduce the total power consumption of the ISL98002 in applications where power is a concern. There are several techniques that can be used to reduce power consumption: 1. The Host selects the ISL98002 it wishes to communicate with. • Buffering Digital Outputs. Switching data output pins into a capacitive bus can consume significant current. The higher the capacitance on the external databus, the higher the switching current. To minimize current consumption inside the ISL98002, minimize bus capacitance and/or insert data buffers such as the SN64AVC16827 between the ISL98002’s data outputs and the external databus. 3. The Host writes to or reads from the ISL98002’s Configuration Register. The ISL98002’s internal address pointer auto increments, so to read registers 0x00 through 0x1B, for example, one would write 0x00 in Step 2, then repeat Step 3 28x, with each read returning the next register value. • Internal Reference Frequency. The crystal frequency is multiplied by the value in register 0x2B to generate an internal high frequency reference clock. This internal frequency should be set to 400MHz ±10% for minimum power consumption. For example, for a 33MHz frequency at XTALIN, register 0x2B should be set to a value of 0x0C to minimize power. Standby Mode The ISL98002 can be placed into a low power standby mode by writing a 0x0F to register 0x1B, powering down the triple ADCs, the DPLL, and most of the internal clocks. To allow input monitoring and mode detection during power-down, the following blocks remain active: • Serial interface (including the crystal oscillator) to enable register read/write activity • Activity and polarity detect functions (registers 0x01 and 0x02) • The HSYNCOUT and VSYNCOUT pins (for mode detection) Initialization The ISL98002 initializes with default register settings for an AC-coupled, RGB input. Reset The ISL98002 has a Power-On Reset (POR) function that resets the chip to its default state when power is initially applied, including resetting all the registers to their default settings as described in the “Register Listing” beginning on page 10. The external RESET pin duplicates the reset function of the POR without having to cycle the power supplies. The RESET pin does not need to be used in normal operation and can be tied high. ISL98002 Serial Communication Overview The ISL98002 uses a 2-wire serial bus for communication with its host. SCL is the Serial Clock line, driven by the host, and SDA is the Serial Data line, which can be driven by all devices on the bus. SDA is open drain to allow multiple devices to share the same bus simultaneously. FN6535 Rev. 1.0 Jul 6, 2021 2. The Host writes the initial ISL98002 Configuration Register address it wishes to write to or read from. The ISL98002 has a 7-bit address on the serial bus. The upper 6-bits are permanently set to 100110, with the lower bit determined by the state of pin 29. This allows two ISL98002s to be independently controlled while sharing the same bus. The bus is nominally inactive, with SDA and SCL high. Communication begins when the host issues a START command by taking SDA low while SCL is high (see Figure 7). The ISL98002 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. The host then transmits the 7-bit serial address plus a R/W bit, indicating if the next transaction will be a Read (R/W = 1) or a Write (R/W = 0). If the address transmitted matches that of any device on the bus, that device must respond with an ACKNOWLEDGE (see Figure 8). Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. Communication with the selected device in the selected direction (read or write) is ended by a STOP command, where SDA rises while SCL is high (see Figure 7), or a second START command, which is commonly used to reverse data direction without relinquishing the bus. Data on the serial bus must be valid for the entire time SCL is high (see Figure 9). To achieve this, data being written to the ISL98002 is latched on a delayed version of the rising edge of SCL. SCL is delayed and deglitched inside the ISL98002 for three crystal clock periods (120ns for a 25MHz crystal) to eliminate spurious clock pulses that could disrupt serial communication. When the contents of the ISL98002 are being read, the SDA line is updated after the falling edge of SCL, delayed and deglitched in the same manner. Configuration Register Write Figure 10 shows two views of the steps necessary to write one or more words to the Configuration Register. Configuration Register Read Figure 11 shows two views of the steps necessary to read one or more words from the Configuration Register. Page 24 of 28 ISL98002 SCL SDA START STOP FIGURE 7. VALID START AND STOP CONDITIONS SCL FROM HOST 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER SCL SDA DATA STABLE DATA CHANGE DATA STABLE FIGURE 9. VALID DATA CHANGES ON THE SDA BUS FN6535 Rev. 1.0 Jul 6, 2021 Page 25 of 28 ISL98002 Signals the beginning of serial I/O START Command ISL98002 Serial Bus R/W 0 A This is the 7-bit address of the ISL98002 on the 2-wire bus. The address is 0x4C if pin 29 is low, 0x4D if pin 29 is high. Shift this value left to when adding the R/W bit. 0 1 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 (pin 29) ISL98002 Serial Bus Address Write ISL98002 Register Address Write This is the address of the ISL98002’s configuration register that the following byte will be written to. ISL98002 Register Data Write(s) This is the data to be written to the ISL98002’s configuration register. Note: The ISL98002’s Configuration Register’s address pointer auto increments after each data write: repeat this step to write multiple sequential bytes of data to the Configuration Register. (Repeat if desired) Signals the ending of serial I/O STOP Command Signals from the Host SDA Bus Signals from the ISL98002 S T Serial Bus A R Address T Register Address aaaaaaaa 1 0 0 1 1 0A0 A C K S T O P Data Write* * The data write step may be repeated to write to the ISL98002’s Configuration Register sequentially, beginning at the Register Address written in the previous step. dddddddd A C K A C K FIGURE 10. CONFIGURATION REGISTER WRITE FN6535 Rev. 1.0 Jul 6, 2021 Page 26 of 28 ISL98002 Signals the beginning of serial I/O START Command ISL98002 Serial Bus R/W 0 1 0 0 1 1 A7 A6 A5 A4 A3 A (pin 29) 0 ISL98002 Serial Bus Address Write This is the 7-bit address of the ISL98002 on the 2-wire bus. The address is 0x4C if pin 29 is low, 0x4D if pin 29 is high. R/W = 0, indicating next transaction will be a write. ISL98002 Register Address Write A2 A1 A0 START Command ISL98002 Serial Bus R/W A 0 1 0 0 1 1 D7 D6 D5 D4 D3 (pin 29) D2 D1 1 D0 SDA Bus Signals from the ISL98002 R E S T Serial Bus A Address R T 1 0 0 1 1 0A1 Register Address 1 0 0 1 1 0A0 aaaaaaaa A C K ISL98002 Register Data Read(s) This is the data read from the ISL98002’s configuration register. Signals the ending of serial I/O STOP Command Signals from the Host ISL98002 Serial Bus Address Write This is the 7-bit address of the ISL98002 on the 2-wire bus. The address is 0x4C if pin 29 is low, 0x4D if pin 29 is high. R/W = 1, indicating next transaction(s) will be a read. Note: The ISL98002’s Configuration Register’s address pointer auto increments after each data read: repeat this step to read multiple sequential bytes of data from the Configuration Register. (Repeat if desired) S T Serial Bus A R Address T This sets the initial address of the ISL98002’s configuration register for subsequent reading. Ends the previous transaction and starts a new one A C K Data Read* S T O AP C K * The data read step may be repeated to read from the ISL98002’s Configuration Register sequentially, beginning at the Register Address written in the previous two steps. Adddddddd C K FIGURE 11. CONFIGURATION REGISTER READ Revision Revision History REV. DATE 1.0 Jul 6, 2021 FN6535 Rev. 1.0 Jul 6, 2021 DESCRIPTION Updated links throughout. Updated Ordering Information table format, removed retired part, and updated applicable notes. Updated termination finish from Matte Sn (e3) to NiPdAu-Ag (e4). Changed POD from L72.10x10B to L72.10x10H. Added Revision History section. Page 27 of 28 ISL98002 Package Outline Drawing For the most recent package outline drawing, see L72.10x10H. L72.10x10H 72 Lead Quad Flat No-Lead Plastic Package (QFN) Rev 1, 4/20 FN6535 Rev. 1.0 Jul 6, 2021 Page 28 of 28 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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