PD - 97312
IRFR3607PbF IRFU3607PbF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G
HEXFET® Power MOSFET
D
Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
S
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
D
75V 7.34mΩ 9.0mΩ 80Ac 56A
S G
S D G
D-Pak I-Pak IRFR3607PbF IRFU3607PbF
G
D
S
Gate
Drain
Max.
80c 56c 56 310 140 0.96 ± 20 27 -55 to + 175 300
Source
Units
A
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C ID @ TC = 100°C ID @ TC = 25°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case)
W W/°C V V/ns °C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy e Avalanche Current d Repetitive Avalanche Energy g 120 46 14 mJ A mJ
Thermal Resistance
Symbol
RθJC RθJA RθJA
Parameter
Junction-to-Case k Junction-to-Ambient j Junction-to-Ambient (PCB Mount) jk
Typ.
––– ––– –––
Max.
1.045 50 110
Units
°C/W
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1
03/04/08
IRFR/U3607PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
75 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– 0.096 ––– 7.34 9.0 ––– 4.0 ––– 20 ––– 250 ––– 100 ––– -100
Conditions
V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mAd mΩ VGS = 10V, ID = 46A g V VDS = VGS, ID = 100µA µA VDS = 75V, VGS = 0V VDS = 60V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
170 ––– ––– ––– –––
–––
Conditions
VDS = 50V, ID = 46A ID = 46A VDS = 38V VGS = 10V g ID = 46A, VDS =0V, VGS = 10V
––– 56 13 16 40 0.55 16 110 43 96 3070 280 130 380 610
––– 84 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– –––
S nC
Ω
––– ––– ––– ––– ––– ––– ––– j ––– Effective Output Capacitance (Energy Related) ––– Effective Output Capacitance (Time Related)h
ns
pF
VDD = 49V ID = 46A RG = 6.8Ω VGS = 10V g VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 60V j VGS = 0V, VDS = 0V to 60V h
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) d Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
––– ––– ––– ––– 80c 310 A
Conditions
MOSFET symbol showing the integral reverse
G S D
––– ––– 1.3 V ––– 33 50 ns ––– 39 59 ––– 32 48 nC TJ = 125°C ––– 47 71 ––– 1.9 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25°C, IS = 46A, VGS = 0V g TJ = 25°C VR = 64V, TJ = 125°C IF = 46A di/dt = 100A/µs g TJ = 25°C
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 56A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.12mH RG = 25Ω, IAS = 46A, VGS =10V. Part not recommended for use above this value.
ISD ≤ 46A, di/dt ≤ 1920A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C.
2
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IRFR/U3607PbF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
100
4.5V 10
4.5V
≤60µs PULSE WIDTH
Tj = 25°C 1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) 10 0.1 1
≤60µs PULSE WIDTH
Tj = 175°C 10 100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
ID = 80A 2.5 VGS = 10V
ID, Drain-to-Source Current (A)
100
10
T J = 175°C
T J = 25°C
(Normalized)
2.0
1.5
1 VDS = 25V ≤60µs PULSE WIDTH 0.1 2 3 4 5 6 7 8
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C)
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 46A
VGS , Gate-to-Source Voltage (V)
10.0
C, Capacitance (pF)
VDS= 24V VDS= 15V
10000 Ciss Coss Crss
8.0
6.0
1000
4.0
2.0
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0.0 0 10 20 30 40 50 60 Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFR/U3607PbF
1000
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100 T J = 175°C 10 T J = 25°C 1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
1msec
100µsec
10 Tc = 25°C Tj = 175°C Single Pulse 1 1
10msec
DC
10 VDS, Drain-to-Source Voltage (V)
100
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
100 Id = 5mA 95
80 70 60
ID, Drain Current (A)
Limited By Package
90
50 40 30 20 10 0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
85
80
75
70 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
1.20
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10. Drain-to-Source Breakdown Voltage
500 450 400 350 300 250 200 150 100 50 0 ID 5.6A 11A BOTTOM 46A TOP
1.00
0.80
Energy (µJ)
0.60
0.40
0.20
0.00 -10 0 10 20 30 40 50 60 70 80
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (°C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFR/U3607PbF
10.00
Thermal Response ( Z thJC ) °C/W
1.00 D = 0.50 0.20 0.10 0.10 0.05 0.02 0.01 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 0.00 1E-006
τJ R1 R1 τJ τ1 τ2 R2 R2 R3 R3 τ3 R4 R4 τC τ τ2 τ3 τ4 τ4
Ri (°C/W)
0.01109 0.26925 0.49731 0.26766
τi (sec)
0.000003 0.000130 0.001301 0.008693
τ1
Ci= τi/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
100
Avalanche Current (A)
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse) 0.01
10
0.05 0.10
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
150 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 46A
EAR , Avalanche Energy (mJ)
125
100
75
50
25
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFR/U3607PbF
4.5
VGS(th) , Gate Threshold Voltage (V)
20 IF = 31A V R = 64V 15 TJ = 25°C TJ = 125°C
4.0 3.5
IRR (A)
3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) ID = 100µA ID = 250µA ID = 1.0mA ID = 1.0A
10
5
0 0 200 400 600 800 1000 diF /dt (A/µs)
Fig 16. Threshold Voltage vs. Temperature
20 IF = 46A V R = 64V 15 TJ = 25°C TJ = 125°C
Q RR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
560 480 400 320 240 160 80 IF = 31A V R = 64V TJ = 25°C TJ = 125°C
IRR (A)
10
5
0 0 200 400 600 800 1000 diF /dt (A/µs)
0 0 200 400 600 800 1000 diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
560 480 400
Q RR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 46A V R = 64V TJ = 25°C TJ = 125°C
320 240 160 80 0 0 200 400 600 800 1000 diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFR/U3607PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple ≤ 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01Ω
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
VDS
90%
+
VDD -
D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1%
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L VCC
0
DUT 1K
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
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Fig 23b. Gate Charge Waveform
7
IRFR/U3607PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRFR/U3607PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
@Y6HQG@) UCDTÃDTÃ6IÃDSAV ! XDUCÃ6TT@H7G` GPUÃ8P9@Ã$%&' 6TT@H7G@9ÃPIÃXXÃ (Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ6Å Ir)ÃÅQÅÃvÃhriyÃyvrÃvv vqvphrÃGrhqA
rrÅ DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRFR/U3607PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
10
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 03/08
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