KK74ACT240

TECHNICAL DATA KK74ACT240 Octal 3-State Inverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS The KK74ACT240 is identical in pinout to the LS/ALS240, HC/HCT240. The KK74ACT240 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal inverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other busoriented systems. The device has inverting outputs and two active-low output enables. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA; 0.1 µA @ 25°C • Outputs Source/Sink 24 mA ORDERING INFORMATION KK74ACT240N Plastic KK74ACT240DW SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Enable A, Enable B L L PIN 20=VCC PIN 10 = GND H A,B L H X Outputs YA,YB H L Z X = don’t care Z = high impedance 1 KK74ACT240 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 4.5 0 -40 Max 5.5 VCC 140 +85 -24 24 Unit V V °C °C mA mA ns/V VCC =4.5 V VCC =5.5 V 0 0 10 8.0 VIN from 0.8 V to 2.0 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74ACT240 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH VIL VOH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V VOUT= VCC-0.1 V IOUT ≤ -50 µA VIN= VIL IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT ≤ 50 µA * * Guaranteed Limits 2 5 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.5 -40°C to 8 5 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±5.0 µA µA V Unit V V V V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 5.5 VIN=VIH IOL=24 mA IOL=24 mA VIN=VCC or GND IIN IOZ Maximum Input Leakage Current Maximum ThreeState Leakage Current Additional Max ICC/Input +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN (OE)=VIL, VIH VIN=VCC, GND VOUT=VCC, GND VIN=VCC - 2.1 V VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND ∆ICCT IOLD IOHD ICC 5.5 5.5 5.5 5.5 8.0 1.5 75 -75 80 mA mA mA µA * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. 3 KK74ACT240 AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 2 5 °C Min tPLH tPHL tPZH tPZL tPHZ tPLZ CIN Propagation Delay, A to YA or B to YB (Figure 1) Propagation Delay, A to YA or B to YB (Figure 1) Propagation Delay, Output Enable to YA or YB (Figure 2) Propagation Delay, Output Enable to YA or YB (Figure 2) Propagation Delay, Output Enable to YA or YB (Figure 2) Propagation Delay, Output Enable to YA or YB (Figure 2) Maximum Input Capacitance 1.5 1.5 1.5 2.0 2.0 2.5 4.5 Max 8.5 7.5 8.5 9.5 9.5 10.0 -40°C to 8 5 °C Min 1.5 1.5 1.0 1.5 2.0 2.0 4.5 Max 9.5 8.5 9.5 10.5 10.5 10.5 ns ns ns ns ns ns pF Unit Typical @25°C,VCC=5.0 V CPD Power Dissipation Capacitance 45 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms 4 KK74ACT240 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 5