KK74HC323A

TECHNICAL DATA KK74HC323A 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS The KK74HC323A is identical in pinout to the LS/ALS323. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The KK74HC323A features a multiplexed parallel input/output data port to active full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both ModeSelect lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74HC323AN Plastic KK74HC323ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND 1 KK74HC323A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. 2 KK74HC323A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 2 5 °C to -55°C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.26 ±0.1 ±0.5 ≤85 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 0.33 ±1.0 ±5.0 ≤125 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 0.4 ±1.0 ±10 µA µA V Unit VIH Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 6.0 mA (P/Q) ⎢IOUT⎢ ≤ 7.8 mA (P/Q) VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA (Q’) ⎢IOUT⎢ ≤ 5.2 mA (Q’) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum LowLevel Output Voltage VIN= VIL or VIH ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 6.0 mA (P/Q) ⎢IOUT⎢ ≤ 7.8 mA (P/Q) VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA (Q’) ⎢IOUT⎢ ≤ 5.2 mA (Q’) IIN IOZ Maximum Input Leakage Current Maximum ThreeState Leakage Current (QA thru QH) Maximum Quiescent Supply Current (per Package) VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0µA ICC 6.0 8.0 80 160 µA 3 KK74HC323A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter V Guaranteed Limit 2 5 °C to -55°C 5.0 25 29 170 34 29 160 32 27 150 30 26 150 30 26 60 12 10 75 15 13 10 15 ≤85 °C 4.0 20 24 215 43 37 200 40 34 190 38 33 190 38 33 75 15 13 95 19 16 10 15 ≤125 °C 3.4 17 20 255 51 43 240 48 41 225 45 38 225 45 38 90 18 15 110 22 19 10 15 Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 5) Maximum Propagation Delay, Clock to QA’ or QH’ (Figures 1 and 5) Maximum Propagation Delay, Clock to QA or QH (Figures 1 and 5) Maximum Propagation Delay , OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) Maximum Propagation Delay , OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) Maximum Output Transition Time, QA thru QH (Figures 1 and 5) Maximum Output Transition Time, QA’ or QH’ (Figures 1 and 5) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State), QA thru QH Power Dissipation Capacitance (Per Package), Outputs Enable 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - MHz tPLH, tPHL ns tPLH, tPHL ns tPLZ, tPHZ ns tPZL, tPZH ns tTLH, tTHL ns tTLH, tTHL ns CIN COUT pF pF Typical @25°C,VCC=5.0 V 240 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 4 KK74HC323A TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol tsu Parameter Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock (Figure 4) Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) Minimum Hold Time, Clock to Data Inputs, SA, SH, PA thru PH (Figure 4) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 100 20 17 100 20 17 120 24 20 5 5 5 80 16 14 80 16 14 1000 500 400 Guaranteed Limit 25 °C to-55°C ≤85°C 125 25 21 125 25 21 150 30 26 5 5 5 100 20 17 100 20 17 1000 500 400 ≤125°C 150 30 26 150 30 26 180 36 31 5 5 5 120 24 20 120 24 20 1000 500 400 Unit ns tsu ns th ns th ns tw ns tw ns tr, tf ns 5 KK74HC323A FUNCTION TABLE Inputs Mode Reset Mode Select S2 Reset L L L Shift Right H H H Shift Left H H H Parallel Load Hold H H H H X L H L L L H H H H L L L S1 L X H H H H L L L H L L L Output Enables OE1 L L X H X L H X L X H X L OE2 L L X X H L X H L X X H L X X X X Clock Serial Inputs DA D H X X X D D D X X X X X X X X X X X X X D D D X X X X L L L L L L L L L L L L L L L L L L L D D D QB QB QB PA PA PA PA L L L QG QG QG D D D PH PH PH PH Response PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’ QA QB QC QD QE QF QG QH QA through QH=Z Shift Right: QA through QH=Z; F A; F A FB; etc DA Shift Right: QA through QH=Z; FA; FA FB; etc DA Shift Right: DA FA =QA; FB =QB; etc FA Shift Left: QA through QH=Z; FH; FH FG; etc DH Shift Left: QA through QH=Z; F H; F H FG; etc DH Shift Left: DH FH =QH; FG =QG; etc FH Parallel Load:PN FN Hold: QA through QH=Z; FN=FN Hold: QA through QH=Z; FN=FN Hold: QN =QH Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. 6 KK74HC323A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3a. Switching Waveforms Figure 3b. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Test Circuit Figure 6. Test Circuit 7 KK74HC323A N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 8