KK74LV573N

TECHNICAL DATA Octal D-type transparent latch (3-State) The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT573. The 74LV573 is an octal D-type transparent latch featuring separate Dtype inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The ‘573’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the D n inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFFstate. Operation of the OE input does not affect the state of the latches. The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the ‘563’ has inverted outputs and the ‘373’ has a different pin arrangement. KK74LV573 N SUFFIX PLASTIC DIP 20 1 20 1 DW SUFFIX SO ORDERING INFORMATION KK74LV573N Plastic DIP KK74LV573DW SOIC TA = -40° to 125° C for all packages • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.0 to 5.5 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • High Noise Immunity Characteristic of CMOS Devices PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Output Enable L L Output D H L Clock Q H L no change Z PIN 20=VCC PIN 10 = GND L H L,H, X X X H= high level L = low level X = don’t care Z = high impedance 1 KK74LV573 MAXIMUM RATINGS* Symbol VCC IIK * IO * ICC IGND PD 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP *4 SO * 4 Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds Value -0.5 to +7.0 ±20 ±50 ±35 ±70 ±50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * 3 Tstg TL * °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 0 V ≤ VCC ≤ 2.0 V 2.0 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V 3.6 V ≤ VCC ≤ 5.5 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV573 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol VIH Parameter HIGH level input voltage conditions VCC V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 25°C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 ±0.1 8.0 0.2 min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 Guaranteed Limit -40°C max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 ±0.1 8.0 0.2 min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 85°C max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 ±1.0 80 0.5 125°C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 ±1.0 160 0.85 V Unit VIL LOW level output voltage V VOH HIGH level VI = VIH or VIL output IO = -100 µА voltage V VI = VIH or VIL IO = -8 mА VI = VIH or VIL IO = -16 mА VOL LOW level output voltage VI = VIH or VIL IO = 100 µА V V V VI = VIH or VIL IO = 8 mА VI = VIH or VIL IO = 16 mА II ICC ICC1 Input current Supply current Additional supply current per input Three state leakage current VI = VCC or 0 V VI =VCC or 0 V IO = 0 µ А VI = VCC – 0.6V V V µА µА mA IOZ 3-state output VI (11) = VIH VO =VCC or 0 V 5.5 - ±0.5 - ±0.5 - ±5 - ±10 µА 3 KK74LV573 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=2.5 ns) Test Symbol Parameter conditions V I = 0 V or V 1 Figures 1,3 VCC V 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 VI = 0 V or VCC 5.5 min tPHL, tPLH Propagation delay , Clock to Q max 150 30 23 18 15 160 34 28 20 17 160 31 23 20 17 140 28 22 17 14 7.0* 52* Guaranteed Limit -40°C to 25°C 85°C min max 160 39 29 23 19 180 43 31 25 21 160 39 29 24 20 160 37 28 22 18 125°C min max 170 49 36 29 24 190 53 34 31 26 170 48 36 29 24 170 48 35 28 23 ns Unit tPHL, tPLH Propagation delay , LE to Q V I = 0 V or V 1 Figures 1,3 ns tPHZ, tPLZ Propagation delay, OE to Q V I = 0 V or V 1 Figures 2,4 ns tPZH, tPZL Propagation delay, OE to Q V I = 0 V or V 1 Figures 2,4 ns CI CPD Input capacitance Power dissipation capacitance (per latch) pF pF * T = 25oC 4 KK74LV573 TIMING REQUIREMENTS (CL=50 pF, tr=tf=2.5 ns) Test Symbol tw Parameter Pulse Width, LE (low or high) conditions V I = 0 V or V 1 Figures 1,3 VCC V 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 min 100 29 21 17 15 50 15 11 8 6 40 8 8 8 8 max Guaranteed Limit -40°C to 25°C 125 34 25 20 18 75 17 13 10 8 40 8 8 8 8 85°C min max 125°C min 150 41 30 24 21 100 20 15 12 10 40 8 8 8 8 max ns ns ns Unit tsu Setup Time, Data to LE V I = 0 V or V 1 Figures 1,5 th Hold Time, LE to Data V I = 0 V or V 1 Figures 1,5 TEST POINT DEVICE UNDER TEST TEST POINT 1k CL * OUTPUT CL * DEVICE UNDER TEST OUTPUT Co nnect to V CC when testing tPLZ and tPZL Co nnect to GND when testing tPHZ and tPZH * Includes all probe and jig capacitance Figure 1. Test Circuit * Includes all probe and jig capacitance Figure 2. Test Circuit Figure 3. Switching Waveforms 5 KK74LV573 Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Switching Waveforms 6 KK74LV573 Temperature, °C Symbol VCC, V -40°C to 25 V 1.2 2.0 2.7 2.7 4.5 0.6 1.0 1.5 1.5 2.25 0.32 0.4 0.55 0.6 0.85 0.88 1.5 2.1 2.3 3.45 85 Level of a signal V 1.2 2.0 2.7 2.7 4.5 0.6 1.0 1.5 1.5 2.25 0.37 0.45 0.6 0.65 0.90 0.78 1.4 2.0 2.2 3.35 125 V 1.2 2.0 2.7 2.7 4.5 0.6 1.0 1.5 1.5 2.25 0.37 0.45 0.65 0.7 1.0 0.68 1.3 1.9 2.1 3.25 V1 VM VX VY 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 EXPANDED LOGIC DIAGRAM 7 KK74LV573 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 8