LTC1149
LTC1149-3.3/LTC1149-5
High Efficiency Synchronous
Step-Down Switching Regulators
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DESCRIPTIO
FEATURES
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The LTC ®1149 series is a family of synchronous stepdown switching regulator controllers featuring automatic
Burst ModeTM operation to maintain high efficiencies at
low output currents. These devices drive external complementary power MOSFETs at switching frequencies up
to 250kHz using a constant off-time current-mode architecture.
Operation to 48V Input Voltage
Ultrahigh Efficiency: Up to 95%
Current Mode Operation for Excellent Line and
Load Transient Response
High Efficiency Maintained over Wide Current Range
Logic-Controlled Micropower Shutdown
Short-Circuit Protection
Very Low Dropout Operation: 100% Duty Cycle
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
Available in 16-Pin Narrow SO Package
Special onboard regulation and level-shift circuitry allow
operation at input voltages from dropout to 48V (60V
absolute max). The constant off-time architecture maintains constant ripple current in the inductor, easing the
design of wide input range converters. Current mode
operation provides excellent line and load transient
response. The operating current level is user-programmable via an external current sense resistor.
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APPLICATI
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Notebook and Palmtop Computers
Portable Instruments
Battery-Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies
The LTC1149 series incorporates automatic power saving
Burst Mode operation when load currents drop below the
level required for continuous operation. Standby power is
reduced to only about 8mW at VIN = 12V. In shutdown,
both MOSFETs are turned off.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATI
VIN
CAP
VCC
+
3.3µF
P-CHANNEL
IRFR9024
PGATE
0.068µF
PDRIVE
VCC
+
1N4148
VIN
0.047µF
D1
1N5819
SHDN1
SENSE +
SHDN2
SENSE –
ITH
3300µF
1k
CT
CT
470pF
SGND
NGATE
100
FIGURE 1 CIRCUIT
VIN = 12V
90
L*
62µH
RSENSE**
0.05Ω
LTC1149-5
0V = NORMAL
>2V = SHUTDOWN
LTC1149-5 Efficiency
CIN
100µF
100V
VOUT
5V/2A
1000pF
N-CHANNEL
IRFR024
+
EFFICIENCY (%)
1N4148
VIN = 24V
80
70
COUT
220µF
P, RGNDS
*COILTRONICS CTX62-2-MP
**KRL SL-1-C1-0R050J
60
0.02
1149 F01
0.2
LOAD CURRENT (A)
2
1149 TA01
Figure 1. High Efficiency Step-Down Regulator
1
LTC1149
LTC1149-3.3/LTC1149-5
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Input Supply Voltage (Pin 2)...................... – 15V to 60V
VCC Output Current (Pin 3) .................................. 50mA
VCC Input Voltage (Pin 5)........................................ 16V
Continuous Output Current (Pins 4, 13) .............. 50mA
Sense Voltages (Pins 8, 9)
VIN ≥ 12.7V .......................................... 13V to – 0.3V
VIN < 12.7V ............................. (VCC + 0.3V) to – 0.3V
Shutdown Voltages (Pins 10, 15) ............................. 7V
Operating Temperature Range .................... 0°C to 70°C
Extended Commercial
Temperature Range ............................... – 40°C to 85°C
Junction Temperature (Note 1) ............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ELECTRICAL CHARACTERISTICS
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RATI GS
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
TOP VIEW
PGATE
1
16 CAP
VIN
2
15 SHDN2
VCC
3
14 RGND
PDRIVE
4
13 NGATE
VCC
5
12 PGND
CT
6
ITH
7
SENSE –
8
11 SGND
VFB /
10 SHDN1*
9 SENSE +
N PACKAGE
16-LEAD PDIP
ORDER PART
NUMBER
LTC1149CN
LTC1149CN-3.3
LTC1149CN-5
LTC1149CS
LTC1149CS-3.3
LTC1149CS-5
S PACKAGE
16-LEAD PLASTIC SO
*FIXED OUTPUT VERSIONS
TJMAX = 125°C, θJA = 70°C/ W (N)
TJMAX = 125°C, θJA = 110°C/ W (S)
Consult factory for Industrial and Military grade parts.
TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V10
Feedback Voltage (LTC1149 Only)
VIN = 9V
I10
Feedback Current (LTC1149 Only)
VOUT
Regulated Output Voltage
LTC1149-3.3
LTC1149-5
VIN = 9V
ILOAD = 700mA
ILOAD = 700mA
Output Voltage Line Regulation
VIN = 9V to 48V, ILOAD = 50mA
Output Voltage Load Regulation
LTC1149-3.3
LTC1149-5
5mA < ILOAD < 2A
5mA < ILOAD < 2A
Burst Mode Output Ripple
ILOAD = 0A
50
VIN = 12V
VIN = 48V
2.0
2.2
2.8
3.0
mA
mA
Burst Mode
VIN = 12V
VIN = 48V
0.6
0.8
0.9
1.1
mA
mA
Shutdown
VIN = 12V, V15 = 2V
VIN = 48V, V15 = 2V
135
300
170
390
µA
µA
10.25
11
V
200
250
mV
∆VOUT
I2
Input DC Supply Current (Note 3)
Normal Mode
MIN
TYP
MAX
UNITS
1.21
1.25
1.29
V
0.2
1
µA
3.23
4.9
3.33
5.05
3.43
5.2
V
V
– 40
0
40
mV
40
60
65
100
mV
mV
●
VCC
Internal Regulator Voltage
(Sets MOSFET Gate Drive Levels)
VIN = 12V to 48V
I3 = 20mA
V2 – V3
VCC Dropout Voltage
VIN = 5V, I3 = 10mA
VIN – V1
P-Gate to Source Voltage (Off)
VIN = 12V
VIN = 48V
2
●
●
●
●
●
●
●
●
9.75
– 0.2
– 0.2
0
0
mVP-P
V
V
LTC1149
LTC1149-3.3/LTC1149-5
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
V 9 – V8
Current Sense Threshold Voltage
LTC1149
LTC1149-3.3
LTC1149-5
V10
TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
V8 = 5V, V10 = 1.32V (Forced)
V8 = VOUT – 100mV
●
130
25
150
170
mV
mV
V8 = 3.5V (Forced)
V8 = VOUT – 100mV
●
130
25
150
170
mV
mV
V8 = 5.3V (Forced)
V8 = VOUT – 100mV
●
130
25
150
170
mV
mV
0.5
0.8
2
0.8
1.4
2
V
18
25
µA
Shutdown 1 Threshold
LTC1149-3.3, LTC1149-5
V
V15
Shutdown 2 Threshold
I15
Shutdown 2 Input Current
V15 = 5V
I6
CT Pin Discharge Current
VOUT In Regulation, VSENSE– = VOUT
VOUT = 0V
50
70
2
90
10
µA
µA
tOFF
Off-Time (Note 4)
CT = 390pF, ILOAD = 700mA
4
5
6
µs
tr, tf
Driver Output Transition Times
CL = 3000pF (Pins 4, 13), VIN = 6V
100
200
ns
MIN
TYP
MAX
UNITS
1.2
1.25
1.3
V
3.17
4.85
3.33
5.05
3.43
5.2
V
V
VIN = 12V
VIN = 48V
2.0
2.2
3.2
3.5
mA
mA
Burst Mode
VIN = 12V
VIN = 48V
0.6
0.8
1.05
1.30
mA
mA
Shutdown
VIN = 12V, V15 = 2V
VIN = 48V, V15 = 2V
135
300
230
520
µA
µA
9.75
10.25
11
V
125
25
150
175
mV
mV
0.8
1.4
2
V
3.8
5
6
µs
– 40°C ≤ TA ≤ 85°C (Note 5), unless otherwise noted.
SYMBOL
PARAMETER
V10
Feedback Voltage LTC1149 Only
VOUT
Regulated Output Voltage
LTC1149-3.3
LTC1149-5
I2
Input DC Supply Current (Note 3)
Normal Mode
CONDITIONS
VIN = 9V
ILOAD = 700mA
ILOAD = 700mA
VCC
Internal Regulator Voltage
(Sets MOSFET Gate Drive Levels)
VIN = 12V to 48V
I3 = 20mA
V9 – V 8
Current Sense Threshold Voltage
Low Threshold (Forced)
High Threshold (Forced)
V15
Shutdown 2 Threshold
tOFF
Off-Time (Note 4)
CT = 390pF, ILOAD = 700mA, VIN = 10V
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC1149CN, LTC1149CN-3.3, LTC1149CN-5: TJ = TA + (PD )(70°C/W)
LTC1149CS, LTC1149CS-3.3, LTC1149CS-5: TJ = TA + (PD)(110°C/W)
Note 2: Pin 10 is a shutdown pin on the LTC1149-3.3 and LTC1149-5
fixed output voltage versions and must be at ground potential for testing.
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. The allowable operating frequency
may be limited by power dissipation at high input voltages. See Typical
Performance Characteristics and Applications Information.
Note 4: In applications where RSENSE is placed at ground potential, the offtime increases approximately 40%.
Note 5: The LTC1149, LTC1149-3.3, and LTC1149-5 are not tested and
not quality assurance sampled at – 40°C and 85°C. These specifications
are guaranteed by design and/or correlation.
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LTC1149
LTC1149-3.3/LTC1149-5
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TYPICAL PERFOR A CE CHARACTERISTICS
Line Regulation
Efficiency vs Input Voltage
100
Load Regulation
20
60
FIGURE 1 CIRCUIT
ILOAD = 1A
FIGURE 1 CIRCUIT
ILOAD = 1A
40
FIGURE 1 CIRCUIT
VIN = 24V
0
–20
90
∆VOUT (mV)
20
∆VOUT (mV)
EFFICIENCY (%)
95
0
–40
–20
–60
–40
–80
85
80
0
10
30
20
INPUT VOLTAGE (V)
40
–100
–60
50
0
10
20
30
INPUT VOLTAGE (V)
1149 G01
0
50
40
0.5
1149 G03
1149 G02
DC Supply Current
Operating Frequency
vs (VIN – VOUT)
Supply Current in Shutdown
3.0
400
2.0
VSD2 = 2V
VOUT = 5V
2.5
ACTIVE MODE
2.0
1.5
1.0
SLEEP MODE
NORMALIZED FREQUENCY
T = 0°C
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
2.5
1.0
1.5
2.0
LOAD CURRENT (A)
300
200
100
1.5
T = 25°C
T = 70°C
1.0
0.5
0.5
0
0
10
20
30
INPUT VOLTAGE (V)
0
50
40
0
10
30
20
INPUT VOLTAGE (V)
40
1149 G04
Gate Charge Supply Current
15
10
70
140
60
120
50
40
30
LTC1149-5
10
100
150
200
OPERATING FREQUENCY (kHz)
250
1149 G07
0
0
1
25
3
4
2
OUTPUT VOLTAGE (V)
MAXIMUM
THRESHOLD
100
80
60
40
MINIMUM
THRESHOLD
20
LTC1149-3.3
0
4
160
20
QP + QN = 50nC
5
15
20
10
(VIN – VOUT) VOLTAGE (V)
Current Sense Threshold Voltage
80
SENSE VOLTAGE (mV)
OFF-TIME (µs)
GATE CHARGE CURRENT (mA)
25
QP + QN = 100nC
5
1149 G06
Off-Time vs VOUT
20
0
1149 G05
30
50
0
50
0
5
1149 G08
0
20
60
40
TEMPERATURE (°C)
80
100
1149 G09
LTC1149
LTC1149-3.3/LTC1149-5
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PI FU CTIO S
PGATE (Pin 1): Level-Shifted Gate Drive Signal for Top
P-Channel MOSFET. The voltage swing at Pin 1 is from VIN
to VIN – VCC.
VIN (Pin 2): Main Supply Input Pin.
VCC (Pin 3): Output Pin of Low Dropout 10V Regulator. Pin
3 is not protected against DC short circuits.
PDRIVE (Pin 4): High Current Gate Drive for Top
P-Channel MOSFET. The voltage swing at Pin 4 is from VCC
to ground.
VCC (Pin 5): Regulated 10V Input for Driver and Control
Supplies. Must be closely decoupled to power ground.
CT (Pin 6): External capacitor CT from Pin 6 to ground sets
the operating frequency. (The frequency is also dependent
on the ratio VOUT/VIN.)
ITH (Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage.
SENSE – (Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1149-3.3 and
LTC1149-5 versions. Pin 8 is also the (–) input for the
current comparator.
SENSE+ (Pin 9): The (+) Input for the Current Comparator.
A built-in offset between Pins 8 and 9 in conjunction with
RSENSE sets the current trip threshold.
OPERATIO
SHDN1/VFB (Pin 10): In fixed output voltage versions, Pin
10 serves as a shutdown pin for the control circuitry only
(VCC is not affected). Taking Pin 10 of the LTC1149-3.3 or
LTC1149-5 high holds both MOSFETs off. Must be at
ground potential for normal operation.
For the LTC1149 adjustable version, Pin 10 serves as the
feedback pin from an external resistive divider used to set
the output voltage.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of COUT.
PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of CIN.
NGATE (Pin 13): High Current Drive for Bottom
N-channel MOSFET. The voltage swing at Pin 13 is from
ground to VCC.
RGND (Pin 14): Low Dropout Regulator Ground. Connects to power ground.
SHDN2 (Pin 15): Master Shutdown Pin. Taking Pin 15
high shuts down VCC and all control circuitry; requires a
logic signal with tr, tf < 1µs.
CAP (Pin 16): Charge Compensation Pin. A capacitor from
Pin 16 to VCC provides the charge required by the P-drive
level-shift capacitor during supply transitions. The Pin 16
capacitor must be larger than the Pin 4 capacitor.
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(Refer to Functional Diagram)
The LTC1149 series uses a current mode, constant offtime architecture to synchronously switch an external pair
of complementary power MOSFETs. Operating frequency
is set by an external capacitor at the timing capacitor,
Pin 6.
The output voltage is sensed either by an internal voltage
divider connected to SENSE–, Pin 8 (LTC1149-3.3 and
LTC1149-5) or an external divider returned to VFB Pin 10
(LTC1149). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference
voltage of 1.25V. To optimize efficiency, the LTC1149
series automatically switches between two modes of
operation, burst and continuous. The voltage comparator
is the primary control element for Burst Mode operation,
while the gain block controls the output voltage in continuous mode.
A low dropout 10V regulator provides the operating voltage VCC for the MOSFET drivers and control circuitry. The
driver outputs at Pins 4 and 13 are referenced to ground,
which fulfills the N-channel MOSFET gate drive requirement. The P-channel gate drive at Pin 1 must be referenced to the main supply input VIN, which is accomplished
by level-shifting the Pin 4 signal via an internal 500k
resistor and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the PGATE output is switched to VIN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 6 is now allowed to discharge at a rate
determined by the off-time controller. The discharge
5
LTC1149
LTC1149-3.3/LTC1149-5
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OPERATIO (Refer to Functional Diagram)
current is made proportional to the output voltage (measured by Pin 8) to model the inductor current, which
decays at a rate which is also proportional to the output
voltage. While the timing capacitor is discharging, the
NGATE output is high, turning on the N-channel MOSFET.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the NGATE output to go low (turning off the
N-channel MOSFET) and the PGATE output to also go low
(turning the P-channel MOSFET back on). The cycle then
repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET
is held off by comparator V and the timing capacitor
continues to discharge below VTH1. When the timing
capacitor discharges past VTH2, voltage comparator S
trips, causing the internal SLEEP line to go low and the
N-channel MOSFET to turn off.
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FU CTIO AL DIAGRA
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, much of the circuitry
is turned off, dropping the supply current from several
milliamperes (with the MOSFETs switching) to 600µA.
When the output capacitor has discharged by the amount
of hysteresis in comparator V, the P-channel MOSFET is
again turned on and this process repeats. To avoid the
operation of the current loop interfering with Burst Mode
operation, a built-in offset is incorporated in the gain
stage. This prevents the current comparator threshold
from increasing until the output voltage has dropped
below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the N-gate
output can go high, the P-drive output must also be high.
Likewise, the P-drive output is prevented from going low
when the N-gate output is high.
Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the offtime controller increases the discharge current as VIN
drops below VOUT + 1.5V. In dropout the P-channel
MOSFET is turned on continuously.
Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149.
VIN
2
1 PGATE
CAP
16
LOW
DROPOUT
10V
REGULATOR
SHDN2
15
VCC
5 VCC
500k
4 PDRIVE
500k
3
13 NGATE
14 RGND
9 SENSE +
12 PGND
8 SENSE –
–
V
+
R
Q
–
S
C
+
+
25mV TO 150mV
+
VTH1
–
VOS
T
13k
–
SLEEP
G
–
1.25V
VTH2
6
CT
6
100k
+
S
OFF-TIME
CONTROL
VIN
SENSE –
7
ITH
11
SGND
REFERENCE
10
SHDN1
(VFB)
1149 FD
LTC1149
LTC1149-3.3/LTC1149-5
TEST CIRCUIT
+
0.1µF
+
IRF9Z34
VIN
0.068µF
220µF
100V
MBR380
1
2
0.047µF
3
4
+
1µF
5
6
7
390pF
3300pF
8
+
1k
PGATE
CAP
VIN
SHDN2
VCC
RGND
PDRIVE
NGATE
LTC1149
VCC
PGND
CT
SGND
ITH
SENSE –
16
+
IRFZ34
V15
15
14
13
50µH
12
11
+
VFB / 10
SHDN1
9
SENSE +
V10
25k
+
V8
V9 – V8
75k
+
220µF
0.05Ω
1000pF
VOUT
1149 TC
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APPLICATIO S I FOR ATIO
Typical Application Circuit
The basic LTC1149 series application circuit is shown in
Figure 1. External component selection is driven by the
input voltage and output load requirement, and begins
with the selection of RSENSE. Once RSENSE is known, CT
and L can be chosen. Next, the power MOSFETs and D1
are selected. Finally, CIN and COUT are selected and the
loop is compensated. The circuit shown in Figure 1 can be
configured for operation up to an input voltage of 48V. If
the application does not require greater than 15V operation, then the LTC1148 should be used.
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current.
The LTC1149 series current comparator has a threshold
range which extends from a minimum of 25mV/RSENSE to
a maximum of 150mV/RSENSE. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode operation, IRIPPLE(P-P) must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing a
margin for variations in the LTC1149 series and external
component values yields:
RSENSE = 100mV
IMAX
A graph for selecting RSENSE versus maximum output
current is given in Figure 2. The LTC1149 series works well
with values of RSENSE from 0.02Ω to 0.2Ω.
The load current below which Burst Mode operation
commences, IBURST, and the peak short-circuit current,
ISC(PK), both track IMAX. Once RSENSE has been chosen,
IBURST and ISC(PK) can be predicted from the following
equations:
IBURST ≈ 15mV
RSENSE
ISC(PK) = 150mV
RSENSE
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LTC1149
LTC1149-3.3/LTC1149-5
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APPLICATIO S I FOR ATIO
The LTC1149 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
ISC(AVG) to be reduced to approximately IMAX.
0.18
0.14
1–
VOUT
VIN
)
where:
0.12
0.10
) )
VREG
VOUT
Note that as VIN decreases, the frequency decreases.
When the input to output voltage differential drops below
1.5V, the LTC1149 series reduces tOFF by increasing the
discharge current in CT. This prevents audible operation
prior to dropout.
0.08
0.06
0.04
0.02
0
1
3
4
2
MAXIMUM OUTPUT CURRENT (A)
5
1149 F02
Figure 2. RSENSE vs Maximum Output Current
L and CT Selection for Operating Frequency
The LTC1149 series uses a constant off-time architecture
with tOFF determined by an external timing capacitor CT.
Each time the P-channel MOSFET switch turns on, the
voltage on CT is reset to approximately 3.3V. During the
off-time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the
current in inductor L, which likewise decays at a rate
proportional to VOUT. Thus the inductor value must track
the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency, f:
)
–5
V
CT = (7.8)(10 ) 1 – OUT
VIN
f
)
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency is given by:
Once the frequency has been set by CT, the inductor L must
be chosen to provide no more than 25mV/RSENSE of peakto-peak inductor ripple current. This results in a minimum
required inductor value of:
LMIN =( 5.1)(105)(RSENSE)(CT)(VREG)
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor are
eased at the expense of efficiency. If too small an inductor
is used, the inductor current will decrease past zero and
change polarity. A consequence of this is that the LTC1149
series may not enter Burst Mode operation and efficiency
will be severely degraded at low currents.
1400
VOUT = 5V
1200
CT CAPACITANCE (pF)
RSENSE (Ω)
tOFF
)
VREG is the desired output voltage (i.e., 5V, 3.3V), while
VOUT is the actual output voltage. Thus VREG/VOUT = 1
when in regulation.
0.16
8
1
tOFF = (1.3)(104)(CT)
0.20
0
f=
1000
800
VIN = 48V
600
VIN = 24V
400
200
VIN = 12V
0
0
50
150
100
FREQUENCY (kHz)
200
250
1149 F03
Figure 3. Timing Capacitor Selection
LTC1149
LTC1149-3.3/LTC1149-5
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Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ® cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode operation to be falsely
triggered in the LTC1149 series. Do not allow the core to
saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, new surface mount designs available
from Coiltronics do not increase the height significantly.
P-Channel MOSFET Selection
Two external power MOSFETs must be selected for use
with the LTC1149 series: a P-channel MOSFET for the
main switch, and an N-channel MOSFET for the synchronous switch.
The minimum input voltage determines whether standard
threshold or logic-level threshold MOSFETs must be used.
For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V)
may be used. If VIN is expected to drop below 8V, logiclevel threshold MOSFETs (VGS(TH) < 2.5V) are strongly
recommended. When logic-level MOSFETs are used, the
absolute maximum VGS rating for the MOSFETs must be
greater than the LTC1149 series internal regulator
voltage VCC.
Selection criteria for the P-channel MOSFET include the
on-resistance RDS(ON), reverse transfer capacitance CRSS,
input voltage and maximum output current. When the
LTC1149 is operating in continuous mode, the duty cycle
for the P-channel MOSFET is given by:
V
P-Ch Duty Cycle = OUT
VIN
The P-channel MOSFET dissipation at maximum output
current is given by:
V
P-Ch PD = OUT (IMAX)2(1 + ∂P) RDS(ON)
VIN
+ K(VIN)2(IMAX)(CRSS)(f)
where ∂ is the temperature dependency of RDS(ON) and K
is a constant related to the gate drive current. Note the two
distinct terms in the equation. The first gives the I2R
losses, which are highest at low input voltages, while the
second gives the transition losses, which are highest at
high input voltages. For VIN < 24V, the high current
efficiency generally improves with larger MOSFETs
(although gate charge losses begin eating into the gains.
See Efficiency Considerations). For VIN > 24V, the transition losses rapidly increase to the point that the use of a
higher RDS(ON) device with lower CRSS actually provides
higher efficiency. This is illustrated in the Design Example
section.
The term (1 + ∂) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
∂ = 0.007/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the MOSFET
electrical characteristics. The constant K is much harder to
pin down, but K = 5 can be used for the LTC1149 series to
estimate the relative contributions of the two terms in the
P-channel dissipation equation.
N-Channel MOSFET and D1 Selection
The same input voltage constraints apply to the N-channel
MOSFET as to the P-channel with regard to when logiclevel devices are required. However, the dissipation calculation is quite different. The duty cycle and dissipation for
Kool Mµ is a registered trademark of Magnetics, Inc.
9
LTC1149
LTC1149-3.3/LTC1149-5
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the N-channel MOSFET operating in continuous mode are
given by:
V –V
N-Ch Duty Cycle = IN OUT
VIN
V –V
N-Ch PD = IN OUT (IMAX)2 (1 + ∂N)RDS(ON)
VIN
where ∂ is the temperature dependency of RDS(ON). Note
that there is no transition loss term in the N-channel
dissipation equation because the drain-to-source voltage
is always low when the N-channel MOSFET is turning on
or off. The remaining I2R losses are the greatest at high
input voltage or during a short circuit, when the N-channel
duty cycle is nearly 100%. Fortunately, low RDS(ON)
N-channel MOSFETs are readily available which reduce
losses to the point that heat sinking is not required, even
during continuous short-circuit operation.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
power MOSFETs. D1’s sole purpose in life is to prevent the
body diode of the N-channel MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
conducting IMAX.
Finally, both MOSFETs and D1 must be selected for
breakdown voltages higher than the maximum VIN.
CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
IMAX [VOUT (VIN – VOUT)]1/2
CIN Required IRMS ≈
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IMAX/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
10
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. An additional 0.1µF ceramic capacitor may also be
required on VIN for high frequency decoupling.
The selection of COUT is driven by the required effective
series resistance (ESR). The ESR of COUT must be less
than twice the value of RSENSE for proper operation of the
LTC1149 series:
COUT Required ESR < 2RSENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon, Chemicon and Sprague
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR for its size, at a somewhat
higher price. Once the ESR requirement for COUT has been
met, the RMS current rating generally far exceeds the
IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR, or RMS
current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. For example,
if 200µF/10V is called for in an application requiring 3mm
height, two AVX 100µF/10V (P/N TPSD 107K010) could be
used. Consult the manufacturer for other specific recommendations.
At low supply voltages, a minimum value of COUT is
suggested to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is too small, the
LTC1149
LTC1149-3.3/LTC1149-5
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output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes the Burst Mode
operation to be activated when the LTC1149 series would
normally be in continuous operation. The effect is most
pronounced with low values of RSENSE and can be
improved by operating at higher frequencies with lower
values of L. The output remains in regulation at all times.
Checking Transient Response
Switching regulators take several cycles to respond to a
step in DC (resistive) load current. When a load step
occurs, VOUT shifts by an amount equal to (∆ILOAD)(ESR),
where ESR is the effective series resistance of COUT.
∆ILOAD also begins to charge or discharge COUT until the
1000
L = 50µH
RSENSE = 0.02Ω
regulator loop adapts to the current change and returns
VOUT to its steady state value. During this recovery time
VOUT can be monitored for overshoot or ringing which
would indicate a stability problem. The Pin 7 external
components shown in the Figure 1 circuit will prove
adequate compensation for most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
COUT (µF)
800
LTC1149 Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1149 adjustable version is used with an external
resistive divider from VOUT to VFB Pin 10. The regulated
voltage is determined:
L = 25µH
RSENSE = 0.02Ω
600
400
L = 50µH
RSENSE = 0.05Ω
200
0
1
0
3
4
2
(VIN – VOUT) VOLTAGE (V)
)
VOUT = 1.25 1 + R2
R1
5
)
In applications where VOUT is greater than the LTC1149
internally regulated VCC voltage, RSENSE must be moved to
1149 F04
Figure 4. Minimum Suggested COUT
VIN
1N4148
CAP
PGATE
VCC
1µF
150µF
50V
IRF9Z34
0.068µF
+
+
1N4148
VIN
100µH
0.047µF
PDRIVE
VCC
IRFZ34
NGATE
1N5819
LTC1149
0V = NORMAL
>2V = SHUTDOWN
VFB
SHDN2
SENSE +
1k
SENSE –
CT
3300pF
CT
200pF
GNDS
+
R1
25k
1%
100pF
ITH
R2
215k
1%
1000pF
( )
VOUT = 1.25 1 + R2
R1
VALUES SHOWN FOR VOUT = 12V
150µF
16V
OS-CON
RSENSE
0.05Ω
VOUT
LOAD
OUTPUT
GROUND
CONNECTION
1149 F05
Figure 5. High Efficiency Step-Down Regulator with VOUT > VCC
11
LTC1149
LTC1149-3.3/LTC1149-5
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the ground side of the output to prevent the absolute
maximum voltage ratings of the sense pins from being
exceeded. This is shown in Figure 5. When the current
sense comparator is operating at 0V common mode, the
off-time increases approximately 40%, requiring the use
of a smaller timing capacitor CT.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100 – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1149 series circuits: 1) LTC1149 DC supply
current, 2) MOSFET gate charge current, 3) I2R losses and
4) P-channel transition losses.
1. The DC supply current is the current which flows into
VIN Pin 2 less the gate charge current. For VIN = 12V the
LTC1149 DC supply current is 0.6mA for no load, and
increases proportionally with load up to 2mA after the
LTC1149 series has entered continuous mode.
Because the DC supply current is drawn from VIN, the
resulting loss increases with input voltage. For
VIN = 24V, the DC bias losses are generally less than 3%
for load currents over 300mA. However, at very low
load currents the DC bias current accounts for nearly all
of the loss.
2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from VIN to ground. The
resulting dQ/dt is a current out of VIN which is typically
much larger than the DC supply current. In continuous
12
mode, IGATECHG = f (QN + QP). The typical gate charge
for a 0.1Ω N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
IGATECHG = 7.5mA in 100kHz continuous operation, for
a 5% to 10% typical mid-current loss with VIN = 24V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it
argues against using larger MOSFETs than necessary
to control I2R losses, since overkill can cost efficiency
as well as money!
3. I2R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continuous mode all of the output current flows through L and
RSENSE, but is “chopped” between the P-channel and
N-channel MOSFETs. If the two MOSFETs have
approximately the same RDS(ON), then the resistance of
one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For
example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω and
RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I2R losses cause the
efficiency to roll-off at high output currents.
4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typically 24V or greater). Transition losses can be estimated from:
Transition Loss ≈ 5(VIN)2 (IMAX)(CRSS)(f)
For example, if VIN = 48V, IMAX = 2A, CRSS = 300pF (a very
large MOSFET) and f = 100kHz, the transition loss is 0.7W.
A loss of this magnitude would not only kill efficiency but
would probably require additional heat sinking for the
MOSFET! See Design Example for further guidelines on
how to select the P-channel MOSFET.
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead-time, and
inductor core losses, generally account for less than 2%
total additional loss.
LTC1149
LTC1149-3.3/LTC1149-5
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LTC1149 Package Dissipation
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1149 series
to be exceeded. The LTC1149 supply current is dominated
by the gate charge supply current, which is given as a
function of operating frequency in the Typical Performance Characteristics. The LTC1149 series junction temperature can be estimated by using the equations given in
Note 1 of the Electrical Characteristics. For example, the
LT1149CS is limited to less than 11mA from a 48V supply:
TJ = 70°C + (11mA)(48V)(110°C/W)
= 128°C exceeds absolute maximum
To prevent the maximum junction temperature from being
exceeded, the Pin 2 supply current must be checked in
continuous mode when operating at the maximum VIN.
Design Example
As a design example, assume VIN = 24V, VOUT = 5V,
IMAX = 2.5A and f = 100kHz. RSENSE, CT and L can
immediately be calculated:
RSENSE = 100mV = 0.039Ω
2.5
(7.8)(10 –5)
5V
CT =
1–
= 620pF
24V
100kHz
)
)
LMIN = (5.1)(105)(0.039Ω)(620pF)(5V) = 62µH
Selection of the P-channel MOSFET involves doing calculations for different sized MOSFETs to determine the
relative loss contributions. Taking an International Rectifier IRF9Z34 for example, R DS(ON) = 0.14Ω Max,
QP = 35nC and CRSS = 200pF (VDS = VIN/2). These values
can be used to estimate the I2R losses, transition losses
and gate charge supply current losses:
Est. I2R Loss (TJ = 100°C) =
(5V/24V)(2.5)2 (1 + 0.5)0.14Ω = 270mW
Est. Transition Loss =
5(24V)2 (2.5A)(200pF)(100kHz) = 145mW
Est. Gate Charge Loss =
(100kHz)(35nC)(24V) = 85mW
The same calculations were repeated for a smaller device,
the Motorola MTD2955 (RDS(ON) = 0.3Ω) and a larger one,
the Harris RFP30P05 (RDS(ON) = 0.065Ω). The results are
summarized in the table.
CONDITIONS
VIN = 24V, VOUT = 5V
F = 100kHz, IOUT = 2.5A
P-CHANNEL MOSFET
MTD2955
IRF9Z34
RFP30P05
Est. I2R Loss (100°C)
550mW
270mW
120mW
Est. Transition Loss
110mW
145mW
290mW
Est. Gate Charge Loss
60mW
85mW
240mW
Est. Total Loss
720mW
500mW
650mW
For this set of conditions, the midsized P-channel MOSFET
actually produces the lowest total losses at IMAX. The
resulting efficiency differences will be even more pronounced at lower output currents. Note that only the I2R
and transition losses are dissipated in the MOSFET; the
gate charge supply current loss is dissipated by the
LTC1149 series.
Selection of the N-channel MOSFET is somewhat easier; it
need only be sized for the anticipated I2R losses at 100%
duty cycle (worst-case assumption for short circuit.) The
Siliconix Si9410, for example, has RDS(ON) = 0.03Ω Max
and QN = 30nC. This will produce an I2R loss of 250mW at
100°C and a gate charge supply current loss of 75mW. As
with the P-channel device, the use of a larger MOSFET may
actually result in lower midcurrent efficiency.
CIN will require an RMS current rating of at least 1.25A at
temperature, and COUT will require an ESR of 0.04Ω for
optimum efficiency. The output capacitor ESR requirement can be fulfilled by a single OS-CON or by two or more
surface mount tantalums in parallel.
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1149 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the
13
LTC1149
LTC1149-3.3/LTC1149-5
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APPLICATIO S I FOR ATIO
25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE – pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 6. Two 100Ω resistors are
inserted in series with the leads from the sense resistor.
With the addition of R3, a current is generated through R1
causing an offset of:
VOFFSET = VOUT
)
R1
R1 + R3
)
circuitry. Turning on the N-channel MOSFET when this
fault is detected will then force the system fuse to blow.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the CT Pin 6 high to when the NGATE Pin 13 goes
high is 250ns. Under shutdown conditions, the N-channel
is held off and pulling Pin 6 high will not cause the output
to be crowbarred.
A small N-channel FET can be used as an interface between
the overvoltage detect circuitry and the LTC1149 as shown
in Figure 7.
5
If VOFFSET > 25mV, the minimum threshold will be cancelled
and Burst Mode operation is prevented from occurring.
Since VOFFSET is constant, the maximum load current is
also decreased by the same offset. Thus, to get back to the
same IMAX, the value of the sense resistor must be lower:
RSENSE ≈ 75mV
IMAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 8 and 9.
L
LTC1149
SENSE +
R2
100Ω
9
+
8
1149 F06
R3
Figure 6. Suppressing Burst Mode Operation
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin 6
above 1.5V when the output voltage is greater than the
desired regulated value, will turn on the N-channel MOSFET.
A fault condition which causes the output voltage to go
above a maximum value can be detected by external
14
LTC1149
VN2222LL
6
CT
ACTIVE WHEN CROWBAR = VIN
OFF WHEN CROWBAR = GROUND
1149 F07
Figure 7. Output Crowbar Interface
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1149 series. These items are also illustrated graphically in the layout diagram of Figure 8. Check the following
in your layout:
COUT
R1
100Ω
1000pF
SENSE –
RSENSE
CROWBAR
VCC
1. Are the signal and power grounds segregated? The
LTC1149 signal ground Pin 11 must connect separately
to the (–) plate of COUT. The other ground Pins 12 and
14 should return to the source of the N-channel MOSFET,
anode of the Schottky diode and (–) plate of CIN, which
should have as short lead lengths as possible.
2. Does the LTC1149 SENSE – Pin 8 connect to a point
close to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider R1, R2 must be
connected between the (+) plate of COUT and signal
ground.
3. Are the SENSE – and SENSE + leads routed together with
minimum PC trace spacing? The differential decoupling capacitor between Pins 8 and 9 should be as close
as possible to the LTC1149. Up to 100Ω may be placed
LTC1149
LTC1149-3.3/LTC1149-5
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+
BOLD LINES INDICATE HIGH CURRENT PATHS
1N4148
CIN
+
1N4148
P-CHANNEL
VIN
0.068µF
D1
1µF
+
1
2
3
0.047µF
4
5
6
7
CT
3300pF
8
N-CHANNEL
PGATE
CAP
VIN
SD2
VCC
PDRIVE
RGND
NGATE
VCC
PGND
CT
SGND
ITH
VFB/
SHDN1
SENSE –
SENSE +
–
16
15
SHUTDOWN
14
L
13
12
11
10
–
100pF
R1
+
9
COUT
R2
1k
VOUT
RSENSE
+
1000pF
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
1149 F08
Figure 8. LTC1149 Series Layout Diagram (see Layout Checklist)
in series with each sense lead to help decouple Pins 8
and 9. However, when these resistors are used, the
capacitor should be no larger than 1000pF.
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 6.
4. Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? An additional 0.1µF ceramic capacitor between VIN and power
ground may be required in some applications.
In continuous mode (ILOAD > IBURST) the voltage on Pin 6
should be a sawtooth with a 0.9VP-P swing. This voltage
should never dip below 2V as shown in Figure 9a.
5. Is the VCC decoupling capacitor connected closely
between Pin 5 of the LTC1149 and power ground? This
capacitor carries the MOSFET driver peak currents.
6. Is the SHDN1 Pin 10 (fixed output versions only)
actively pulled to ground during normal operation? The
SHDN1 pin is high impedance and must not be allowed
to float. In adjustable versions, Pin 10 is the feedback
pin and is very sensitive to pickup from the switch node.
Care must be taken to isolate VFB from possible capacitive coupling of the inductor switch signal.
Troubleshooting Hints
Since efficiency is critical to LTC1149 series applications,
it is very important to verify that the circuit is functioning
When load currents are low (ILOAD < IBURST) Burst Mode
operation should occur with the CT pin waveform periodically falling to ground as shown in Figure 9b.
If Pin 6 is observed falling to ground at high output
currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
1149 F09
Figure 9. CT Pin 6 Waveforms
15
LTC1149
LTC1149-3.3/LTC1149-5
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TYPICAL APPLICATIO S
VIN
8V TO 20V
1N4148
+
1N4148
IRFR9024
1
0.068µF
0.047µF
2
3
4
5
6
7
+
1µF
390pF
3300pF
8
PGATE
CAP
VIN
SHDN2
VCC
R-GND
L*
68µH
16
ITH
SHDN1
SENSE –
SENSE +
VOUT
3.3V/1A
14
+
IRFR024
P-DRIVE
NGATE
LTC1149-3.3
12
VCC
PGND
SGND
RSENSE**
0.1Ω
15
13
CT
100µF
35V
1N5818
220µF
6.3V
AVX
11
10
0V = NORMAL
>2V = SHUTDOWN
9
1k
1000pF
1149 F10
*COILTRONICS CTX02-11932
**DALE WSC-1/2-0.1
Figure 10. High Efficiency 8V to 20V Input 3.3V/1A Output Regulator
VIN
8V TO 20V
1N4148
+
1N4148
220µF
35V
IRF9Z34
1
0.068µF
0.047µF
2
3
4
5
6
7
+
3.3µF
470pF
3300pF
8
PGATE
CAP
VIN
SHDN2
VCC
RGND
ITH
SHDN1
SENSE
–
SENSE
+
1k
VOUT
3.3V/3A
14
PDRIVE
NGATE
LTC1149-3.3
12
VCC
PGND
SGND
RSENSE**
0.033Ω
15
13
CT
L*
33µH
16
+
IRFZ34
1N5818
11
10
SHUTDOWN
100Ω
9
1000pF
100Ω
1149 F11
*COILTRONICS CTX33-4-KM
**KRL SL-1-C1-0R033J
Figure 11. High Efficiency 8V to 20V Input 3.3V/3A Output Regulator
16
220µF
6.3V × 2
AVX
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
VIN
5.5V TO 25V
1N4148
+
1N4148
Si9435DY
1
0.068µF
0.047µF
2
3
4
5
6
7
+
1µF
220pF
3300pF
8
PGATE
CAP
VIN
SHDN2
VCC
RGND
L*
33µH
16
ITH
SHDN1
SENSE
–
SENSE
+
VOUT
5V/2A
14
+
Si9410DY
PDRIVE
NGATE
LTC1149-5
12
VCC
PGND
S-GND
RSENSE**
0.05Ω
15
13
CT
220µF
35V
1N5818
220µF
10V × 2
AVX
11
10
SHUTDOWN
9
1k
1000pF
1149 F12
*COILTRONICS CTX33-4 Kool Mµ
**KRL SL-1-C1-0R050J
Figure 12. Ultra Wide Input Range (5.5V to 25V) High Efficiency 5V Regulator
VIN
8V TO 16V
1N4148
+
1N4148
Si9430DY
1
0.068µF
0.047µF
2
3
4
5
6
7
+
1µF
180pF
3300pF
8
PGATE
CAP
VIN
SHDN2
VCC
RGND
ITH
SHDN1
SENSE –
SENSE +
1k
VOUT
5V/2A
14
PDRIVE
NGATE
LTC1149-5
12
VCC
PGND
SGND
RSENSE**
0.05Ω
15
13
CT
L*
22µH
16
100µF
25V
+
Si9410DY
1N5818
220µF
10V
AVX
11
10
SHUTDOWN
9
1000pF
1149 F13
*DALE LPE-6562-220MB
**KRL SL-1-C1-0R050J
Figure 13. 250kHz High Efficiency 12V Input 5V/2A Output Regulator
17
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
VIN
48V
1N4148
+
1N4148
MTD2955
1
0.068µF
2
0.047µF
3
4
5
6
7
+
3.3µF
620pF
3300pF
8
PGATE
CAP
VIN
SHDN2
VCC
RGND
L*
68µH
16
ITH
SHDN1
VOUT
5V/2.5A
+
IRFZ34
MBR380
220µF
10V
OS-CON
11
10
SHUTDOWN
100Ω
9
SENSE +
SENSE –
RSENSE**
0.04Ω
14
PDRIVE
NGATE
LTC1149-5
12
VCC
PGND
SGND
0.1µF
15
13
CT
100µF
100V
1k
1000pF
100Ω
1149 F14
*HURRICANE LAB HL-KI168M
**IRC LR2512-01-R040-G
Figure 14. High Efficiency 48V Input 5V/2.5A Output Regulator
VIN
8V TO 20V
1N4148
+
1N4148
RFD15P05SM
1
0.068µF
0.047µF
2
3
4
5
6
7
+
1µF
390pF
3300pF
8
PGATE
CAP
VIN
SHDN2
VCC
RGND
PDRIVE
NGATE
LTC1149
VCC
PGND
CT
SGND
ITH
VFB
SENSE –
SENSE +
1k
L*
50µH
16
15
100µF
35V
RSENSE**
0.05Ω
SHUTDOWN
+
14
13
VOUT
3.3V/2A
OR 5V/2A
RFD14N05SM
1N5818
12
VN2222LL
11
10
100pF
R1A
33k
1%
R1B
43k
1%
R2
56k
1%
9
1000pF
1149 F15
*COILTRONICS CTX50-2-MP
**IRC LR2010-01-R050-G
Figure 15. Logic Selectable 5V/2A or 3.3V/2A High Efficiency Regulator
18
220µF
10V × 2
AVX
0V: VOUT = 3.3V
5V: VOUT = 5V
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
VIN
12V TO 36V
1N4148
+
1000µF
63V
220Ω
10k
2N3906
VN2222LL
0.1µF
470Ω
2N2222
1
2
3
0.1µF
PGATE
VIN
CAP
SHDM2
VCC
RGND
16
15
MUR110
13
PDRIVE
NGATE
LTC1149-5
5
12
VCC
PGND
7
+
3.3µF
820pF
3300pF
8
CT
SGND
ITH
SHDN1
SENSE –
SENSE +
RSENSE**
0.02Ω
VOUT
5V/5A
14
4
6
MTP30N06EL L*
50µH
IRFZ44
11
+
MBR380
220µF
10V × 2
OS-CON
0V = NORMAL
>2V = SHUTDOWN
10
100Ω
9
1k
1000pF
100Ω
1149 F16
SEE APPLICATIONS INFORMATION TO SUPPRESS
Burst ModeTM OPERATION AT LOW CURRENTS
*COILTRONICS CTX50-5-52
**DALE LVR-3-0.02
Figure 16. 25W High Efficiency Regulator Using N-Channel MOSFET Switches
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
0.770*
(19.558)
MAX
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
0.065 (6.477 ± 0.381)
(1.651)
TYP
0.125
(3.175)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
N16 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1149
LTC1149-3.3/LTC1149-5
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
16
0.004 – 0.010
(0.101 – 0.254)
15
13
14
12
11
10
9
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
3
2
4
5
6
7
8
S16 0695
U
TYPICAL APPLICATION
1N4148
VIN
20V TO 30V
+
1N4148
MTP23P06
1
0.068µF
0.047µF
2
3
PGATE
VIN
VCC
CAP
SHDN2
RGND
L*
100µH
16
15
SHUTDOWN
R2
172k
1%
13
PDRIVE
NGATE
LTC1149
5
12
VCC
PGND
7
+
3.3µF
300pF
3300pF
8
CT
ITH
SENSE –
SGND
VFB
SENSE +
VOUT
12V/3A
14
4
6
MTP36N06E
R1
20k
1%
100pF
150µF
16V × 2
OS-CON
RSENSE**
0.033Ω
100Ω
9
1k
+
MBR160
11
10
220µF
50V
1000pF
OUTPUT
GROUND
CONNECTION
100Ω
1149 F17
*HURRICANE LAB HL-EK210M
**KRL SL-1-C1-0R033J
Figure 17. High Efficiency 24V Input 12V/3A Output Regulator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1148HV
High Efficiency, Synchronous Step-Down Switching Regulator
4V < VIN < 20V
LTC1159
High Efficiency, Synchronous Step-Down Switching Regulator
4V < VIN < 40V, ISHUTDOWN = 20µA
LTC1435A
High Efficiency, Low Noise, Synchronous Switching Regulator
3.5V < VIN < 36V, N-Channel Driver
LTC1438
Dual, Low Noise, Synchronous Switching Regulator
3.5V < VIN < 36V, N-Channel Driver
20
Linear Technology Corporation
1149fa LT/TP 0898 REV A 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1993
工商网监
湘ICP备2023018690号
