LT3752/LT3752-1
Active Clamp Synchronous
Forward Controllers with Internal
Housekeeping Controller
DESCRIPTION
FEATURES
Input Voltage Range: LT3752: 6.5V to 100V,
LT3752-1:Limited Only by External Components
n Internal Housekeeping DC/DC Controller
n Programmable Volt-Second Clamp
n High Efficiency Control: Active Clamp,
Synchronous Rectification, Programmable Delays
n Short-Circuit (Hiccup Mode) Overcurrent Protection
n Programmable Soft-Start/Stop
n Programmable OVLO and UVLO with Hysteresis
n Programmable Frequency (100kHz to 500kHz)
n Synchronizable to an External Clock
n AEC-Q100 Qualified for Automotive Applications
The LT®3752/LT3752-1 are current mode PWM controllers
optimized for an active clamp forward converter topology.
A DC/DC housekeeping controller is included for improved
efficiency and performance. The LT3752 allows operation
up to 100V input and the LT3752-1 is optimized for applications with input voltages greater than 100V.
APPLICATIONS
The LT3752/LT3752-1 are available in a 38-lead plastic
TSSOP package with missing pins for high voltage
spacings.
n
A programmable volt-second clamp allows primary switch
duty cycles above 50% for high switch, transformer and
rectifier utilization. Active clamp control reduces switch
voltage stress and increases efficiency. A synchronous
output is available for controlling secondary side synchronous rectification.
Offline and HV Car Battery Isolated Power Supplies
48V Telecommunication Isolated Power Supplies
n Industrial, Automotive and Military Systems
n
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including XXXXX, XXXXX.
TYPICAL APPLICATION
18V to 72V, 12V/12.5A, 150W Active Clamp Isolated Forward Converter
INTVCC
2.2µF
4:4
VAUX
•
•
•
2.2µF
•
ZVN4525E6
Si2325DS
100nF
499Ω
0.15Ω
6.8µH
470µF
16V
•
15nF
10k
100Ω
ISENSEN
LT3752
1.82k
34k
31.6k
49.9k
7.32k
71.5k
22nF
0.33µF
COMP
FB
HCOMP
SS2
SS1
RT
TBLNK
IVSEC
TAS
TOS
TAO
22.6k
22nF
PGOOD
SYNC
560Ω
VAUX
3.16k
100Ω
4.7µF
4.7µF
HFB
1.1k
100k
100k
•
1µF
1.2k
CSN
CSP
CG
CSW
GND
INTVCC
10k
2.8k
•
220pF
SOUT
INTVCC
GND
0.006Ω
100k
LT8311
11.3k
220nF
499k
68pF
FB
SS
5.9k
100k
2k
VIN
INTVCC
PMODE
TIMER
UVLO_VSEC
2.2µF
FG
OC
ISENSEP
SYNC
OVLO
BSC077N12NS3
VAUX
OUT
OPTO
100k
AOUT
FSW
100Ω
HOUT HISENSE
VIN
+
VOUT
12V
12.5A
22µF
16V
×2
BSC077N12NS3
FDMS86101
COMP
VIN
18V TO 72V
4.7µF
100V
×3
68pF
13.7k
4.7nF
3752 TA01
2.2nF
EFFICIENCY: 94% AT 48VIN/10AOUT
Rev. C
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1
LT3752/LT3752-1
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Table of Contents........................................... 2
Absolute Maximum Ratings............................... 3
Order Information........................................... 3
Pin Configuration........................................... 3
Electrical Characteristics.................................. 4
Pin Functions............................................... 13
Block Diagram.............................................. 15
Timing Diagrams.......................................... 16
Operation................................................... 19
Introduction ........................................................ 19
LT3752 Part Start-Up.......................................... 19
LT3752-1 Part Start-Up....................................... 19
Applications Information................................. 21
Programming System Input Undervoltage Lockout
(UVLO) Threshold and Hysteresis....................... 21
Soft-Stop Shutdown............................................ 21
Micropower Shutdown........................................ 21
Programming System Input Overvoltage Lockout
(OVLO) Threshold................................................ 21
LT3752-1 Micropower Start-Up from High System
Input Voltages.....................................................22
Programming Switching Frequency.....................23
Synchronizing to an External Clock.....................23
INTVCC Regulator Bypassing and Operation ....... 24
HOUSEKEEPING CONTROLLER............................... 24
Housekeeping: Operation.....................................25
Housekeeping: Soft-Start/Shutdown...................25
Housekeeping: Programming Output Voltage......25
Housekeeping: Programming Cycle-by-Cycle Peak
Inductor Current and Slope Compensation..........25
Housekeeping: Adaptive Leading Edge Blanking.. 26
Housekeeping: Overcurrent Hiccup Mode............26
Housekeeping: Output Overvoltage and Power
Good ...................................................................26
Housekeeping: Transformer Turns Ratio and
Leakage Inductance.............................................26
Housekeeping: Operating Without This Supply.... 27
FORWARD CONTROLLER........................................ 27
Adaptive Leading Edge Blanking Plus
Programmable Extended Blanking...................... 27
Current Sensing and Programmable Slope
Compensation..................................................... 28
Overcurrent: Hiccup Mode................................... 28
Programming Maximum Duty Cycle Clamp: DVSEC
(Volt-Second Clamp)...........................................29
DVSEC Open Loop Control: No Opto-Coupler, Error
Amplifier or Reference.........................................30
RIVSEC: Open Pin Detection Provides Safety........30
Transformer Reset: Active Clamp Technique ......30
LO Side Active Clamp Topology (LT3752)............ 32
HI Side Active Clamp Topology (LT3752-1)..........33
Active Clamp Capacitor Value and
Voltage Ripple.....................................................33
Active Clamp MOSFET Selection.........................34
Programming Active Clamp Switch Timing: AOUT
to OUT (t AO) and OUT to AOUT (tOA) Delays........35
Programming Synchronous Rectifier Timing:
SOUT to OUT (tSO) and OUT to SOUT (tOS)
Delays..................................................................35
Soft-Start (SS1, SS2)..........................................36
Soft-Stop (SS1)...................................................36
Hard-Stop (SS1, SS2).......................................... 37
OUT, AOUT, SOUT Pulse-Skipping Mode............. 37
AOUT Timeout.....................................................38
Main Transformer Selection................................38
Primary-Side Power MOSFET Selection..............40
Synchronous Control (SOUT)..............................40
Output Inductor Value.......................................... 41
Output Capacitor Selection.................................. 41
Input Capacitor Selection.................................... 41
PCB Layout / Thermal Guidelines ....................... 42
Typical Applications....................................... 44
Package Description...................................... 50
Revision History........................................... 51
Typical Application........................................ 52
Related Parts............................................... 52
Rev. C
2
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LT3752/LT3752-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW
VIN (LT3752)............................................................100V
UVLO_VSEC, OVLO.....................................................20V
VIN (LT3752-1)..................................................16V, 8mA
INTVCC, SS2..............................................................16V
FB, SYNC.....................................................................6V
SS1, COMP, HCOMP, HFB, RT......................................3V
ISENSEP, ISENSEN, OC, HISENSE.................................0.35V
IVSEC...................................................................–250µA
Operating Junction Temperature Range (Notes 2, 3)
LT3752EFE, LT3752EFE-1................... –40°C to 125°C
LT3752IFE, LT3752IFE-1..................... –40°C to 125°C
LT3752HFE, LT3752HFE-1.................. –40°C to 150°C
LT3752MPFE, LT3752MPFE-1............. –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)................... 300°C
HFB
1
38 PGND
HCOMP
2
37 NC
RT
3
36 HISENSE
FB
4
COMP
5
SYNC
6
SS1
7
IVSEC
8
UNLO_VSEC
9
OVLO 10
TAO 11
34 HOUT
32 AOUT
39
PGND
GND
30 SOUT
28 VIN
TAS 12
TOS 13
26 INTVCC
TBLNK 14
NC 15
24 OUT
NC 16
SS2 17
22 OC
GND 18
21 ISENSEP
PGND 19
20 ISENSEN
FE PACKAGE
VARIATION: FE38(31)
38-LEAD PLASTIC TSSOP
θJA = 25°C/W
EXPOSED PAD (PIN 39) IS PGND AND GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3752EFE#PBF
LT3752EFE#TRPBF
LT3752FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752IFE#PBF
LT3752IFE#TRPBF
LT3752FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752HFE#PBF
LT3752HFE#TRPBF
LT3752FE
38-Lead Plastic TSSOP
–40°C to 150°C
LT3752MPFE#PBF
LT3752MPFE#TRPBF
LT3752FE
38-Lead Plastic TSSOP
–55°C to 150°C
LT3752EFE-1#PBF
LT3752EFE-1#TRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752IFE-1#PBF
LT3752IFE-1#TRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752HFE-1#PBF
LT3752HFE-1#TRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–40°C to 150°C
LT3752MPFE-1#PBF
LT3752MPFE-1#TRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–55°C to 150°C
Rev. C
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3
LT3752/LT3752-1
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3752EFE#WPBF
LT3752EFE#WTRPBF
LT3752FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752IFE#WPBF
LT3752IFE#WTRPBF
LT3752FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752HFE#WPBF
LT3752HFE#WTRPBF
LT3752FE
38-Lead Plastic TSSOP
–40°C to 150°C
LT3752EFE-1#WPBF
LT3752EFE-1#WTRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752IFE-1#WPBF
LT3752IFE-1#WTRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–40°C to 125°C
LT3752HFE-1#WPBF
LT3752HFE-1#WTRPBF
LT3752FE-1
38-Lead Plastic TSSOP
–40°C to 150°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
Operational Input Voltage (LT3752)
l
6.5
Operational Input Voltage (LT3752-1)
l
10.5
VIN(ON) (LT3752)
l
VIN(OFF) (LT3752)
VIN(ON/OFF) Hysteresis (LT3752)
l
VIN(ON) (LT3752-1)
l
0.1
VIN(OFF) (LT3752-1)
TYP
MAX
UNITS
100
V
16
V
5.8
6.4
V
5.5
5.9
V
0.3
0.5
V
9.5
10.4
7.6
VIN(ON/OFF) Hysteresis (LT3752-1)
1.9
2.19
V
VIN Start-Up Current (LT3752-1)
(Notes 6, 7)
l
170
265
µA
VIN Quiescent Current (Housekeeping Controller
Only) (LT3752)
HCOMP = 1V (Housekeeping Not Switching),
HFB = 0.85V
l
4
6.2
mA
VIN Quiescent Current (Housekeeping Controller
Only) (LT3752-1)
HCOMP = 1V (Housekeeping Not Switching),
HFB = 0.85V
l
3
4.6
mA
VIN Quiescent Current (Housekeeping Controller +
Forward Controller)
HCOMP = 1V (Housekeeping Not Switching),
HFB = 1.35V, FB = 1.5V (Main Loop Not Switching)
7.5
9.5
mA
UVLO_VSEC Micropower Threshold (VSD)
IVIN < 20µA
0.4
0.6
V
VIN Shutdown Current (Micropower)
UVLO_VSEC = 0.2V
20
40
µA
1.250
1.320
V
165
220
l
UVLO_VSEC Threshold (VSYS_UV)
l
l
VIN Shutdown Current (After Soft-Stop)
UVLO_VSEC = 1V
UVLO_VSEC (ON) Current
UVLO_VSEC = VSYS_UV + 50mV
UVLO_VSEC (OFF) Current
Hysteresis Current
With One-Shot Communication Current
UVLO_VSEC = VSYS_UV – 50mV
OVLO (Falling) (Restart SS1)
0.2
1.180
0
µA
µA
l
4.0
5
25
6.0
µA
µA
l
1.220
1.250
1.280
V
(Note 15)
OVLO (Rising) (No Switching, Reset SS1)
1.61
V
V
1.215
V
Rev. C
4
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LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
OVLO Hysteresis
OVLO Pin Current (Note 10)
l
MIN
TYP
MAX
23
35
47
mV
5
0.9
5
100
100
nA
mA
nA
OVLO = 0V
OVLO = 1.5V (SS1 = 2.7V)
OVLO = 1.5V (SS1 = 1.0V)
UNITS
Oscillator (Forward Controller: OUT, SOUT, AOUT)
Frequency: fOSC = 100kHz
RT = 82.5k
Frequency: fOSC = 300kHz
RT = 24.9k
Frequency: fOSC = 500kHz
RT = 14k
fOSC Line Regulation
RT = 24.9k
6.5V < VIN < 100V (LT3752)
10.5V < VIN < 16V (LT3752-1)
Frequency and DVSEC Foldback Ratio (LT3752) (Fold)
SS1 = VSSACT + 25mV, SS2 = 2.7V
l
94
100
106
kHz
279
300
321
kHz
470
500
530
kHz
0.05
0.05
0.1
0.1
%/V
%/V
1.8
V
4
Frequency and DVSEC Foldback Ratio (LT3752-1) (Fold) SS1 = VSS1ACT + 25mV, SS2 = 2.7V
SYNC Input High Threshold
2
(Note 4)
l
SYNC Input Low Threshold
(Note 4)
l
SYNC Pin Current
SYNC = 6V
SYNC Frequency/Programmed fOSC
1.2
0.6
1.025
V
75
µA
1.0
1.25
kHz/kHz
Linear Regulator (INTVCC) (LT3752)
INTVCC Regulation Voltage
6.6
7
7.2
V
Dropout (VIN-INTVCC)
VIN = 6.5V, IINTVCC = 10mA
0.8
INTVCC UVLO(+)
(Start Switching)
4.75
5
V
INTVCC UVLO(–)
(Stop Switching)
4.6
4.85
V
0.075
0.15
0.24
V
9.4
10
10.4
V
INTVCC UVLO Hysteresis
V
Linear Regulator (INTVCC) (LT3752-1)
INTVCC Regulation Voltage
Dropout (VIN-INTVCC)
VIN = 8.75V, IINTVCC = 10mA
INTVCC UVLO(+)
(Start Switching)
INTVCC UVLO(–)
(Stop Switching)
0.6
7
INTVCC UVLO Hysteresis
V
7.4
V
6.8
7.2
V
0.1
0.2
0.3
V
15.9
16.5
17.2
V
Linear Regulator (INTVCC) (LT3752/LT3752-1)
INTVCC OVLO(+)
(Stop Switching)
INTVCC OVLO(–)
(Start Switching)
15.4
16
16.7
V
0.38
0.5
0.67
V
l
l
17
35
35
23
50
50
29
60
60
l
1.220
INTVCC OVLO Hysteresis
INTVCC Current Limit
INTVCC = 0V
INTVCC = 5.75V (LT3752)
INTVCC = 8.75V (LT3752-1)
mA
mA
mA
Error Amplifier
FB Reference Voltage
1.250
1.275
FB Line Reg
6.5V < VIN < 100V (LT3752)
10.5V < VIN < 16V (LT3752-1)
0.1
0.1
0.3
0.3
mV/V
mV/V
FB Load Reg
COMP_SW – 0.1V < COMP < COMP_VOH – 0.1V
0.1
0.3
mV/V
FB Input Bias Current
(Note 10)
50
200
nA
85
dB
Unity-Gain Bandwidth
(Note 8)
2.5
MHz
COMP Source Current
FB = 1V, COMP = 1.75V (Note 10)
11
mA
Open-Loop Voltage Gain
6
V
Rev. C
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5
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
TYP
COMP Sink Current
FB = 1.5V, COMP = 1.75V
6.5
11.5
mA
COMP Output High Clamp
FB = 1V
2.6
V
1.25
V
COMP Switching Threshold
MAX
UNITS
Current Sense (Main Loop)
ISENSEP Maximum Threshold
FB = 1V, OC = 0V
180
220
260
mV
COMP Current Mode Gain
∆VCOMP/∆VISENSEP
6.1
V/V
ISENSEP Input Current (D = 0%)
(Note 10)
2
µA
ISENSEP Input Current (D = 80%)
(Note 10)
33
ISENSEN Input Current
FB = 1.5V (COMP Open) (Note 10)
FB = 1V (COMP Open) (Note 10)
20
90
30
135
µA
µA
96
107.5
mV
200
500
nA
OC Overcurrent Threshold
l
82.5
OC Input Current
µA
AOUT Driver (Active Clamp Switch Control) (LT3752 External PMOS; LT3752-1 External NMOS)
AOUT Rise Time
CL = 1nF (Note 5), INTVCC = 12V
23
ns
AOUT Fall Time
CL = 1nF (Note 5), INTVCC = 12V
19
ns
0.1
V
AOUT Low Level
AOUT High Level
INTVCC = 12V
11.9
V
AOUT High Level in Shutdown (LT3752)
UVLO_VSEC = 0V, INTVCC = 8V, IAOUT = 1mA Out
of the Pin
7.8
V
AOUT Low Level in Shutdown (LT3752-1)
UVLO_VSEC = 0V, INTVCC = 12V, IAOUT = 1mA Into
the Pin
AOUT Edge to OUT (Rise): (tAO)
CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTAO = 44.2k
RTAO = 73.2k (Note 11)
168
253
218
328
268
403
ns
ns
OUT (Fall) to AOUT Edge: (tOA)
CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTAO = 44.2k
RTAO = 73.2k (Note 12)
150
214
196
295
250
376
ns
ns
0.25
V
SOUT Driver (Synchronous Rectification Control)
SOUT Rise Time
COUT = 1nF, INTVCC = 12V (Note 5)
21
ns
SOUT Fall Time
COUT = 1nF, INTVCC = 12V (Note 5)
19
ns
SOUT Low Level
0.1
V
SOUT High Level
INTVCC = 12V
11.9
V
SOUT High Level in Shutdown
UVLO_VSEC = 0V, INTVCC = 8V, ISOUT = 1mA Out
of the Pin
7.8
V
AOUT Edge to SOUT (Fall): (tAS)
CAOUT = CSOUT = 1nF, INTVCC = 12V
RTAS = 44.2k (Note 13)
RTAS = 73.2k
168
253
218
328
268
403
ns
ns
SOUT (Fall) to OUT (Rise): (tSO = tAO – tAS)
CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTAO = 73.2k, RTAS = 44.2k (Notes 11, 13)
RTAO = 44.2k, RTAS = 73.2k
70
–70
110
–110
132
–132
ns
ns
OUT (Fall) to SOUT (Rise): (tOS)
CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTOS = 14.7k
RTOS = 44.2k (Note 14)
52
102
68
133
84
164
ns
ns
OUT Driver (Main Power Switch Control)
OUT Rise Time
COUT = 3.3nF, INTVCC = 12V (Note 5)
19
ns
OUT Fall Time
COUT = 3.3nF, INTVCC = 12V (Note 5)
20
ns
0.1
V
OUT Low Level
Rev. C
6
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LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
OUT High Level
INTVCC = 12V
11.9
OUT Low Level in Shutdown
UVLO_VSEC = 0V, INTVCC = 8V, IOUT = 1mA Into
the Pin
OUT (Volt-Sec) Max Duty Cycle Clamp
DVSEC (1 • System Input (Min)) × 100
DVSEC (2 • System Input (Min)) × 100
DVSEC (4 • System Input (Min)) × 100
RT = 24.9k, RIVSEC = 51.1k, FB = 1V, SS1 = 2.7V
UVLO_VSEC = 1.25V
UVLO_VSEC = 2.50V
UVLO_VSEC = 5.00V
OUT Minimum ON Time
COUT = 3.3nF, INTVCC = 12V (Note 9)
RTBLNK = 14.7k
RTBLNK = 73.2k (Note 16)
TYP
MAX
V
0.25
68.5
34.3
17.5
UNITS
72.5
36.5
18.6
V
76.2
38.7
19.7
%
%
%
325
454
ns
ns
150
mV
1.25
V
SS1 Pin (Soft-Start: Frequency and DVSEC) (Soft-Stop: COMP Pin, Frequency and DVSEC)
SS1 Reset Threshold (VSS1(RTH))
SS1 Active Threshold (VSS1(ACT))
(Allow Switching)
SS1 Charge Current (Soft-Start)
SS1 = 1.5V (Note 10)
SS1 Discharge Current (Soft-Stop)
SS1 = 1V, UVLO_VSEC = VSYS_UV – 50mV
SS1 Discharge Current (Hard Stop)
OC > OC Threshold
INTVCC < INTVCC UVLO(–)
OVLO > OVLO(+)
SS1 = 1V
7
11.5
16
µA
6.4
10.5
14.6
µA
0.9
0.9
0.9
mA
mA
mA
2.8
mA
SS2 Pin (Soft-Start: Comp Pin)
SS2 Discharge Current
SS1 < VSS(ACT), SS2 = 2.5V
SS2 Charge Current
SS1 > VSS(ACT), SS2 = 1.5V
11
21
28
0.90
1.000
1.10
µA
Error Amplifier (Housekeeping Controller)
HFB Reference Voltage
V
HFB Line Reg
6.5V < VIN < 100V (LT3752)
10.5V < VIN < 16V (LT3752-1)
0.1
0.1
mV/V
mV/V
HFB Load Reg
HCOMP VSW – 0.1V < HCOMP < HCOMP VOH –
0.1V
–6
mV/V
HFB Input Bias Current
HFB = 1.1V (Note 10)
85
Transconductance
∆IHCOMP ±5µA
250
µS
Voltage Gain
175
V/V
Power Good(+) (HFB Level)
0.96
V
0.92
V
1.206
V
Power Good(–) (HFB Level)
HFB OVLO(+)
(Disable HOUT Switching)
HFB OVLO(–)
(Enable Housekeeping Operation)
HCOMP Source Current
HCOMP = 1.75V (Note 10)
11
HCOMP Sink Current
HCOMP = 1.75V
13
170
1.150
nA
V
15
19
µA
18
23
µA
HCOMP Output High Clamp
2.9
V
HCOMP Switching Threshold
1.28
V
Current Sense (Housekeeping Controller)
HISENSE Peak Current Threshold
HFB = 0.8V
HCOMP Current Mode Gain
∆VHCOMP/∆VHISENSE
9.1
V/V
HISENSE Input Current (D = 0%)
HISENSE Input Current (D = 80%)
(Note 10)
2
52
µA
µA
HISENSE Overcurrent Threshold
69
84.6
79
98
86.5
105.4
mV
mV
Rev. C
For more information www.analog.com
7
LT3752/LT3752-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HOUT Driver (Housekeeping Controller)
HOUT Rise Time
CL = 1nF (Note 5), INTVCC = 12V
13
ns
HOUT Fall Time
CL = 1nF (Note 5), INTVCC = 12V
12
ns
0.1
V
HOUT Low Level
HOUT High Level
LT3752
LT3752-1
INTVCC = 12V
11.9
11.9
V
V
HOUT Low Level in Shutdown
UVLO_VSEC = 0V, INTVCC = 12V, IHOUT = 1mA
Into the Pin
HOUT Maximum Duty Cycle
HCOMP = 2.7V, RT = 24.9k
95
%
HOUT Minimum ON Time
CL = 1nF (Note 9), INTVCC = 12V
350
ns
HCOMP SW ≥ HCOMP VOH – 0.1V
2.2
4
ms
55
65
75
kHz
119
141
163
kHz
279
300
321
kHz
0.25
90
V
Soft-Start (HSS) (Housekeeping Controller)
HSS (Internal) Ramp Time (tHSS)
Oscillator (Housekeeping Controller)
Frequency (fHOUT) (fOSC Folded Back) (LT3752)
HFB = 0.8V, RT = 24.9k, SS1 = 0V
Frequency (fHOUT) (fOSC Folded Back) (LT3752-1)
HFB = 0.8V, RT = 24.9k, SS1 = 0V
Frequency (fHOUT) (Full-Scale fOSC)
HFB = 1.15V, HCOMP = 2.7V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3752EFE/LT3752EFE-1 are guaranteed to meet performance
specifications from 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3752IFE/LT3752IFE-1 are guaranteed to meet performance
specifications from –40°C to 125°C junction temperature. The LT3752HFE/
LT3752HFE-1 are guaranteed to meet performance specifications from
–40°C to 150°C junction temperature. The LT3752MPFE/LT3752MPFE-1
are tested and guaranteed to meet performance specifications from –55°C
to 150°C junction temperature.
Note 3: For maximum operating ambient temperature, see the Thermal
Calculations section in the Applications Information section.
Note 4: SYNC minimum and maximum thresholds are guaranteed by
SYNC frequency range test using a clock input with guard banded SYNC
levels of 0.7V low level and 1.7V high level.
Note 5: Rise and fall times are measured between 10% and 90% of gate
driver supply voltage.
l
Note 6: Guaranteed by correlation to static test.
Note 7: VIN start-up current is measured at VIN = VIN(ON) – 0.25V and then
scaled by 1.18× to correlate to worst-case VIN current required for part
start-up at VIN = VIN(ON).
Note 8: Guaranteed by design.
Note 9: ON times are measured between rising and falling edges at 50% of
gate driver supply voltage.
Note 10: Current flows out of pin.
Note 11: Guaranteed by correlation to RTAS = 73.2k test.
Note 12: tOA timing guaranteed by design based on correlation to
measured tAO timing.
Note 13: Guaranteed by correlation to RTAO = 44.2k test.
Note 14: Guaranteed by correlation to RTOS = 14.7k test.
Note 15: A 2µs one-shot of 20µA from the UVLO_VSEC pin allows
communication between ICs to begin shutdown (useful when stacking
supplies for more power ( = inputs in parallel/outputs in series)). The
current is tested in a static test mode. The 2µs one-shot is guaranteed by
design.
Note 16: Guaranteed by correlation to RTBLNK = 14.7k test.
Rev. C
8
For more information www.analog.com
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
VIN Start-Up and Shutdown Current
vs Junction Temperature
VIN(ON), VIN(OFF) Thresholds
vs Junction Temperature
10.0
200
9.5
180
9.0
120
LT3752-1 VIN START-UP CURRENT
(VIN = VIN_ON)
100
80
60
40
LT3752/LT3752-1 VIN SHUTDOWN CURRENT
(VIN = 12V) UVLO_VSEC = 0.2V
20
8
LT3752-1 VIN_ON
7
8.0
LT3752-1 VIN_OFF
7.5
7.0
6.5
LT3752 VIN_ON
6.0
5.5
4.5
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G03
UVLO_VSEC Hysteresis Current
vs Junction Temperature
HFB PGOOD Thresholds
vs Junction Temperature
1.240
1.235
1.230
1.225
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
1.20
1.15
HFB PGOOD THRESHOLDS (V)
UVLO_VSEC HYSTERESIS CURRENT (µA)
1.245
5.5
5.0
4.5
1.10
1.05
1.00
4.0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
HFB PGOOD (+) = ENABLE FORWARD
CONTROLLER CIRCUITRY
0.95
0.90
0.85
3752 G04
HFB PGOOD (–) = DISABLE FORWARD
CONTROLLER CIRCUITRY
0.80
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G05
HFB Reference Voltage
vs Junction Temperature
3752 G06
HFB OVLO Thresholds
vs Junction Temperature
1.30
1.100
HFB OVLO THRESHOLDS (V)
1.075
HFB REFERENCE VOLTAGE (V)
UVLO_VSEC THRESHOLD (V)
1.250
LT3752-1: HOUSEKEEPING ONLY
(NO SWITCHING)
0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
6.0
1.255
3
3752 G02
1.275
1.260
4
LT3752: HOUSEKEEPING ONLY
(NO SWITCHING)
1
LT3752 VIN_OFF
UVLO_VSEC Turn-On Threshold
vs Junction Temperature
1.265
5
2
3752 G01
1.270
LT3752/-1: HOUSEKEEPING + FORWARD
(NO SWITCHING)
6
8.5
5.0
0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
VIN Quiescent Current vs Junction
Temperature
VIN IQ (mA)
VIN CURRENT (µA)
140
VIN ON/OFF THRESHOLDS (V)
220
160
TA = 25°C, unless otherwise noted.
1.050
1.025
1.000
0.975
0.950
0.925
0.900
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
1.25
HFB > OVLO (+) = DISABLE HOUT
SWITCHING
1.20
1.15
1.10
HFB < OVLO (–) = ENABLE HOUSEKEEPING
OPERATION
1.05
1.00
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G07
3752 G08
Rev. C
For more information www.analog.com
9
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
60
84
HISENSE Pin Current vs Duty Cycle
50
82
81
80
79
78
77
105
40
100
30
20
TJ = 150°C
TJ = 25°C
TJ = –55°C
10
76
0
75
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
0
3752 G10
3.00
2.75
2.50
4.80
5.5
5.0
4.5
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 15mA
ILOAD = 20mA
3.0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
LT3752: INTVCC Regulation
Voltage vs Current, Junction
Temperature
10.0
VIN = 12V
9.5
INTVCC < UVLO (–): DISABLE SWITCHING
4.60
4.55
4.50
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G14
VIN = 12V
8.5
6.85
INTVCC (V)
INTVCC (V)
4.65
9.0
6.90
6.80
6.75
6.65
4.70
LT3752-1: INTVCC in Dropout at
VIN = 8.75V vs Current, Junction
Temperature
6.95
6.70
INTVCC > UVLO (+): ENABLE SWITCHING
4.75
3752 G13
3752 G12
7.00
LT3752: INTVCC UVLO Thresholds
vs Junction Temperature
6.5
3.5
1.50
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G11
4.85
4.0
1.75
85
7.0
6.0
2.00
90
LT3752: INTVCC in Dropout at
VIN = 6.5V vs Current, Junction
Temperature
INTVCC (V)
HOUSEKEEPING INTERNAL SOFT-START TIME (ms)
Housekeeping Internal Soft-Start
Time (HSS) vs Junction
Temperature
95
80
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3752 G09
2.25
110
INTVCC UVLO THRESHOLD (V)
83
HISENSE PIN CURRENT (µA)
HISENSE PEAK CURRENT THRESHOLD (mV)
85
HISENSE Overcurrent
(Hiccup Mode) Threshold
vs Junction Temperature
HISENSE OVERCURRENT THRESHOLD (mV)
HISENSE Peak Current Threshold
vs Junction Temperature
TA = 25°C, unless otherwise noted.
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 20mA
ILOAD = 30mA
6.60
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G15
8.0
7.5
7.0
6.5
6.0
5.5
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 15mA
ILOAD = 20mA
5.0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G16
Rev. C
10
For more information www.analog.com
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
LT3752-1: INTVCC Regulation
Voltage vs Current, Junction
Temperature
LT3752-1: INTVCC UVLO Thresholds
vs Junction Temperature
10.00
7.15
9.95
7.10
9.90
13.0
9.85
12.5
6.95
6.90
6.85
9.80
6.70
9.75
9.70
9.65
9.60
6.80
6.75
SS1 CURRENTS (µA)
7.00
INTVCC > UVLO (+): ENABLE FORWARD
CONVERTER SWITCHING
13.5
INTVCC < UVLO (–): DISABLE FORWARD
CONVERTER SWITCHING
9.55
9.50
9.45
6.60
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
9.40
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
2.00
SS1 ACTIVE LEVEL
(ALLOW FORWARD CONVERTER SWITCHING)
1.00
0.75
0.25
SS1 RESET LEVEL (RESET SS1 LATCH)
0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
23
22
21
20
19
18
17
16
15
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
8.5
8.0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G19
SWITCHING FREQUENCY (kHz)
350
RT = 24.9k
325
LT3752-1
300
f(HOUT)
275
f(OUT)
250
225
200
175
f(HOUT)LT3752-1
LT3752
150
f(HOUT)
125
f(OUT)
100
f(HOUT)LT3752
75
50
25
f(OUT)
0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75
SS1 (V)
3752 G21
Switching Frequency
vs Junction Temperature
320
SS1 SOFT-STOP: DISCHARGE CURRENT
Switching Frequency
vs SS1 Pin Voltage
SS2 PIN CURRENT* (–1)
3752 G20
325
9.5
9.0
24
3752 G22
FB Reference Voltage
vs Junction Temperature
1.30
RT = 24.9k
1.29
315
FB REFERENCE VOLTAGE (V)
0.50
SS2 SOFT-START CHARGE CURRENT (µA)
2.25
1.25
10.0
25
SS1 HIGH LEVEL
2.50
1.50
10.5
SS2 Soft-Start Charge Current
vs Junction Temperature
3.00
1.75
11.0
3752 G18
SS1 High, Active and Reset
Levels vs Junction Temperature
SS1 SOFT-START: CHARGE CURRENT* (–1)
11.5
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 20mA
ILOAD = 30mA
6.65
2.75
12.0
SWITCHING FREQUENCY (kHz)
7.05
14.0
VIN = 12V
3752 G17
SS1 HIGH, ACTIVE AND RESET LEVELS (V)
SS1 Soft-Start/Soft-Stop Pin
Currents vs Junction Temperature
7.20
INTVCC (V)
INTVCC UVLO THRESHOLDS (V)
TA = 25°C, unless otherwise noted.
310
305
300
295
290
285
1.28
1.27
1.26
1.25
1.24
1.23
1.22
280
1.21
275
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
1.20
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G23
3752 G24
Rev. C
For more information www.analog.com
11
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
ISENSEP Maximum Threshold – VSLP
vs Duty Cycle (Programming Slope
Compensation)
ISENSEP MAXIMUM THRESHOLD - VSLOPE (V)
240
ISENSEP THRESHOLD (mV)
220
200
180
160
140
120
100
OC THRESHOLD
60
40
20
0
1.2
1.4
1.6
1.8
2
COMP (V)
2.2
2.4
2.6
240
110
VSLP = I(ISENSEP) • RISLP
220
RISLP = 0Ω
200
RISLP = 1.5kΩ
180
RISLP = 2kΩ
160
140
0
160
140
120
280
60
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
tOA
RTAO = 73.2k
240
220
180
RTBLNK = 14.7k
tAO
tOA
RTAO = 44.2k
260
240
220
RTAS = 44.2k
200
180
160
140
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
140
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G30
3752 G29
SOUT (Fall) to OUT (Rise) Delay
(tSO = tAO – tAS) vs Junction
Temperature
120
160
RTAO = 73.2k, RTAS = 44.2k
OUT (Fall) to SOUT (Rise) Delay
(tOS) vs Junction Temperature
140
60
120
40
20
tSO (ns)
tSO (ns)
280
160
3752 G28
0
–20
–40
RTOS = 44.2k
100
80
RTOS = 14.7k
60
–60
–100
RTAS = 73.2k
300
260
200
320
tAS (ns)
180
tAO AND tCA (ns)
EXTENDED BLANKING DURATION (ns)
AOUT to SOUT Delay (tAS)
vs Junction Temperature
tAO
300
–80
85
340
320
RTBLNK = 73.2k
80
90
3752 G27
340
100
95
AOUT to OUT Delay (tAO) and OUT
to AOUT Delay (tOA) vs Junction
Temperature
220
80
100
3752 G26
Extended Blanking Duration
vs Junction Temperature
200
105
80
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3752 G25
100
OC Overcurrent
(Hiccup Mode) Threshold
vs Junction Temperature
OC OVERCURRENT THRESHOLD (mV)
ISENSEP Maximum Threshold
vs COMP
80
TA = 25°C, unless otherwise noted.
40
RTAO = 44.2k, RTAS = 73.2k
–120
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
RTOS = 7.32k
20
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
3752 G31
3752 G32
Rev. C
12
For more information www.analog.com
LT3752/LT3752-1
TYPICAL PERFORMANCE CHARACTERISTICS
50
40
30
20
120
100
10
0
60
140
PROGRAMMED RIVSEC (k)
60
80
60
40
20
0
OUT Pin Rise/Fall Times
vs OUT Pin Load Capacitance
160
VIN = 12V
RT = 24.9k (300kHz)
RIVSEC = 51.1k
70
IDVSEC × 100 (%)
Required RIVSEC vs Switching
Frequency (for DVSEC × 100 = 72.5%,
UVLO_VSEC = 1.25V)
OUT Maximum Duty Cycle Clamp
(DVSEC) vs UVLO_VSEC
OUT PIN RISE/FALL TIMES (ns)
80
TA = 25°C, unless otherwise noted.
1.25 2.5 3.75 5 6.25 7.5 8.75 10
UVLO_VSEC (V)
0
100 150 200 250 300 350 400 450 500
SWITCHING FREQUENCY (kHz)
3752 G33
3752 G34
INTVCC = 12V
(OVERDRIVEN FROM
HOUSEKEEPING SUPPLY)
50
40
30
20
10
0
0
1
2 3 4 5 6 7 8 9
OUT PIN LOAD CAPACITANCE (nF)
10
3752 G35
PIN FUNCTIONS
HFB (Pin 1): Housekeeping Supply Error Amplifier
Inverting Input.
HCOMP (Pin 2): Housekeeping Supply Error Amplifier
Output and Compensation Pin.
RT (Pin 3): A resistor to ground programs switching
frequency.
FB (Pin 4): Error Amplifier Inverting Input.
COMP (Pin 5): Error Amplifier Output. Allows various
compensation networks for nonisolated applications.
SYNC (Pin 6): Allows synchronization of internal oscillator
to an external clock. fSYNC equal to fOSC allowed.
SS1 (Pin 7): Capacitor controls soft-start/stop of switching frequency and volt-second clamp. During soft-stop it
also controls the COMP pin.
IVSEC (Pin 8): Resistor Programs OUT Pin Maximum
Duty Cycle Clamp (DVSEC). This clamp moves inversely
proportional to system input voltage to provide a voltsecond clamp.
UVLO_VSEC (Pin 9): A resistor divider from system input allows switch maximum duty cycle to vary inversely
proportional with system input. This volt-second clamp
prevents transformer saturation for duty cycles above
50%. Resistor divider ratio programs undervoltage lockout
(UVLO) threshold. A 5µA pin current hysteresis allows
programming of UVLO hysteresis. Pin below 0.4V reduces
VIN currents to microamps.
OVLO (Pin 10): A resistor divider from system input
programs overvoltage lockout (OVLO) threshold. Fixed
hysteresis included.
TAO (Pin 11): A resistor programs nonoverlap timing
between AOUT rise and OUT rise control signals.
TAS (Pin 12): Resistors at TAO and TAS define delay between
SOUT fall and OUT rise (= tAO – tAS).
TOS (Pin 13): Resistor programs delay between OUT fall
and SOUT rise.
TBLNK (Pin 14): Resistor programs extended blanking of
ISENSEP and OC signals during MOSFET turn-on.
NC (Pins 15, 16, 37): No Connect Pins. These pins are not
connected inside the IC. These pins should be left open.
SS2 (Pin 17): Capacitor controls soft-start of COMP pin.
Alternatively can connect to OPTO to communicate start of
switching to secondary side. If unused, leave the pin open.
GND (Pin 18): Analog Signal Ground. Electrical connection
exists inside the IC to the exposed pad (Pin 39).
Rev. C
For more information www.analog.com
13
LT3752/LT3752-1
PIN FUNCTIONS
PGND (Pins 19, 38, 39): The Power Grounds for the IC.
The package has an exposed pad (Pin 39) underneath the
IC which is the best path for heat out of the package. Pin 39
should be soldered to a continuous copper ground plane
under the device to reduce die temperature and increase
the power capability of the LT3752/LT3752-1.
ISENSEN (Pin 20): Negative input for the current sense
comparator. Kelvin connect to the sense resistor in the
source of the power MOSFET.
ISENSEP (Pin 21): Positive input for the current sense
comparator. Kelvin connect to the sense resistor in the
source of the power MOSFET. A resistor in series with
ISENSEP programs slope compensation.
OC (Pin 22): An accurate 96mV threshold, independent
of duty cycle, for detection of primary side MOSFET overcurrent and trigger of hiccup mode. Connect directly to
sense resistor in the source of the primary side MOSFET.
Missing Pins 23, 25, 27, 29, 31, 33, 35: Pins removed
for high voltage spacings and improved reliability.
OUT (Pin 24): Drives the gate of an N-channel MOSFET
between 0V and INTVCC. Active pull-off exists in shutdown.
INTVCC (Pin 26): A linear regulator supply generated from
VIN. LT3752 supplies 7V for AOUT, SOUT, OUT and HOUT
gate drivers. LT3752-1 supplies 10V for AOUT,SOUT, and
OUT gate drivers (HOUT supplied from VIN). INTVCC must
be bypassed with a 4.7µF capacitor to power ground. Can
be externally driven by the housekeeping supply to remove
power from within the IC.
VIN (Pin 28): Input Supply Pin. Bypass with 1µF to ground.
SOUT (Pin 30): Sync signal for secondary side synchronous rectifier controller.
AOUT (Pin 32): Control signal for external active clamp
switch. (P-channel LT3752, N-channel LT3752-1).
HOUT (Pin 34): Drives the gate of an N-channel MOSFET
used for the housekeeping supply. Active pull-off exists
in shutdown.
HISENSE (Pin 36): Current sense input for the house keeping supply. Connect to sense resistor in the source of the
power MOSFET. A resistor in series with HISENSE programs
slope compensation.
Rev. C
14
For more information www.analog.com
LT3752/LT3752-1
BLOCK DIAGRAM
HOUSEKEEPING CONTROLLER
1
UVLO_VSEC
1.25V
SS1 > 1.25V
HARD STOP
0.4V
5µA
HFB
+
–
1.25V
REF
1.0V
20µA (1 SHOT)
1.25V
+ –
+ –
SS1 < 150mV
10
HCOMP
–
+
79mV
CLAMP
HSS
SOFT STOP
0.9mA
OVLO
2
–
+
VIN_ON
VIN_OFF
VIN
1.25V (+)
1.215V (–)
HICCUP
HISLP
HISENSE
+
–
9
+
–
98mV
+ –
EN
+
–
UVLO_VSEC
6
3
17
7
IVSEC
PGOOD
HISLP
1.25V
100k
SYNC
HOUT
±0.7A
R Q
S
EN_SS1
VIN
–
+
INTVCC
RT
SS1 > 2.2V
OSC
+
–
ISLP
SS2
1.25V
FOLD
BACK
SS1
Q R
S
VSEC
CLAMP
R
SOFT
START
CG
ON
OFF
SOFT
STOP TJ > 170°C
– +
96mV
OC
ISLP
+
EA
–
ISENSEP
ISENSEN
FB
COMP
28
26
(0→220)mV
TAO
5
11
TAS
12
TOS
13
TBLNK GND
14
32
30
24
HICCUP
BLANK
– +
OUT
±2A
CONTROL
MAIN SWITCH
SOUT
±0.4A
SYNCHRONOUS CONTROL
HARD STOP
SS1
EN_SS1
4
FG
AOUT
±0.4A
ACTIVE CLAMP CONTROL
SS1 < 1.25V
INTVCC_OV
INTVCC_UV
SS2
1.25V
ON
OFF
S
Q
TIMING
LOGIC
S
R
34
(INVERT LEVEL FOR LT3752-1)
+
–
150mV
Q
+ –
8
OUT
36
PGND (19, 38)
18
22
21
20
3752 BD
(+ EXPOSED (+ EXPOSED
PAD PIN 39) PAD PIN 39)
PART
LT3752
LT3752-1
SYSTEM INPUT MAX
VIN PIN MAX
VIN ON/OFF
INTVCC
UVLO(+)/(REG)
AOUT PHASING
100V
100V
5.8V/5.5V
4.75V/7V
for External PMOS
Limited Only by
External Components
16V, 8mA
(Internal VIN Clamp)
9.5V/7.6V
7V/10V
for External NMOS
Rev. C
For more information www.analog.com
15
LT3752/LT3752-1
TIMING DIAGRAMS
AOUT
tOA
0V
tAO
OUT
0V
VIN/(1 – DUTY CYCLE)
VIN
SWP
0V
SOUT
tAS
0V
tSO
tOS
CG
0V
FG
0V
VOUT/(1 – DUTY CYCLE)
FSW
0V
CSW
0V
T
(1/fOSC)
3752 F01
tAO PROGRAMMED BY RTAO, tAS PROGRAMMED BY RTAS
tOS PROGRAMMED BY RTOS, tOA = 0.9 • tAO, tSO = tAO – tAS
Figure 1. LT3752 Timing Diagram
(LT3752-1 Inverts AOUT Phase for N-Channel Control)
CSW
VIN
•
OUT
SWP
FSW
M1
M3
AOUT
TAO
–VIN
CG
M4
SYNC
SOUT
TAS
FG
LTXXXX
LT3752
M2
VOUT
•
TOS
•
•
GND
3752 F02
–VOUT
Figure 2. Timing Reference Circuit
Rev. C
16
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LT3752/LT3752-1
TIMING DIAGRAMS
SYSTEM INPUT
(LT3752 VIN PIN)
SYSTEM INPUT (MIN)
+VHYST
SYSTEM INPUT (MIN)
0V
UVLO_VSEC
(RESISTOR DIVIDER
FROM SYSTEM INPUT)
TRIGGER
SOFT STOP
1.25V
0V
INTVCC
7V (REG)
OPTIONAL
BOOTSTRAP
DIODE
FROM VHK
4.75V UVLO(+)
0V
VHK
(HOUSEKEEPING
SUPPLY OUTPUT)
PGOOD(+)
(96% OF FULL-SCALE VHK)
SS1
SOFT
STARTS
fOSC AND
DVSEC
0V
SS1
SS1
SOFT
STOPS
fOSC, DVSEC
AND COMP
COMPLETED SOFT-STOP
SHUTDOWN:
0.6V < UVLO_VSEC < 1.25V
AND SS1 < 150mV
1.25V
150mV
0V
COMP
SWITCHING
THRESHOLD
1.25V
COMP
0V
SS2
SOFT
STARTS
COMP
SS2
0V
fOSC
(SWITCHING
FREQUENCY)
0Hz
FULL-SCALE fOSC
FULL-SCALE fOSC/4.6
AOUT, OUT, SOUT
SWITCHING
HOUT
SWITCHING
3752 F03
Figure 3. LT3752 Start-Up and Shutdown Timing Diagram
Rev. C
For more information www.analog.com
17
LT3752/LT3752-1
TIMING DIAGRAMS
SYSTEM INPUT
SYSTEM INPUT (MIN)
SYSTEM INPUT (MIN)
+VHYST
0V
UVLO_VSEC PIN
(RESISTOR DIVIDER
FROM SYSTEM INPUT)
TRIGGER
SOFT STOP
1.25V
0V
16V CLAMP
LT3752-1 VIN PIN V
IN(ON)
(RESISTOR FROM
SYSTEM INPUT)
0V
VIN(OFF)
BOOTSTRAP DIODE FROM VHK
10V (REG)
INTVCC
7V UVLO(+)
0V
VHK
(HOUSEKEEPING
SUPPLY OUTPUT)
SS1
OPTIONAL
BOOTSTRAP
DIODE
FROM VHK
PGOOD(+)
(96% OF FULL-SCALE VHK)
SS1
SOFT
STOPS
fOSC, DVSEC
SS1
SOFT
STARTS
fOSC AND
DVSEC
AND COMP
COMPLETED SOFT-STOP
SHUTDOWN:
0.6V < UVLO_VSEC < 1.25V
AND SS1 < 150mV
1.25V
150mV
COMP
SWITCHING
THRESHOLD
1.25V
COMP
SS2
SOFT
STARTS
COMP
SS2
FULL-SCALE fOSC
fOSC
(SWITCHING
FREQUENCY)
FULL-SCALE fOSC/2.13
AOUT, OUT, SOUT
SWITCHING
HOUT
SWITCHING
3752 F04
Figure 4. LT3752-1 Start-Up and Shutdown Timing Diagram
Rev. C
18
For more information www.analog.com
LT3752/LT3752-1
OPERATION
Introduction
LT3752 Part Start-Up
The LT3752/LT3752-1 are primary side, current mode,
PWM controllers optimized for use in a synchronous
forward converter with active clamp reset. Combined with
an integrated housekeeping controller, each IC provides
a compact, versatile, and highly efficient solution. The
LT3752 allows VIN pin operation between 6.5V and 100V.
For applications with system input voltages greater than
100V, the LT3752-1 allows RC start-up from input voltage
levels limited only by external components. The LT3752
and LT3752-1 based forward converters are targeted for
power levels up to 400W and are not intended for battery
charger applications. For higher power levels the converter
outputs can be stacked in series. Connecting UVLO_VSEC
pins, OVLO pins, SS1 pins and SS2 pins together allows
blocks to react simultaneously to all fault modes and
conditions.
LT3752 start-up is best described by referring to the Block
Diagram and to the start-up waveforms in Figure 3. For
part start-up, system input voltage must be high enough
to drive the UVLO_VSEC pin above 1.25V and the VIN pin
must be greater than 6.5V. An internal linear regulator is
activated and provides a 7V INTVCC supply for all gate
drivers. The housekeeping controller starts up before the
forward controller. An internal soft-start (HSS) ramps
the housekeeping HCOMP pin to allow switching at the
gate driver output HOUT to drive an external N-channel
MOSFET. The housekeeping controller output voltage
VHK is regulated when the HFB pin reaches 1.0V. VHK can
be used to override INTVCC to reduce power in the part,
increase efficiency and to optimize the INTVCC level. During start-up the housekeeping controller switches at the
programmed switching frequency (fOSC) folded back by
1/4.6. The SS1 pin of the forward controller is allowed to
start charging when VHK reaches 96% of its target value
(PGOOD). When SS1 reaches 1.25V, the SS2 pin begins
to charge, controlling COMP pin rise and the soft-start of
output inductor peak current. The SS1 pin independently
soft starts switching frequency and a volt-second clamp.
As SS1 charges towards 2.6V the switching frequencies
of both controllers remain equal, synchronized and soft
started towards full-scale fOSC.
Each IC contains an accurate programmable volt-second
clamp. When set above the natural duty cycle of the converter, it provides a duty cycle guardrail to limit primary
switch reset voltage and prevent transformer saturation
during load transients. The accuracy and excellent line
regulation of the volt-second clamp provides VOUT regulation for open-loop conditions such as no opto-coupler,
reference or error amplifier on the secondary side.
For applications not requiring isolation but requiring high
step-down ratios, each IC contains a voltage error amplifier to allow a very simple nonisolated, fully regulated
synchronous forward converter.
The integrated housekeeping controller reduces the complexity and size of the main power transformer by avoiding the need for extra windings to create bias supplies.
Secondary side ICs no longer require start-up circuitry
and can operate even when output voltage is 0V.
A range of protection features include programmable
overcurrent (OC) hiccup mode, programmable system
input undervoltage lockout (UVLO), programmable
system input overvoltage lockout (OVLO) and built-in
thermal shutdown. Programmable slope compensation
and switching frequency allow the use of a wide range of
output inductor values and transformer sizes.
If secondary side control already exists for soft starting
the converter output voltage then the SS2 pin can still be
used to control initial inductor peak current rise. Simply
programming the primary side SS2 soft-start faster than
the secondary side allows the secondary side to take over.
If SS2 is not needed for soft-start control, its pull-down
strength and voltage rating also allow it to drive the input
of an opto-coupler connected to INTVCC. This allows
the option of communicating to the secondary side that
switching has begun.
LT3752-1 Part Start-Up
The LT3752-1 start-up of housekeeping supply and forward
converter are similar to the LT3752 except for a small
change in architecture and VIN pin level. LT3752‑1 start-up
is best described by referring to the Block Diagram and to
Rev. C
For more information www.analog.com
19
LT3752/LT3752-1
OPERATION
the start-up waveforms in Figure 4. The LT3752-1 starts
up by using a high valued resistor from system input to
charge up the input capacitor at the VIN pin. If system
input is already high enough to generate UVLO_VSEC
above 1.25V, then the part turns on once VIN pin charges
past VIN(ON) (9.5V). If system input is not high enough
to generate UVLO_VSEC above 1.25V, the VIN pin charges
towards system input until it reaches an internal 16V, 8mA
clamp. The part turns on when system input becomes
high enough to generate UVLO_VSEC above 1.25V. As the
supply current of the part discharges the VIN capacitor a
bootstrap supply must be generated to prevent VIN pin
from falling below VIN(OFF) (7.6V).
The LT3752-1 uses the housekeeping controller to provide
the bootstrap bias to the VIN pin during RC start-up instead
of waiting for the forward converter to also start. This method is more efficient, requires a smaller VIN input capacitor
and avoids the need for an auxiliary winding in the main
transformer. The part’s low start-up current at the VIN pin
allows the use of a large start-up resistor to minimize power
loss from system input. The VIN capacitor value required for
proper start-up is minimized by providing a large VIN(ON)VIN(OFF) hysteresis, a low VIN IQ and a fast start-up time for
the housekeeping controller. In contrast to the LT3752, the
LT3752-1 housekeeping gate driver (HOUT) runs from the
VIN pin instead of INTVCC. This avoids having to use current from the VIN pin to charge the INTVCC capacitor during
initial start-up. This means the regulated 10V INTVCC on the
LT3752-1 does not wake up until the housekeeping supply
is valid. Start-up from this point is similar to the LT3752.
The housekeeping supply and forward converter switch
together with a soft-started frequency and volt-second
clamp. The forward converter peak inductor current is also
soft started similar to the LT3752.
Rev. C
20
For more information www.analog.com
LT3752/LT3752-1
APPLICATIONS INFORMATION
Programming System Input Undervoltage Lockout
(UVLO) Threshold and Hysteresis
The LT3752/LT3752-1 have an accurate 1.25V shutdown
threshold at the UVLO_VSEC pin. This threshold can be
used in conjunction with an external resistor divider to
define the falling undervoltage lockout threshold (UVLO(–))
for the converter’s system input voltage (VS) (Figure 5).
A pin hysteresis current of 5µA allows programming of
the UVLO(+) threshold.
used to pull down the UVLO_VSEC pin below 1.25V but not
below the micropower shutdown threshold of 0.6V(max).
Typical VIN quiescent current after soft-stop is 165µA.
Micropower Shutdown
VS (UVLO(–)) [begin SOFT-STOP then shut down]
If a micropower shutdown is required using an external
control signal, an open-drain transistor can be directly
connected to the UVLO_VSEC pin. The LT3752/LT3752‑1
have a micropower shutdown threshold of typically 0.4V at
the UVLO_VSEC pin. VIN quiescent current in micropower
shutdown is 20µA.
⎡ ⎛ R1 ⎞ ⎤
= 1.25 ⎢ 1+ ⎜
⎟⎥
⎣ ⎝ R2 + R3 ⎠ ⎦
Programming System Input Overvoltage Lockout
(OVLO) Threshold
VS (UVLO(+)) [begin SOFT-START]
= VS (UVLO(–)) + (5µA • R1)
It is important to note that the part enters soft-stop when
the UVLO_VSEC pin falls back below 1.25V. During softstop the converter continues to switch as it folds back
switching frequency, volt-second clamp and COMP pin
voltage. See Soft-Stop in the Applications Information
section. When the SS2 pin is finally discharged below its
150mV reset threshold both the housekeeping supply and
forward converter are shut down.
SYSTEM
INPUT (VS)
LT3752/LT3752-1
R1
UVLO_VSEC
VS OVLO(+) [stop switching; HARD STOP]
5µA
R2
R3
–
TO
OVLO PIN
1.250V
The LT3752/LT3752-1 have an accurate 1.25V overvoltage
shutdown threshold at the OVLO pin. This threshold can
be used in conjunction with an external resistor divider to
define the rising overvoltage lockout threshold (OVLO(+))
for the converter’s system input voltage (VS) (Figure 6).
When OVLO(+) is reached, the part stops switching immediately and a hard stop discharges the SS1 and SS2
pins. The falling threshold OVLO(–) is fixed internally at
1.215V and allows the part to restart in soft-start mode.
A single resistor divider can be used from system input
supply (VS) to define both the undervoltage and overvoltage thresholds for the system. Minimum value for R3 is
1k. If OVLO is unused, place a 10k resistor from OVLO
pin to ground.
+
⎡ ⎛ R1+ R2 ⎞ ⎤
= 1.25 ⎢ 1+ ⎜
⎟⎥
⎣ ⎝ R3 ⎠ ⎦
VS OVLO(–) [begin SOFT-START]
3752 F05
Figure 5. Programming Undervoltage Lockout (UVLO)
= VS OVLO ( + ) •
1.215
1.25
Soft-Stop Shutdown
Soft-stop shutdown (similar to system undervoltage) can
be commanded by an external control signal. A MOSFET
with a diode (or diodes) in series with the drain should be
Rev. C
For more information www.analog.com
21
LT3752/LT3752-1
APPLICATIONS INFORMATION
SYSTEM
INPUT (VS)
R1
R2
SYSTEM
INPUT (VS)
LT3752/LT3752-1
RSTART
TO
UVLO_VSEC
PIN
1.250V(+)
1.215V(–)
OVLO
+
VHK (HOUSEKEEPING SUPPLY OUTPUT)
LT3752-1
16V
VIN
CSTART
8mA
+
OVLO
–
R3
1.250V
–
3752 F06
GND
Figure 6. Programming Overvoltage Lockout (OVLO)
3752 F07
LT3752-1 Micropower Start-Up from High System
Input Voltages
Figure 7. Micropower Start-Up from High System Input
The LT3752-1 starts up from system input voltage levels
limited only by external components (Figure 7). The low
start-up current of the LT3752-1 allows a large start-up
resistor (RSTART) to be connected from system input voltage (VS) to the VIN pin.
The start-up capacitor can be calculated as:
When system input voltage is applied, the start-up capacitor
(CSTART) begins charging at the VIN pin. Once the VIN pin
exceeds 9.5V (and UVLO_VSEC > 1.25V) the housekeeping
controller will start to switch and VIN supply current will
begin to discharge CSTART. The CSTART capacitor value
should be chosen high enough to prevent the VIN pin
from falling below 7.6V before the housekeeping supply
can provide a bootstrap bias to the VIN pin. The LT3752‑1
start-up architecture minimizes the value of CSTART by
activating only the house keeping controller for providing drive back to the VIN pin. The forward controller only
operates once the housekeeping supply is established. (If
a bootstrap diode is used from the housekeeping supply
back to INTVCC, this only uses current from system input
and not from the VIN pin).
IHKEEP = Housekeeping IQ (not switching)
IDRIVE = (fOSC/2.13) • QG)
fOSC = full-scale controller switching frequency
QG = gate charge (VGS = VIN)(HOUT MOSFET)
tHSS = housekeeping output voltage soft-start time
VDROOP = 16V(clamp) – VIN(OFF) or VIN(ONOFFHYST)
C START(MIN) = (IHKEEP + IDRIVE ) (MAX ), •
t HSS(MAX)
VDROOP(MIN)
where:
The start-up resistor can be calculated as:
R START(MAX) =
VS(MAX) – VIN(ON)(MAX)
ISTART(MAX) • k
where:
VS(MAX) = Maximum system input voltage
VIN(ON)(MAX) = Maximum VIN pin turn on threshold
ISTART(MAX) = Maximum VIN IQ for part start-up
k > 1.0 reduces RSTART and VIN charge-up time
Rev. C
22
For more information www.analog.com
LT3752/LT3752-1
APPLICATIONS INFORMATION
Worst-case values should be used to calculate the CSTART
and RSTART required to guarantee start-up and to turn on
in the time required.
Example: (LT3752-1)
For VS(MIN) = 75V, VIN(ON)(MAX) = 10.4V
ISTART(MAX) = 265µA, IHKEEP(MAX) = 4.6mA
QG = 8nC (at VIN = 10V), fOSC = 150kHz
tHSS(MAX) = 4ms, VDROOP(MIN) = 1.61V
C START(MIN) = ( 4.6mA + 71kHz • 8nC ) •
75V – 10.4V
265µA • k
X = (109/fOSC) – 365
Y = (300kHz – fOSC)/107 (fOSC < 300kHz)
Y = (fOSC – 300kHz)/107 (fOSC > 300kHz)
Example: For fOSC = 200kHz,
RT = 8.39 • 4635 • (1 + 0.01) = 39.28k (choose 39.2k)
4ms
1.61V
= 12.8µF ( Choose 14.7µF )
R START(MAX) =
where,
= 243k ( for k = 1.0 )
The LT3752/LT3752-1 include frequency foldback at startup (see Figures 3 and 4). In order to make sure that a
SYNC input does not override frequency foldback during
start-up, the SYNC function is ignored until SS1 pin reaches
2.2V. Both the housekeeping and forward controllers run
synchronized to each other and in phase, with or without
the SYNC input.
Table 1. RT vs Switching Frequency (fOSC)
SWITCHING FREQUENCY (kHz)
RT (kΩ)
The RSTART(MAX) value should be chosen with higher k
values until the charge-up time for CSTART is acceptable.
In most cases, CSTART will be charged to the 16V clamp
on the LT3752-1 VIN pin before system input reaches its
UVLO(+) threshold (Figure 4). This will allow an extra
5.6V for VDROOP in the CSTART equation, allowing a smaller
CSTART value and hence a faster start-up time.
100
82.5
150
53.6
200
39.2
250
30.9
300
24.9
The trade-off of lower RSTART is greater power dissipation, given by:
PRSTART = (VS – VIN)2/RSTART
for RSTART = 200k, VS(MAX) = 150V, VIN = 10V (back
driven from housekeeping supply)
PRSTART = (150 – 10)2/200k = 98mW.
Programming Switching Frequency
The switching frequency for the housekeeping supply
and the main forward converter are programmed using a
resistor, RT, connected from analog ground (Pin 18) to the
RT pin. Table 1 shows typical fOSC vs RT resistor values.
The value for RT is given by:
RT = 8.39 • X • (1 + Y)
350
21
400
18.2
450
15.8
500
14
Synchronizing to an External Clock
The LT3752 / LT3752-1 internal oscillator can be synchronized to an external clock at the SYNC pin. SYNC pin high
level should exceed 1.8V for at least 100ns and SYNC
pin low level should fall below 0.6V for at least 100ns.
The SYNC pin frequency should be set equal to or higher
than the typical frequency programmed by the RT pin.
An fSYNC/fOSC ratio of x (1.0 < x < 1.25) will reduce the
externally programmed slope compensation by a factor
of 1.2x. If required, the external resistor RISLP can be
reprogrammed higher by a factor of 1.2x. (see Current
Sensing and Programmable Slope Compensation).
Rev. C
For more information www.analog.com
23
LT3752/LT3752-1
APPLICATIONS INFORMATION
The part injection locks the internal oscillator to every rising edge of the SYNC pin. If the SYNC input is removed
at any time during normal operation the part will simply
change switching frequency back to the oscillator frequency
programmed by the RT resistor. This injection lock method
avoids the possible issues from a PLL method which can
potentially cause a large drop in frequency if SYNC input
is removed.
During soft-start the SYNC input is ignored until SS1 exceeds 2.2V. During soft-stop the SYNC input is completely
ignored. If the SYNC input is to be used, recall that the
programmable duty cycle clamp DVSEC is dependent on the
switching frequency of the part (see section Programming
Duty Cycle Clamp). RIVSEC should be reprogrammed by
1/x for an fSYNC/fOSC ratio of x.
INTVCC Regulator Bypassing and Operation
The INTVCC pin is the output of an internal linear regulator driven from VIN and provides the supply for onboard
gate drivers. The LT3752 INTVCC provides a regulated 7V
supply for gate drivers AOUT, SOUT, OUT and HOUT. The
LT3752-1 INTVCC provides a regulated 10V supply for gate
drivers AOUT, SOUT and OUT. INTVCC should be bypassed
with a 4.7µF low ESR, X7R or X5R ceramic capacitor to
power ground to ensure stability and to provide enough
charge for the gate drivers.
The INTVCC regulator has a minimum 35mA output current limit. This current limit should be considered when
choosing the switching frequency and capacitance loading
on each gate driver. Average current load on the INTVCC
pin for a single gate driver driving an external MOSFET
is given as :
IINTVCC = fOSC • QG
be externally overdriven by the housekeeping supply to
improve efficiency, remove power dissipation from within
the IC and provide more than 35mA output current capability. Any overdrive level should exceed the regulated
INTVCC level but not exceed 16V.
In the case of a short-circuit fault from INTVCC to ground,
each IC reduces the INTVCC output current limit to typically
23mA. The INTVCC regulator has an undervoltage lockout
rising threshold, UVLO(+), which prevents gate driver
switching until INTVCC reaches 4.75V (7V for LT3752-1)
and maintains switching until INTVCC falls below a UVLO(–)
threshold of 4.6V (6.8V for LT3752-1).
For VIN levels close to or below the INTVCC regulated level,
the INTVCC linear regulator may enter dropout. The resulting lower INTVCC level will still allow gate driver switching
as long as INTVCC remains above INTVCC UVLO(–) levels.
See the Typical Performance Characteristics section for
INTVCC performance vs VIN and load current.
HOUSEKEEPING CONTROLLER
The LT3752/LT3752-1 include an internal constant frequency, current mode, PWM controller for creating a
housekeeping supply (see the Block Diagram and Figure 8).
Connected as a flyback converter with multiple outputs,
the housekeeping supply is able to efficiently provide bias
to both primary and secondary ICs. It eliminates the need
to generate bias supplies from auxiliary windings in the
main forward transformer, reducing the complexity, size
and cost of the transformer.
VIN
•
•
VIN
INTVCC
where:
HOUT
INTVCC
LTC3752/LT3752-1
fOSC = controller switching frequency
QG = gate charge (VGS = INTVCC)
HCOMP
HISENSE
GND
While the INTVCC 50mA output current limit is sufficient
for LT3752/LT3752-1 applications, efficiency and internal
power dissipation should also be considered. INTVCC can
VAUX*
RHISLP
•
INTVCC
HFB
RHSENSE
R2
R1
VHK
*OPTIONAL ISOLATED SUPPLY FOR SECONDARY SIDE
3752 F08
Figure 8. Housekeeping Supply
Rev. C
24
For more information www.analog.com
LT3752/LT3752-1
APPLICATIONS INFORMATION
Integrating the housekeeping controller saves cost and
space and allows switching frequency to be inherently
synchronized to the main forward converter.
to achieve regulation. The housekeeping controller is shut
down and the internal soft-start capacitor is discharged
for any of the following conditions (typical values):
The housekeeping supply can be used to overdrive the
INTVCC pin to take power outside of the part, improve
efficiency, provide more drive current and optimize the
INTVCC level. It can also be used as a bootstrap bias to
the VIN pin as described in the section LT3752-1 Part
Start-Up. The housekeeping supply also allows bias to
any secondary side IC before the main forward converter
starts switching. This removes the need for external startup circuitry on the secondary side. Alternative methods
involve powering secondary side ICs directly from the
output voltage of the forward converter. This can cause
issues depending on the minimum and maximum allowed
input voltages for each IC.
(1) UVLO_VSEC < 1.25V
(and SS1 < 0.15V)
:Soft-Stop Shutdown
(2) UVLO_VSEC < 0.4V :Micropower Shutdown
(3) OVLO > 1.250V
:System Input OVLO
:Housekeeping Overcurrent
(4) HISENSE > 98mV
(5) INTVCC < X, > 16.5V :INTVCC UVLO, OVLO
:Thermal Shutdown
(6) TJ > 170°C
:VIN Pin UVLO
(7) VIN < Y
(X = 4.6V, Y = 5.5V for LT3752)
(X = 6.8V, Y = 7.6V for LT3752-1)
Housekeeping: Operation
The output voltage, VHK, of the housekeeping controller
is programmed using a resistor divider between VHK and
the HFB pin (Figure 8) using the equation:
The LT3752/LT3752-1 housekeeping controller operation is best described by referring to the Block Diagram
and Figure 8. The housekeeping controller uses a ±0.7A
gate driver at HOUT to control an external N-channel
MOSFET. When current in the primary winding of the flyback
transformer exceeds a level commanded by HCOMP and
sensed at the HISENSE pin, the duty cycle of the HOUT is
terminated. Stored energy in the transformer is delivered
to the output during the off time of HOUT. The housekeeping output voltage is programmed using a resistor divider
to the HFB pin. A transconductance amplifier monitors
the error signal between HFB pin and a 1.0V reference to
control HCOMP level and hence peak switch current. A
simple RC network from HCOMP pin to ground provides
compensation. Overcurrent protection exists for the external switch when 98mV is sensed at the HISENSE pin. This
causes a low power hiccup mode (repeated retry cycles’
of shutdown followed by soft-start) until the overcurrent
condition is removed.
Housekeeping: Soft-Start/Shutdown
During start-up of the LT3752/LT3752-1, the housekeeping
controller has a built-in soft-start of approximately 2.2ms.
The time will vary depending on the HCOMP level needed
Housekeeping: Programming Output Voltage
R1
VHK = 1V • 1+
R2
The HFB pin bias current is typically 85nA.
Housekeeping: Programming Cycle-by-Cycle Peak
Inductor Current and Slope Compensation
The housekeeping controller limits cycle-by-cycle peak
current in the external switch and primary winding of
the flyback transformer by sensing voltage at a resistor
(RHISENSE) connected in the source of the external N‑channel MOSFET (Figure 8). This sense voltage is compared to
a sense threshold at the HISENSE pin, controlled by HCOMP
with an upper limit of 79mV. Since there is only one sense
line from the positive terminal of the sense resistor, any
parasitic resistance in ground side will increase its effective value and reduce available peak switch current. For
operation in continuous mode and above 50% duty cycle,
required slope compensation can be programmed by
adding a resistor RHISLP in series with the HISENSE pin. A
ramped current always flows out of the HISENSE pin. The
current starts from 2µA at 0% duty cycle and ramps to
52µA at 100% duty cycle. Minimize capacitance on this pin.
Rev. C
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25
LT3752/LT3752-1
APPLICATIONS INFORMATION
For a desired peak switch current, the value for RHISENSE
should be calculated using a 30% derated 79mV sense
threshold with the effects of slope compensation included:
R HSENSE =
52.5mV – ∆VHSLP
hiccup mode over current level in the switch and primary
winding is given by:
I LP(PEAK)
ILP(OVERCURRENT) =
98mV – ∆ V HSLP
R HSENSE
where:
where:
∆VHSLP = (2µA + D • (62.5µA) • RHISLP)
ILP(PEAK) = cycle-by-cycle peak current in primary
winding
D = switch duty cycle
RHISLP = slope compensation programming resistor
If operating in continuous mode above 50% duty cycle,
a good starting value for RHISLP is 499Ω which gives a
26mV total drop in current comparator threshold at 80%
duty cycle. An fSYNC/fOSC ratio of x (1.0V < x < 1.25) will
reduce the externally programmed slope compensation by
a factor of 1.2x. If required, the external resistor RHISLP
can be reprogrammed higher by a factor of 1.2x.
Housekeeping: Adaptive Leading Edge Blanking
Blanking of the HISENSE signal on the leading edge of
HOUT is adaptive to allow a wide range of MOSFETs. The
blanking occurs from the start of HOUT rise and waits
until HOUT has reached within 1V of its maximum level
(INTVCC for LT3752, VIN for LT3752-1) before adding an
additional fixed 100ns of blanking.
Housekeeping: Overcurrent Hiccup Mode
To protect the housekeeping controller during a shortto-ground fault on the housekeeping output voltage, a
98mV fixed overcurrent threshold exists at the HISENSE
pin to discharge the internal soft-start capacitor and enter
a hiccup (retry) mode. This hiccup mode significantly
reduces the average power in the external components
compared to continued cycle-by-cycle switching at the
79mV threshold. Having already calculated the RHSENSE
resistor for peak cycle-by-cycle current, the typical
∆VHSLP = (2µA + D • (62.5µA) • RHISLP)
D = switch duty cycle
RHISLP = slope compensation programming resistor
RHSENSE = current sense resistor
Housekeeping: Output Overvoltage and Power Good
The housekeeping controller monitors its supplies’ rising output voltage VHK via the HFB pin and determines
power good (PGOOD(+)) when VHK reaches 96% of its
programmed value. 10µs after confirmation of PGOOD,
the circuitry for the LT3752/LT3752-1 forward controller
is activated.
The SS1 pin is allowed to begin charging and eventually
allows the forward converter to start switching. If VHK
falls below 92% of its programmed level (PGOOD(–)),
the SS1 pin is discharged and forward controller circuitry
is disabled.
To limit housekeeping output overvoltage, VHK, the housekeeping controller overrides it’s own regulation loop and
immediately stops switching if its output voltage exceeds
20% of its programmed value. This is especially important when using the housekeeping supply to bias other
ICs. The forward controller is still allowed to switch. The
housekeeping controller returns to normal regulation loop
control when it’s output voltage, VHK, falls to less than
15% above it’s programmed value.
Housekeeping: Transformer Turns Ratio and Leakage
Inductance
The external resistor divider used to set the output voltage
of the housekeeping supply provides a relative freedom
in selecting the transformer turns ratio to suit a given
Rev. C
26
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LT3752/LT3752-1
APPLICATIONS INFORMATION
application. Simple integer turns ratios can be used which
allow off-the-shelf transformers (see example circuits in the
Typical Applications section). Turns ratios can be chosen
on the basis of desired duty cycle. However, the input and
output levels, turns ratio and flyback leakage spike must
be considered for the breakdown rating of the MOSFET.
Transformer leakage inductance causes a voltage spike to
occur after the switch turns off. In some cases a snubber
circuit will be required to limit this spike.
Housekeeping: Operating Without This Supply
The housekeeping supply is highly recommended for
providing local bias voltages for both the primary and
secondary sides (to improve efficiency, simplify the main
transformer design and ensure all ICs are activated even
for VOUT = 0V). The LT3752 (not LT3752-1) housekeeping
supply components can be omitted (not populated) if an
extra winding already exists from the main transformer
to create an auxiliary supply. Care must be taken that the
auxiliary supply (for either the primary side or secondary
side or both) does not affect proper operation. A resistor
divider (Figure 8) should now be connected directly from
INTVCC to supply the HFB pin with a ratio :
be used in a fully regulated forward converter application.
In addition, they can still operate if damage occurs to
the feedback path—no secondary side error amplifier or
opto-coupler—by using an accurate, programmable voltsecond clamp to regulate duty cycle inversely proportional
to transformer input voltage.
Adaptive Leading Edge Blanking Plus Programmable
Extended Blanking
The LT3752/LT3752-1 provide a ±2A gate driver at the
OUT pin to control an external N-channel MOSFET for
main power delivery in the forward converter (Figure 10).
During gate rise time and sometime thereafter, noise can
be generated in the current sensing resistor connected
to the source of the MOSFET. This noise can potentially
cause a false trip of sensing comparators resulting in
early switch turn off and in some cases re-soft-start of
the system. To prevent this, LT3752/LT3752-1 provide
adaptive leading edge blanking of both OC and ISENSEP
signals to allow a wide range of MOSFET QG ratings. In
addition, a resistor RTBLNK connected from TBLNK pin to
analog ground (Pin 18) programs an extended blanking
duration (Figure 9).
R1/R2 = 3
(ADAPTIVE)
LEADING
EDGE
BLANKING
(Example : R1 = 10k, R2 = 3.32k).
This ratio ensures HFB >> 0.96V (typical PGOOD level to
enable SS1 and the forward converter).
(a) At INTVCC = 4.75V (UVLO(+)), HFB = 1.2V.
(b) At INTVCC = 7V (Regulated), HFB = 1.7V.
(PROGRAMMABLE)
EXTENDED
BLANKING
7.32k ≤ RTBLNK ≤ 249k
OUT
tBLNK = 50ns + (2.2ns • RTBLNK)
k
(c) At INTVCC = 8V (Overdriven), HFB = 2V.
CURRENT
SENSE
DELAY
220ns
3752 F09
Care should be taken not to exceed HFB = 3V.
Figure 9. Adaptive Leading Edge Blanking Plus
Programmable Extended Blanking
FORWARD CONTROLLER
The LT3752/LT3752-1 are primary side, current mode,
PWM controllers optimized for use in a synchronous
forward converter with active clamp reset. Each IC can
Rev. C
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27
LT3752/LT3752-1
APPLICATIONS INFORMATION
Adaptive leading edge blanking occurs from the start of
OUT rise and completes when OUT reaches within 1V of
its maximum level (INTVCC for LT3752, VIN for LT3752-1).
An extended blanking then occurs which is programmable
using the RTBLNK resistor given by:
tBLNK
2.2ns
= 50ns +
• RTBLNK ,
k
connected in the source of the external n-channel MOSFET
(Figure 10).
VIN
•
•
VOUT
VIN
INTVCC
M1
OUT
INTVCC
LTC3752/LT3752-1
7.32k < RTBLNK < 249k
Adaptive leading edge blanking minimizes the value required for RTBLNK. Increasing RTBLNK further than required
increases M1 minimum on time (Figure 10).
In addition, the critical volt-second clamp (DVSEC) is not
blanked. Therefore, if DVSEC decreases far enough (in soft
start foldback and at maximum input voltage) M1 may turn
off before blanking has completed. Since OC and ISENSEP
signals are only seen when M1 is on (and after blanking
has completed), RTBLNK value should be limited by:
(2.2ns/k)RTBLNK < TVSEC(MIN) – tADAPTIVE – 50ns
where,
TVSEC(MIN) = 109(DVSEC (MAX) /(fold.fosc))
(Input(MIN)/Input(MAX))
fold = fOSC and DVSEC foldback ratio (for OUT pin)
( = 4 for LT3752 , = 2 for LT3752-1)
tADAPTIVE = OUT pin rise time to INTVCC – 1V
Example: For Figure 20 circuit, DVSEC(MAX) = 0.77,
Input(MIN)/(MAX) = 17.4V/74V, fold = 4, tADAPTIVE = 23ns
and fOSC = 240kHz,
TVSEC(MIN) = 109(0.77/(4 • 2.4 • 105)) • 17.4/74 = 188ns
(2.2ns/1k)RTBLNK < 188 – 23 – 50
RTBLNK < 52.5k (Actual Circuit Uses 34k)
Current Sensing and Programmable Slope
Compensation
FROM
REGULATION
LOOP
OC
ISENSEP
COMP
GND
RISLP
RSENSE
ISENSEN
3752 F10
Figure 10. Current Sensing and Programmable
Slope Compensation
The sense voltage across RSENSE is compared to a sense
threshold at the ISENSEP pin, controlled by COMP pin level.
Two sense inputs, ISENSEP and ISENSEN, are provided to
allow a Kelvin connection to RSENSE. For operation in continuous mode and above 50% duty cycle, required slope
compensation can be programmed by adding a resistor,
RISLP, in series with the ISENSEP pin. A ramped current
always flows out of the ISENSE pin. The current starts from
2µA at 0% duty cycle and linearly ramps to 33µA at 80%
duty cycle. A good starting value for RISLP is 1.5kΩ which
gives a 41mV total drop in current comparator threshold
at 65% duty cycle.
The COMP pin commands an ISENSEP threshold between
0mV and 220mV. The 220mV allows a large slope compensation voltage drop to exist in RISLP without effecting
the programming of RSENSE to set maximum operational
currents in M1. An fSYNC/fOSC ratio of x (1.0 < x < 1.25)
will reduce the externally programmed slope compensation by a factor of 1.2x. If required, the external resistor
RISLP can be reprogrammed higher by a factor of 1.2x.
Overcurrent: Hiccup Mode
The LT3752/LT3752-1 command cycle-by-cycle peak
current in the external switch and primary winding of the
forward transformer by sensing voltage across a resistor
The LT3752/LT3752-1 use a precise 96mV sense threshold at the OC pin to detect excessive peak switch current
(Figure 10). During an overload condition switching
Rev. C
28
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LT3752/LT3752-1
APPLICATIONS INFORMATION
stops immediately and the SS1/SS2 pins are rapidly
discharged. The absence of switching reduces the sense
voltage at the OC pin, allowing SS1/SS2 pins to recharge
and eventually attempt switching again. The part exists
in this hiccup mode as long as the overcurrent condition
exists. This protects the converter and reduces power
dissipation in the components (see Hard Stop in the
Applications Information section). The 96mV peak switch
current threshold is independent of the voltage drop in
RISLP used for slope compensation.
t
tON_VSEC
OUT
3752 F11
Figure 11. Volt-Second (DVSEC) Clamp
SYSTEM
INPUT
LOAD(OVERCURRENT)
(
(PROGRAMMED
BY RIVSEC)
DVSEC = tON_VSEC/t
DVSEC = “DUTY CYCLE GUARDRAIL”
Output DC load current to trigger hiccup mode:
N
96mV
= P •
– 1/2 IRIPPLE(P-P)
NS RISENSE
tON
D = tON/t
R1
)
UVLO_VSEC
R2
R3
where:
NP = forward transformer primary turns
TO
OVLO
PIN
LT3752/LT3752-1
IVSEC
RT
RIVSEC
NS = forward transformer secondary turns
RT
3752 F12
IRIPPLE(P-P) = Output inductor peak-to-peak ripple
current
Figure 12. Programming DVSEC
RISENSE should be programmed to allow maximum DC load
current for the application plus enough margin during load
transients to avoid overcurrent hiccup mode.
A resistor RIVSEC from the IVSEC pin to analog ground
(Pin 18) programs DVSEC.
Programming Maximum Duty Cycle Clamp: DVSEC
(Volt-Second Clamp)
R
f
1.25
= 0.725 • IVSEC • OSC •
51.1k 300 UVLO_VSEC
Unlike other converters which only provide a fixed maximum duty cycle clamp, the LT3752/LT3752-1 provide an
accurate programmable maximum duty cycle clamp
(DVSEC) on the OUT pin which moves inversely with
system input. DVSEC provides a duty cycle guardrail to
limit the volt-seconds-on product over the entire natural
duty cycle range (Figures 11 and 12). This limits the
drain voltage required for complete transformer reset.
DVSEC (OUT pin duty cycle clamp)
where:
RIVSEC = programming resistor at IVSEC pin
fOSC = switching frequency (kHz)
UVLO_VSEC = resistor divided system input voltage
RIVSEC can program any DVSEC required at minimum
system input. DVSEC will then follow natural duty cycle
as VIN varies. Maximum programmable DVSEC is typi-
Rev. C
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29
LT3752/LT3752-1
APPLICATIONS INFORMATION
cally 0.75 but may be further limited by the transformer
design and voltage ratings of components connected to
the drain of the primary side power MOSFET (SWP). See
voltage calculations in the LO side and HI side active clamp
topologies sections.
If system input voltage falls below it's UVLO threshold
the part will enter soft-stop with continued switching.
The LT3752/LT3752-1 include an intelligent circuit which
prevents DVSEC from continuing to rise as system input
voltage falls (see Soft-Stop). Without this, too large a DVSEC
would require extremely high reset voltages on the SWP
node to properly reset the transformer. The UVLO_VSEC
pin maximum operational level is the lesser of VIN – 2V
or 12.5V.
The LT3752/LT3752-1 volt-second clamp architecture
is superior to an external RC network connected from
system input to trip an internal comparator threshold.
The RC method suffers from external capacitor error, partto-part mismatch between the RC time constant and the
IC’s switching period, the error of the internal comparator
threshold and the nonlinearity of charging at low input
voltages. The LT3752/LT3752-1 use the RIVSEC resistor to
define the charge current for an internal timer capacitor to
set an OUT pin maximum on-time, tON(VSEC). The voltage
across RIVSEC follows UVLO_VSEC pin voltage (divided
down from system input voltage). Hence, RIVSEC current
varies linearly with input supply. The LT3752/LT3752-1
also trim out internal timing capacitor and comparator
threshold errors to optimize part-to-part matching between
tON(VSEC) and T.
DVSEC Open Loop Control: No Opto-Coupler, Error
Amplifier or Reference
secondary side. DVSEC controls the output of the converter
by controlling duty cycle inversely proportional to system
input. If DVSEC duty cycle guardrail is programmed X%
above natural duty cycle, VOUT will only increase by X%
if a closed loop system breaks open. This volt-second
clamp is operational over a 10:1 system input voltage
range. See DVSEC versus UVLO_VSEC pin voltage in the
Typical Performance Characteristics section.
RIVSEC: Open Pin Detection Provides Safety
The LT3752/LT3752-1 provide an open-detection safety
feature for the RIVSEC pin. If the RIVSEC resistor goes
open circuit the part immediately stops switching. This
prevents the part from running without the volt-second
clamp in place.
Transformer Reset: Active Clamp Technique
The LT3752/LT3752-1 include a ±0.4A gate driver at the
AOUT pin to allow the use of an active clamp transformer
reset technique (Figures 13, 17). The active clamp method
improves efficiency and reduces voltage stress on the
main power switch, M1. By switching in the active clamp
capacitor only when needed, the capacitor does not lose
its charge during M1 on-time. By allowing the active clamp
capacitor, CCL, to store the average voltage required to
reset the transformer, the main power switch sees lower
drain voltage.
An imbalance of volt-seconds will cause magnetizing current to walk upwards or downwards until the active clamp
capacitor is charged to the optimal voltage for proper
transformer reset. The voltage rating of the capacitor will
depend on whether the active clamp capacitor is actively
switched to ground (Figure 13) or actively switched to
The accuracy of the programmable volt-second clamp
(DVSEC) safely controls VOUT if open loop conditions exist
such as no opto-coupler, error amplifier or reference on the
Rev. C
30
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LT3752/LT3752-1
APPLICATIONS INFORMATION
LLEAK
VIN
LMAG
•
CSW
VOUT
•
FSW
LLEAK
SWP
OUT
LT3752
AOUT
M1
CCL
C1
M2
R1
LTXXXX
VD
M3
FG
CG
M4
D1
–VIN
3752 F13
–VOUT
Figure 13. LO Side Active Clamp Topology
IMAG
1A/DIV
SWP
50V/DIV
3752 F14
20µs/DIV
Figure 14. Active Clamp Reset: Magnetizing Current and M1 Drain Voltage
system input (Figure 17). In an active clamp reset topology, volt-second balance requires:
ACTIVE CLAMP CAPACITOR VOLTAGE
NORMALIZED TO 50% DUTY CYCLE
1.6
1.5
LO SIDE ACTIVE CLAMP TOPOLOGY
1.4
VIN • D = (SWP – VIN) • (1 – D)
where:
1.3
1.2
1.1
1.0
0.9
20
30
60
50
40
DUTY CYCLE (%)
80
70
3752 F15
VIN = Transformer input supply
D = (VOUT/VIN) • N = switch M1 duty cycle
VOUT = Output voltage (including the voltage drop
contribution of M4 catch diode during M1 off)
N = Transformer turns ratio = NP/NS
SWP = M1 drain voltage
Figure 15. LO Side VCCL vs Duty Cycle
(Normalized to 50% Duty Cycle)
Rev. C
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LT3752/LT3752-1
APPLICATIONS INFORMATION
LO Side Active Clamp Topology (LT3752)
During load transients, duty cycle and hence VCCL may
increase. Replace D with DVSEC in the equation above to
calculate transient VCCL values. See the previous section
Programming Duty Cycle Clamp–DVSEC. The DVSEC guardrail can be programmed as close as 5% higher than D but
may require a larger margin to improve transient response.
The steady-state active clamp capacitor voltage, VCCL,
required to reset the transformer in a LO side active clamp
topology (Figure 13) can be approximated as the drain-tosource voltage (VDS) of switch M1, given by:
VCCL (LO side):
As shown in Figure 15, the maximum steady-state value
for VCCL may occur at minimum or maximum input voltage. Hence VCCL should be calculated at both input voltage
levels and the largest of the two calculations used. M1
drain should be rated for a voltage greater than the above
steady-state VDS calculation due to tolerances in duty
cycle, load transients, voltage ripple on CCL and leakage
inductance spikes. CCL should be rated higher due to the
effect of voltage coefficient on capacitance value. A typical
choice for CCL is a good quality X7R capacitor. M2 should
have a VDS rating greater than VCCL since the bottom plate
of CCL is –VCCL during M1 on and M2 off. For high input
voltage applications, the limited VDS rating of available
P-channel MOSFETs might require changing from a LO
side to HI side active clamp topology.
(a) Steady state: VCCL = SWP = VDS
=
VIN2
1
• VIN =
1– D
( VIN – ( VOUT • N)
)
(b) Transient:
ACTIVE CLAMP CAPACITOR VOLTAGE
NORMALIZED TO 50% DUTY CYCLE
2.5
2.3
HI SIDE ACTIVE CLAMP TOPOLOGY
2.0
1.8
1.5
1.3
For the lo side active clamp topology in steady state, during
M1 on time, magnetizing current (IMAG) increases from a
negative value to a positive value (Figure 14). When M1
turns off, magnetizing current charges SWP until it reaches
VCCL plus the voltage drop of the M2 body diode. At this
1.0
0.8
0.5
20
30
40
50
60
70
80
DUTY CYCLE (%)
3752 F16
Figure 16. HI Side VCCL vs Duty Cycle
(Normalized to 50% Duty Cycle)
LLEAK
VIN
C2
T4
•
•
LMAG
CCL
C1
M2
R1
D1
•
VOUT
FSW
VD
LLEAK
LTXXXX
SWP
AOUT
CSW
•
–VIN
M3
FG
CG
M4
LT3752-1
OUT
M1
–VIN
3752 F17
–VOUT
Figure 17. HI Side Active Clamp Topology
Rev. C
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LT3752/LT3752-1
APPLICATIONS INFORMATION
moment the active clamp capacitor is passively switched
in to ground (due to the forward conduction of M2 body
diode) and the drain voltage increases at a slower rate
due to the loading of CCL. SWP above VIN causes IMAG
to reduce from a positive value towards zero (dVSWP/dT
= 0). As IMAG becomes negative it begins to discharge
the SWP node. Switching in M2 before IMAG reverses,
actively connects the bottom plate of CCL to ground and
allows SWP to be discharged slowly. The resulting SWP
waveform during M1 off-time appears as a square wave
with a superimposed sinusoidal peak representing ripple
voltage on CCL.
The switch M2 experiences near zero voltage switching
(ZVS) since only the body diode voltage drop appears
across it at switch turn on.
HI Side Active Clamp Topology (LT3752-1)
For high input voltage applications the VDS rating of available P-channel MOSFETs might not be high enough to
be used as the active clamp switch in the LO side active
clamp topology (Figure 13). An N-channel approach using
the HI side active clamp topology (Figure 17) should be
used. This topology requires a gate drive transformer or
a simple gate drive opto-coupler to drive the N-channel
MOSFET (M2) for switching in the active clamp capacitor
from SWP to VIN. The M1 drain voltage calculation is the
same as in the LO side active clamp case and M1 should
be rated in a similar manner. The voltage across the clamp
capacitor in the HI side architecture, however, is lower by
VIN since it is referenced to VIN.
The steady-state active clamp capacitor voltage VCCL to
reset the transformer in a HI side active clamp topology
can be approximated by:
VCCL (HI side):
(a) Steady state: VCCL = VRESET = VDS – VIN
=
During load transients, duty cycle and hence VCCL may
increase. Replace D with DVSEC in the equation above to
calculate transient VCCL values. DVSEC guardrail can be
programmed as close as 6% higher than D but may require
a larger margin to improve transient response. See the
previous section Programming Duty Cycle Clamp–DVSEC.
CCL should be rated for a voltage higher than the above
steady-state calculation due to tolerances in duty cycle,
load transients, voltage ripple on CCL and the effect of
voltage coefficient on capacitance value. A typical choice
for CCL is a good quality (X7R) capacitor. When using a
gate drive transformer to provide control of the active
clamp switch (M2), the external components C1, C2, R1,
D1 and T4 are required. T4 size will increase for lower
programmed switching frequencies due to a minimum
volt-second requirement. Alternatively, a simple gate driver
opto-coupler can be used as a switch to control M2, for a
smaller solution size. The input supply capacitor for the gate
drive opto-coupler is easily charged using the housekeeping supply of the LT3752-1. Common component values
are shown in the Typical Applications section.
Active Clamp Capacitor Value and Voltage Ripple
The active clamp capacitor value should be chosen based
on the amount of voltage ripple which can be tolerated
by components attached to SWP. Lower CCL values will
create larger voltage ripple (increased drain voltage for the
primary side power MOSFET) but will require less swing
in magnetizing current to move the active clamp capacitor
during duty cycle changes. Choosing too high a value for
the active clamp capacitor (beyond what is needed to keep
ripple voltage to an acceptable level) will require unnecessary additional flux swing during transient conditions. For
systems with flux swing detection, too high a value for the
active clamp capacitor will trigger the detection system
early and degrade transient response.
N
D
• VIN = VIN • VOUT •
1– D
VIN – ( VOUT • N)
(b) Transient:
Rev. C
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LT3752/LT3752-1
APPLICATIONS INFORMATION
Another factor to consider is the resonance between CCL and
the magnetizing inductance (LMAG) of the main transformer.
An RC snubber (RS, CS) in parallel with CCL will dampen
the sinusoidal ringing and limit the peak voltages at the
primary side MOSFET drain during input/load transients.
Check circuit performance to determine if the snubber
is required. Component values can be approximated as:
C CL (active clamp capacitance) =
2
⎛ (1– D MIN ) ⎞
•⎜
⎟
L MAG ⎝ 2 • π • fOSC ⎠
10
where,
DMIN = (VOUT/VIN(MAX)) • NP/NS
Active Clamp MOSFET Selection
The selection of active clamp MOSFET is determined by
the maximum levels expected for the drain voltage and
drain current. The active clamp switch (M2) in a either a lo
side or hi side active clamp topology has the same BVdss
requirements as the main N-channel power MOSFET. The
current requirements are divided into two categories :
(A) Drain Current
This is typically less than the main N-channel power
MOSFET because the active clamp MOSFET sees only
magnetizing current, estimated as :
and (if needed),
Peak IMAG (steady state) = (1/2) • (NP/NS) • (VOUT/
LMAG) • (1/fOSC)
CS (snubber capacitance) = 6 • CCL
where,
RS (snubber resistance) = (1/(1-DMAX)) • √(LMAG/CCL)
LMAG = main transformer’s magnetizing inductance
where,
Example (LT3752) : For VOUT =12V, NP/NS = 2, fOSC =
250kHz and LMAG = 100µH, Peak IMAG = 0.48A.
DMAX = ( VOUT/VIN(MIN)) • NP/NS
Check the voltage ripple on SWP during steady-state
operation.
This value should be doubled for safety margin due to
variations in LMAG, fOSC and transient conditions.
CCL voltage ripple can be estimated as:
(B) Body Diode Current
VCCL(RIPPLE) = VCCL • (1-D)2/(8 • CCL • LMAG • fOSC2)
where,
D = (VOUT/VIN) • (NP/NS)
VCCL = VIN/(1-D) (Lo side active clamp topology)
VCCL = D • VIN/(1-D) (Hi side active clamp topology)
Example : For VIN = 36V, VOUT = 12V, NP/NS = 2, VCCL =
108V (Lo side active clamp topology), CCL = 22nF, LMAG
= 100µH, fOSC = 250kHz, VCCL(RIPPLE) = 108(0.33)2/(8(22
• 10–9)(10–4)(2.5 • 104)2) = 10.7V
The transformer is typically chosen to operate at a maximum
flux density that is low enough to avoid excessive core
losses. This also allows enough headroom during input
and load transients to move the active clamp capacitor at
a fast enough rate to keep up with duty cycle changes.
The body diode will see reflected output current as a pulse
every time the main N-channel power MOSFET turns off.
This is due to residual energy stored in the transformer's
leakage inductance. The body diode of the active clamp
MOSFET should be rated to withstand a forward pulsed
current of:
ID(MAX) = (NS/NP) (IOUT(MAX) + (IL(RIPPLE)(P-P)/2))
where,
IL(RIPPLE)(P-P) = output inductor ripple current = (VOUT/
(LOUT • fOSC)) • (1–(VOUT/VIN)(NP/NS))
IOUT(MAX) = maximum output load current
Rev. C
34
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LT3752/LT3752-1
APPLICATIONS INFORMATION
Programming Active Clamp Switch Timing: AOUT to
OUT (tAO) and OUT to AOUT (tOA) Delays
Programming Synchronous Rectifier Timing: SOUT to
OUT (tSO) and OUT to SOUT (tOS) Delays
The timings tAO and tOA represent the delays between AOUT
and OUT edges (Figures 1 and 2) and are programmed
by a single resistor, RTAO, connected from analog ground
(Pin 18) to the TAO pin. Once tAO is programmed for the
reasons given below, tOA will be automatically generated.
The LT3752/LT3752-1 include a ±0.4A gate driver at the
SOUT pin to send a control signal via a pulse transformer
to the secondary side of the forward converter for synchronous rectification (see Figures 1 and 2). For the
highest efficiency, M4 should be turned on whenever M1
is turned off. This suggests that SOUT should be a nonoverlapping signal with OUT with very small non-overlap
times. Inherent timing delays, however, which can vary
from application to application, can exist between OUT to
CSW and between SOUT to CG. Possible shoot-through
can occur if both M1 and M4 are on at the same time,
resulting in transformer and/or switch damage.
Front-end timing tAO (M2 off, M1 on)
= AOUT(edge)-to-OUT(rising)
= 50ns + 3.8ns •
RTAO
, 14.7k < RTAO < 125k
1k
In order to minimize turn-on transition loss in M1 the drain
of M1 should be as low as possible before M1 turns on.
To achieve this, AOUT should turn M2 off a delay of tAO
before OUT turns M1 on. This allows the main transformer’s
magnetizing current to discharge M1 drain voltage quickly
towards VIN before M1 turns on.
As SWP falls below VIN, however, the rectifying diodes on
the secondary side are typically active and clamp the SWP
node close to VIN. If enough leakage inductance exists,
however, the clamping action on SWP by the secondary
side will be delayed—potentially allowing the drain of
M1 to be fully discharged to ground just before M1 turns
on. Even with this delay due to the leakage inductance,
LMAG needs to be low enough to allow IMAG to be negative
enough to slew SWP down to ground before M1 turns on.
If achievable, M1 will experience zero voltage switching
(ZVS) for highest efficiency. As will be seen in a later section entitled Primary-Side Power MOSFET Selection, M1
transition loss is a significant contributor to M1 losses.
Back-end timing tOA (M1 off, M2 on) is automatically
generated
= OUT(falling)-to-AOUT(edge) = 0.9 • tAO
tOA should be checked to ensure M2 is not turned on until
M1 and M3 are turned off.
Front-end timing: tSO (M4 off, M1 on)
= SOUT(falling)-to-OUT(rising) delay
= tSO = tAO – tAS
= 3.8ns • (RTAS – RTAO)
where:
tAS = 50ns + (3.8ns • RTAS/1k) , 14.7k < RTAS < 125k,
tAO = 50ns + (3.8ns • RTAO/1k), 14.7k < RTAO < 125k,
tSO is defined by resistors RTAS and RTAO connected from
analog ground (Pin 18) to their respective pins TAS and
TAO. Each of these resistor defines a delay referenced
to the AOUT edge at the start of each cycle. RTAO was
already programmed based on requirements defined in
the previous section Programming AOUT to OUT Delay.
RTAS is then programmed as a delay from AOUT to SOUT
to fulfill the equation above for tSO. By choosing RTAS less
than or greater than RTAO, the delay between SOUT falling
and OUT rising can be programmed as positive or negative. While a positive delay can always be programmed
for tSO, the ability to program a negative delay allows for
improved efficiency if OUT(rising)-to-CSW(rising) delay
is larger than SOUT(falling)-to-CG(rising) delay.
Rev. C
For more information www.analog.com
35
LT3752/LT3752-1
APPLICATIONS INFORMATION
Back-end timing: tOS (M1 off, M4 on)
= OUT (falling)-to-SOUT (rising) delay
= tOS = 35ns + (2.2ns • RTOS/1k), 7.32k < RTOS < 249k
The timing resistor, RTOS, defines the OUT (falling)-to-SOUT
(rising) delay. This pin allows programming of a positive
delay, for applications which might have a large inherent
delay from OUT fall to SW2 fall.
Soft-Start (SS1, SS2)
The LT3752/LT3752-1 use SS1 and SS2 pins for soft starting
various parameters (Figures 3, 4 and 18). SS1 soft starts
internal oscillator frequency and DVSEC (maximum duty
cycle clamp). SS2 soft starts COMP pin voltage to control
output inductor peak current. Using separate SS1 and SS2
pins allows the soft-start ramp of oscillator frequency and
DVSEC to be independent of COMP pin soft-start. Typically
SS1 capacitor (CSS1) is chosen as 0.47µF and SS2 capacitor (CSS2) is chosen as 0.1µF. Soft-start charge currents
are 11.5µA for SS1 and 21µA for SS2.
SS1 is allowed to start charging (soft-start) if all of the
following conditions exist (typical values) :
(1) UVLO_VSEC > 1.25V: System input not in UVLO
(2) OVLO < 1.215V: System input not in OVLO
(3) HFB > 0.96V: Housekeeping supply valid
SS1 = 1.25V to 2.45V (soft-start fOSC, DVSEC). This is the
SS1 range for soft-starting fOSC and DVSEC folded back from
22% (50% for LT3752-1) to 100% of their programmed
levels. Fold back of fOSC and DVSEC reduces effective
minimum duty cycle for the primary side MOSFET. This
allows inductor current to be controlled at low output
voltages during start-up.
SS1 ramp rate is chosen slow enough to ensure fOSC and
DVSEC foldback lasts long enough for the converter to take
control of inductor current at low output voltages. In addition, slower SS1 ramp rate increases the non-switching
period during an output short to ground fault (over current
hiccup mode) to reduce average power dissipation (see
Hard-Stop).
SS2 = 0V to 1.6V (soft-start COMP pin). This is the SS2
range for soft-starting COMP pin from approximately 1V
to 2.6V.
SS2 ramp rate is chosen fast enough to allow a (slower)
soft-start control of COMP pin from a secondary side
opto-coupler controller.
SS1 soft-start non-switching period (0V to 1.25V)
= 1.25V • CSS1/11.5µA
SS1 soft-start fOSC, DVSEC period (1.25V to 2.45V)
= 1.2V • CSS1/11.5µA
SS2 soft-start COMP period (0V to 1.6V) = 1.6V • CSS2/21µA
(4) OC < 96mV: No over current condition
(5) X < INTVCC < 16V: INTVCC valid
Soft-Stop (SS1)
(6) TJ < 165°C: Junction temperature valid
The LT3752/LT3752-1 gradually discharge the SS1 pin
(soft-stop) when a system input UVLO occurs or when
an external soft-stop shutdown command occurs (0.4V <
UVLO_VSEC < 1.25V). During SS1 soft-stop the converter
continues to switch, folding back fOSC, DVSEC and COMP
pin voltage (Figures 3, 4 and 18). Soft-stop discharge
current is 10.5µA for SS1. Soft-stop provides:
(7) VIN > Y: VIN pin valid
(X = 4.75V, Y = 5.8V for LT3752)
(X = 7.0V, Y = 9.5V for LT3752-1)
SS1 = 0V to 1.25V (no switching). This is the SS1 range
for no switching for the forward converter. SS2 = 0V.
SS1 > 1.25V allows SS2 to begin charging from 0V.
(1) Active control of the secondary winding during output
discharge for clean shutdown in self-driven applica tions.
(2) Controlled discharge of the active clamp capacitor
to minimize magnetizing current swing during restart.
Rev. C
36
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LT3752/LT3752-1
APPLICATIONS INFORMATION
SS1: 2.45V to 1.25V (soft-stop fOSC, DVSEC, COMP). This
is the SS1 range for soft-stop folding back of:
(3) HFB < 0.92V: Housekeeping supply UVLO
(1) fOSC and DVSEC from 100% to 22% (50% for LT3752-1)
of their programmed levels.
(5) INTVCC < X(UVLO), > 16.5V (OVLO)
(2) COMP pin (100% to 0% of commanded peak
current).
SS1 soft-stop fOSC , DVSEC, COMP period (2.45V to 1.25V)
= 1.2V • CSS1/10.5µA
SS1 < 1.25V. Forward converter stops switching and SS2
pin is discharged to 0V using 2.8mA.
SS1 = 1.25V to 0V: When SS1 falls below 0.15V the internal
SS1 latch is reset. If all faults are removed, SS1 begins
charging again. If faults still remain, SS1 discharges to 0V.
SS1 soft-stop non-switching period (1.25V to 0V)
= 1.25V • CSS1/10.5µA
DVSEC rises as system input voltage falls in order to
provide a maximum duty cycle guardrail (volt-second
clamp). When system input falls below it's UVLO threshold, however, this triggers a soft-stop with the converter
continuing to switch. It is important that DVSEC no longer
increases even though system input voltage may still be
falling. The LT3752/LT3752-1 achieve an upper clamp on
DVSEC by clamping the minimum level for the IVSEC pin
to 1.25V. As SS1 pin discharges during soft-stop it folds
back DVSEC. As DVSEC falls below the natural duty cycle
of the converter, the converter loop follows DVSEC. If the
system input voltage rises (IVSEC pin rises) during softstop the volt-second clamp circuit further reduces DVSEC.
The I.C. chooses the lowest DVSEC commanded by either
the IVSEC pin or the SS1 soft-stop function.
Hard-Stop (SS1, SS2)
Switching immediately stops and both SS1 and SS2 pins
are rapidly discharged (Figure 18. Hard-Stop) if any of the
following faults occur (typical values):
(1) UVLO_VSEC < 0.4V: Micropower shutdown
(2) OVLO > 1.250V: System input OVLO
(4) OC > 96mV: Over current condition
(6) TJ > 170°C: Thermal shutdown
(7) VIN < Y: VIN pin UVLO
(X = 4.6V, Y = 5.5V for LT3752)
(X = 6.8V, Y = 7.6V for LT3752-1)
Switching stops immediately for any of the faults listed
above. When SS1 discharges below 0.15V it begins charging again if all faults have been removed. For an over current fault triggered by OC > 96mV, the disable of switching
will cause the OC pin voltage to fall back below 96mV.
This will allow SS1 and SS2 to recharge and eventually
attempt switching again. If the over current condition still
exists, OC pin will exceed 96mV again and the discharge/
charge cycle of SS1 and SS2 will repeat in a hiccup mode.
The non-switching dead time period during hiccup mode
reduces the average power seen by the converter in an
over current fault condition. The dead time is dominated
by SS1 recharging from 0.15V to 1.25V.
Non-switching period in over current (hiccup mode):
= 1.1V • CSS1/11.5µA
OUT, AOUT, SOUT Pulse-Skipping Mode
During load steps, initial soft-start, end of soft-stop or
light load operation (if the forward converter is designed
to operate in DCM), the loop may require pulse skipping on
the OUT pin. This occurs when the COMP pin falls below
its switching threshold. If the COMP pin falls below it's
switching threshold while OUT is turned on, the LT3752/
LT3752-1 will immediately turn OUT off ; both AOUT and
SOUT will complete their normal signal timings referenced
from the OUT falling edge. If the COMP pin remains below
it's switching threshold at the start of the next switching
cycle, the LT3752/LT3752-1 will skip the next OUT pulse
and therefore also skip AOUT and SOUT pulses. For AOUT
control, this prevents the active clamp capacitor from be-
Rev. C
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37
LT3752/LT3752-1
APPLICATIONS INFORMATION
HARD STOP
(FAULTS)
SOFT-START
(WHEN ALL CONDITIONS SATISFIED)
SOFT-STOP
(0.4V < UVLO_VSEC < 1.25)
(1) UVLO_VSEC < 0.4V
(2) OVLO > 1.25V
(3) HFB < 0.92V
(4) OC > 96mV
(5) INTVCC < X, > 16.5V
(6) TJ > 170°C
(7) VIN < Y
(X = 4.6V, Y = 5.5V: LT3752)
(X = 6.8V, Y = 7.6V: LT3752-1)
(1) UVLO_VSEC > 1.25V
(2) OVLO < 1.215V
(3) HFB > 0.96V
(4) OC < 96mV
(5) X < INTVCC < 16V
(6) TJ < 165°C
(7) VIN > Y
(X = 4.75V, Y = 5.8V: LT3752)
(Y = 7.0V, Y = 9.5V: LT3752-1)
(1) EXTERNAL SOFT-STOP SHUTDOWN
(2) SYSTEM INPUT UVLO
SS1 SOFT STARTS
fOSC AND DVSEC
HARD
STOP
SS1 SOFT STOPS
fOSC, DVSEC AND COMP
2.6V
SS1
SS1 LATCH
RESET THRESHOLD
1.25V
0.15V
0V
2.6V
SS2 SOFT STARTS
COMP
SS2
0V
0.25V
2.6V
COMP
RANGE
COMP 1.25V
SWITCHING THRESHOLD
COMP
0V
1V
3752 F18
Figure 18. SS1, SS2 and COMP Pin Voltages During Faults, Soft-Start and Soft-Stop
ing accidentally discharged during missing OUT pulses
and/or causing reverse saturation of the transformer.
For SOUT control, this prevents the secondary side synchronous rectifier controller from incorrectly switching
between forward FET and synchronous FET conduction.
The LT3752/LT3752-1 correctly re-establish the required
AOUT, SOUT control signals if the OUT signal is required
for the next cycle.
AOUT Timeout
During converter start-up in soft-start, the switching frequency and maximum duty cycle clamp DVSEC are both
folded back. While this correctly reduces the effective
minimum on time of the OUT pin (to allow control of inductor current for very low output voltages during start-up),
this means the AOUT pin on time duration can be large.
In order to ensure the active clamp switch controlled by
AOUT does not stay on too long, the LT3752/LT3752-1 have
an internal 15µs timeout to turn off the AOUT signal. This
prevents the active clamp capacitor from being connected
across the transformer primary winding long enough to
create reverse saturation.
Main Transformer Selection
The LT3752/LT3752-1 simplify the design of the main
transformer and output inductor by removing the need for
any auxiliary windings. Any bootstrap supplies required
for the primary side or bias supplies required for the
secondary side can all be provided by the housekeeping
DC/DC controller included in the LT3752/LT3752-1. (see
Housekeeping Controller in the Applications Information
Section).
Rev. C
38
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LT3752/LT3752-1
APPLICATIONS INFORMATION
The selection of the main transformer will depend on the
applications requirements : isolation voltage, power level,
maximum volt-seconds, turns ratio, component size, power
losses and switching frequency.
Transformer construction using the planar winding technology is typically chosen for minimizing leakage inductance
and reducing component height. Transformer core type is
usually a ferrite material for high frequency applications.
Find a family of transformers that meet both the isolation
and power level requirements of the application. The next
step is to find a transformer within that family which is
suitable for the application. The subsequent thought process for the transformer design will include :
(1) Secondary turns (NS), core losses, temperature
rise, flux density, switching frequency
(2) Primary turns (NP), maximum duty cycle and reset
voltages
(3) Copper losses
The expression for secondary turns (NS) is given by,
NS = 108 VOUT/(fOSC • AC • BM)
where,
AC = cross-sectional area of the core in cm2
BM = maximum AC flux density desired
For flux density, choose a level which achieves an acceptable level of core loss/temperature rise at a given switching
frequency. The transformer data sheet will provide curves
of core loss versus flux density at various switching frequencies. The data sheet will also provide temperature rise
versus core loss. While choosing a value for BM to avoid
excessive core losses will usually allow enough headroom
for flux swing during input / load transients, still make
sure to stay well below the saturation flux density of the
transformer core. If needed, increasing NS will reduce flux
density. After calculating NS, the number of primary turns
(NP) can be calculated from,
NP = NS • DMAX VIN(MIN)/VOUT
where,
VIN(MIN) = minimum system input voltage
DMAX = maximum switch duty cycle at VIN(MIN) (typically
chosen between 0.6 and 0.7)
At minimum input voltage the converter will run at a maximum duty cycle DMAX. A higher transformer turns ratio
(NP/NS) will create a higher DMAX but it will also require
higher voltages at the drain of the primary side switch to
reset the transformer (see previous sections Lo side Active
Clamp Topology and Hi side Active Clamp Topology). DMAX
values are typically chosen between 0.6 and 0.7. Even for
a given DMAX value, the loop must also provide protection
against duty cycles that may excessively exceed DMAX
during transients or faults. While most converters only
provide a fixed duty cycle clamp, the LT3752/LT3752-1
provide a programmable maximum duty cycle clamp DVSEC
that also moves inversely with input voltage.
The resulting function is that of a programmable voltsecond clamp. This allows the user to choose a transformer
turns ratio for DMAX and then customize a maximum duty
cycle clamp DVSEC above DMAX for safety. DVSEC then
follows the natural duty cycle of the converter as a safety
guardrail (see previous section Programming Duty Cycle
Clamp).
After deciding on the particular transformer and turns ratio,
the copper losses can then be approximated by,
PCU = D • I(Load)(MAX)2 (RSEC + (NS/NP)2 RPRI)
where,
D = switch duty cycle (choose nominal 0.5)
I(Load)(MAX) = maximum load current
Rev. C
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39
LT3752/LT3752-1
APPLICATIONS INFORMATION
RPRI = primary winding resistance
perature is known. A final value for RDS(ON) and therefore
PCONDUCTION can be achieved from a few iterations.
RSEC = secondary winding resistance
If there is a large difference between the core losses and
the copper losses then the number of secondary turns
can be adjusted to achieve a more suitable balance. The
number of primary turns should then be recalculated to
maintain the desired turns ratio.
Primary-Side Power MOSFET Selection
The selection of the primary-side N-channel power MOSFET
M1 is determined by the maximum levels expected for the
drain voltage and drain current. In addition, the power
losses due to conduction losses, gate driver losses and
transition losses will lead to a fine tuning of the MOSFET
selection. If power losses are high enough to cause an
unacceptable temperature rise in the MOSFET then several
MOSFETs may be required to be connected in parallel.
The maximum drain voltage expected for the MOSFET M1
follows from the equations previously stated in the active
clamp topology sections:
VDS (M1) = VIN2/(VIN – (VOUT • N))
The MOSFET should be selected with a BVDSS rating approximately 20% greater than the above steady state VDS
calculation due to tolerances in duty cycle, load transients,
voltage ripple on CCL and leakage inductance spikes. A
MOSFET with the lowest possible voltage rating for the
application should be selected to minimize switch on resistance for improved efficiency. In addition, the MOSFET
should be selected with the lowest gate charge to further
minimize losses.
MOSFET M1 losses at maximum output current can be
approximated as :
PM1 = PCONDUCTION + PGATEDRIVER + PTRANSITION
(i) PCONDUCTION = (NP/NS) • (VOUT/VIN) • (NS/NP •
IOUT(MAX))2 • RDS(ON)
Note: The on resistance of the MOSFET, RDS(ON), increases with the MOSFET’s junction temperature. RDS(ON)
should therefore be recalculated once junction tem-
(ii) PGATEDRIVER = (QG • INTVCC • fOSC)
where,
QG = gate charge (VGS = INTVCC)
(iii) PTRANSITION = PTURN_OFF + PTURN_ON (≈ 0 if ZVS)
(a) P TURN_OFF = (1/2)I OUT(MAX) (N S/N P)(V IN/1-D)
(QGD/IGATE) • fOSC
where,
QGD = gate to drain charge
IGATE = 2A source/sink for OUT pin gate driver
(b) PTURN_ON = (1/2)IOUT(MAX)(NS/NP)(VDS)(QGD/IGATE)
• fOSC
where,
VDS = M1 drain voltage at the beginning of M1 turn on
VDS typically sits between VIN and 0V (ZVS)
During programmable timing tAO, negative IMAG discharges
M1 drain SWP towards VIN (Figure 1). ZVS is achieved if
enough leakage inductance exists—to delay the secondary side from clamping M1 drain to VIN—and if enough
energy is stored in LMAG to discharge SWP to 0V during
that delay. (see Programming Active Clamp Switch Timing:
AOUT to OUT (tAO)).
Synchronous Control (SOUT)
The LT3752 / LT3752-1 use the SOUT pin to communicate
synchronous control information to the secondary side
synchronous rectifier controller (Figure 19). The isolating
transformer (TSYNC), coupling capacitor (CSYNC) and resistive load (RSYNC) allow the ground referenced SOUT signal
to generate positive and negative signals required at the
SYNC input of the secondary side synchronous rectifier
controller. For the typical LT3752/LT3752-1 applications
operating with an LT8311, CSYNC is 220pF, RSYNC is 560Ω
and TSYNC is typically a PULSE PE-68386NL.
Rev. C
40
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LT3752/LT3752-1
APPLICATIONS INFORMATION
CSYNC
220pF
SOUT
(LT3752/LT3752-1)
1
2
3
TSYNC
•
•
•
•
6
5
4
SYNC
RSYNC (SECONDARY SIDE
560Ω CONTROLLER)
3752 F19
Figure 19. SOUT Pulse Transformer
Typically choose CSYNC between 220pF and 1nF. RSYNC
should then be chosen to obey :
(1) SOUTMAX/100mA ≤ RSYNC ≤ √(LMAG/CSYNC)
where,
SOUTMAX = INTVCC
The LT3752/LT3752-1 allow very large ∆IL values (low LOUT
values) without the worry of insufficient slope compensation—by allowing slope compensation to be programmed
with an external resistor in series with the ISENSEP pin (see
Current Sensing and Programmable Slope Compensation).
Larger ∆IL will allow lower LOUT, reducing component size,
but will also cause higher output voltage ripple and core
losses. For LT3752/LT3752-1 applications, ∆IL is typically
chosen to be 40% of IOUT(MAX).
Output Capacitor Selection
The choice of output capacitor value is dependent on
output voltage ripple requirements given by :
∆VOUT ≈ ∆IL(ESR + (1/(8 • fOSC • COUT))
LMAG = TSYNC’S magnetizing inductance
100mA = SOUT gate driver minimum source current
and
(2) RSYNC • CSYNC ≥ (–1) • Y/(ln (Z/SOUTMAX))
where,
Y = SYNC minimum pulse duration (50ns; LT8311)
Z = |SYNC level to achieve Y| (±2V: LT8311)
Even though the LT3752/LT3752-1 INTVCC pin is allowed
to be over driven by as much as 15.4V using the housekeeping supply, SOUTMAX level should be designed to not
cause TSYNC output to exceed the maximum ratings of the
LT8311’s SYNC pin.
Cost/Space reduction : If discontinuous conduction mode
(DCM) operation is acceptable at light load, the LT8311
has a preactive mode which controls the synchronous
MOSFETs without TSYNC, CSYNC, RSYNC or the LT3752/
LT3752-1 timing resistors RTAS, RTOS (leave open).
where,
∆IL = output inductor ripple current IL(RIPPLE)(P-P)
ESR = effective series resistance (of COUT)
fOSC = switching frequency
COUT = output capacitance
This gives:
COUT = ∆IL/(8 • fOSC • ( ∆VOUT – ∆IL • ESR))
Typically COUT is made up of a low ESR ceramic capacitor(s)
to minimize ∆VOUT. Additional bulk capacitance is added
in the form of electrolytic capacitors to minimize output
voltage excursions during load steps.
Input Capacitor Selection
The choice of output inductor value LOUT will depend on
the amount of allowable ripple current. The inductor ripple
current is given by:
The active clamp forward converter demands pulses of
current from the input due to primary winding current and
magnetizing current. The input capacitor is required to
provide high frequency filtering to achieve an input voltage
as close as possible to a pure DC source with low ripple
voltage. For low impedance input sources and medium to
low voltage input levels, a simple ceramic capacitor with
low ESR should suffice. It should be rated to operate at a
worst case RMS input current of :
IL(RIPPLE)(P-P)
ICIN(RMS) = (NS/NP) IOUT(MAX)/2
Output Inductor Value
= ∆IL = (VOUT/(LOUT • fOSC)) • (1 – (VOUT/VIN)(NP/NS))
Rev. C
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41
LT3752/LT3752-1
APPLICATIONS INFORMATION
A small 1µF bypass capacitor should also be placed close
to the IC between VIN and GND.
As input voltage levels increase, any use of bulk capacitance
to minimize input ripple can impact on solution size and
cost. In addition, inputs with higher source impedance will
cause an increase in voltage ripple. In these applications it
is recommended to include an LC input filter. The output
impedance of the input filter should remain below the
negative input impedance of the DC/DC forward converter.
PCB Layout / Thermal Guidelines
For proper operation, PCB layout must be given special
attention. Critical programming signals must be able to
co-exist with high dv/dt signals. Compact layout can be
achieved but not at the cost of poor thermal management.
The following guidelines should be followed to approach
optimal performance.
1. Ensure that a local bypass capacitor is used (and placed
as close as possible) between VIN and GND for the
controller IC(s).
2. The critical programming resistors for timing (pins
TAO,TAS,TOS,TBLNK, IVSEC and RT) must use short traces
to each pin. Each resistor should also use a short trace
to connect to a single ground bus specifically connected
to pin 18 of the IC (GND).
3. The current sense resistor for the forward converter must
use short Kelvin connections to the ISENSEP and ISENSEN
pins. The current sense resistor for the housekeeping
supply should have it’s ground connection as close as
possible to the power ground (PGND) pin 38.
4. High dv/dt lines should be kept away from all timing
resistors, current sense inputs, HCOMP/COMP pins,
UVLO_VSEC/OVLO pins and both HFB and FB feedback
traces.
5. Gate driver traces (HOUT, AOUT, SOUT, OUT) should be
kept as short as possible.
6. When working with high power components, multiple
parallel components are the best method for spreading out power dissipation and minimizing temperature
rise. In particular, multiple copper layers connected
by vias should be used to sink heat away from each
power MOSFET.
7. Keep high switching current PGND paths away from
signal ground. Also minimize trace lengths for those
high current switching paths to minimize parasitic
inductance.
Rev. C
42
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LT3752/LT3752-1
APPLICATIONS INFORMATION
VAUX
ZVN4525E6
M5
HOUT HISENSE
VIN
OVLO
ISENSEN
SOUT
INTVCC
R5
22.6k
R4
49.9k
R7
34k
R6
7.32k
R9
31.6k
R8
71.5k
C3
22nF
C2
0.33µF
COMP
FB
HCOMP
SS2
SS1
RT
GND
TBLNK
IVSEC
R10
2.8k
R24
C4
100k
22nF
C13
22µF
16V
×2
HFB
R23
100k
R14
2k
R15
0.006Ω
•
R13
560Ω
INTVCC
R11
10k
R12
1.1k
VIN
R28
3.16k
R25
100Ω
C5
4.7µF
C16
1µF
PS2801-1
LT8311
FB
R30
100k
GND
PGOOD
SYNC
T3
•
C6 220pF
C11
2.2µF
R27
100k
R22
100Ω
VAUX
C12
4.7µF
C17
220nF
R20
499k
C28
68pF
R31
11.3k
C18
68pF
R29
13.7k
C19
4.7nF
3752 F20a
R26
1k
2.2nF
T1: CHAMPS G45AH2-0404-04
T2: BH ELECTRONICS L00-3250
T3: PULSE PE-68386NL
L1: CHAMPS PQI2050-6R8
D1, D2, D3: BAS516
D4: CENTRAL SEMI CMMR1U-02
Efficiency vs Load Current
96
94
EFFICIENCY (%)
R3
1.82k
UVLO_VSEC
R21
100Ω
BSC077N12NS3
M1
VAUX
OUT
LT3752
M4
M3
+
VOUT
12V
12.5A
D1
OC
ISENSEP
TAS
TOS
R2
5.9k
AOUT
SYNC
TAO
R1
100k
M2
C14
470µF
16V
C24
2.2nF
250V
BSC077N12NS3
FDMS86101
Si2325DS
R16
10k
R38
20k
D4
C8
15nF
C7
100nF
R18
0.15Ω
•
CSN
CSP
•
R17
499Ω
•
C10
2.2µF
COMP
D3
SS
•
CG
T2
CSW
•
INTVCC
PMODE
TIMER
D2
C9
2.2µF
FG
INTVCC
L1
6.8µH
FSW
C1
4.7µF
100V
×3
T1
4:4
OPTO
VIN
18V TO 72V
92
90
24VIN
48VIN
72VIN
88
86
0
3
9
6
LOAD CURRENT (A)
12
15
3752 F20b
Figure 20. 18V to 72V, 12V/12.5A, 150W Active Clamp Isolated Forward Converter
Rev. C
For more information www.analog.com
43
LT3752/LT3752-1
TYPICAL APPLICATIONS
18V to 72V, 12V/12.5A, 150W No-Opto, Active Clamp Isolated Forward Converter
VAUX
R3
1.82k
AOUT
OC
ISENSEP
UVLO_VSEC
ISENSEN
LT3752
OVLO
SOUT
INTVCC
R5
22.6k
R4
49.9k
R7
34k
R6
7.32k
R9
31.6k
R8
60.4k
C3
22nF
C2
0.33µF
FB
HCOMP
SS2
SS1
RT
TBLNK
IVSEC
TAS
TOS
TAO
GND
R10
2.8k
C4
22nF
M4
M3
C14
470µF
16V
+
C13
22µF
16V
×2
D1
HFB
R21
100Ω
BSC077N12NS3
M1
V
OUT
SYNC
C24
2.2nF
250V
AUX
R14
2k
R15
0.006Ω
•
C6 220pF
R11
10k
R12
1.1k
C11
2.2µF
R13
560Ω
LT8311
FB
GND
PGOOD
SYNC
T3
•
VIN
R22
100Ω
CSN
CSP
R2
5.9k
R16
10k
R38
20k
BSC077N12NS3
FDMS86101
Si2325DS
COMP
R1
100k
C8
15nF
M2
R18
0.15Ω
HOUT HISENSE
VIN
D4
C7
100nF
M5 ZVN4525E6
•
VOUT
12V
12.5A
COMP
•
R17
499Ω
•
C10
2.2µF
SS
D3
CG
•
CSW
•
FG
D2
C9
2.2µF
L1
6.8µH
FSW
INTVCC
T1
4:4
INTVCC
PMODE
TIMER
C1
4.7µF
100V
×3
T2
OPTO
VIN
18V TO 72V
VAUX
INTVCC
C12
4.7µF
C5
4.7µF
R20
499k
2.2nF
3752 TA02
T1: CHAMPS G45AH2-0404-04
T2: BH ELECTRONICS L00-3250
T3: PULSE PE-68386NL
L1: CHAMPS PQI2050-6R8
D1, D2, D3: BAS516
D4: CENTRAL SEMI CMMR1U-02
VOUT vs Load Current (No-Opto)
Efficiency vs Load Current
14.0
96
13.5
94
EFFICIENCY (%)
13.0
VOUT (V)
12.5
12.0
11.5
VIN = 70V
VIN = 60V
VIN = 48V
VIN = 36V
VIN = 20V
11.0
10.5
10.0
0
2
6
8
4
LOAD CURRENT (A)
10
92
90
24VIN
48VIN
72VIN
88
86
12
3752 TA02a
0
3
9
6
LOAD CURRENT (A)
12
15
3752 TA02b
Rev. C
44
For more information www.analog.com
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W Active Clamp Isolated Forward Converter
T1
31:5
IPD60R1K4C6
UVLO_VSEC
ISENSEN
LT3752-1
OVLO
IPD65R25OC6
M1
VAUX
R14
2k
R7
100k
R6
13k
R9
78.7k
R8
124k
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
COMP
FB
HCOMP
SS2
SS1
C3
0.22µF
C2
0.47µF
HFB
C4
3.3nF
R24
22k
R23
22k
•
C11
2.2µF
R27
100k
R12
806Ω
VIN
•
R13
560Ω
R28
3.16k
R25
C5 100Ω
4.7µF
PS2801-1
C16
1µF
C12
4.7µF
C13
33µF
16V
×4
R30
100k
C28
68pF
FB
LT8311
VAUX
+
VOUT
12V
16.7A
R22
100Ω
C27
120pF
GND
PGOOD
SYNC
T3
INTVCC
R11
10k
R10
22k
C17
1µF
R20
432k
R31
11.3k
C18
100pF
R29
5.11k
C19
22nF
3752 TA03
R26
1.2k
2.2nF
Efficiency vs Load Current
96
95
94
93
EFFICIENCY (%)
R5
40.2k
R4
95.3k
R15
0.022Ω
C6 220pF
SOUT
INTVCC
GND
R21
100Ω
CSN
OC
ISENSEP
SYNC
M3
C14
330µF
16V
C24
10nF
250V
R38
0.002
CSP
C21
0.22µF
OUT
D4
COMP
M2
CG
AOUT
R38
10k
M4
RJK0653DPB
×2
SS
VOUT
ANODE
CATHODE
VEE
R18
0.15Ω
HISENSE
TBLNK
IVSEC
R3
2.94k
HOUT
D1
VCC
FDMS86200
×3
C8
47nF
630V
CSW
•
R17
499Ω
TAS
TOS
R2
5.76k
D3
M5
BSP300
VIN
TAO
R1
499k
•
L1
15µH
•
INTVCC
PMODE
TIMER
D5
C20
10µF
R34
499k
•
•
R19
402Ω
FG
R36
374k
D2
C9
10µF
VAUX
R16 4.2Ω
C15
C10 INTVCC
10nF
4.7µF
630V
ACPL-W346
FSW
R35
374k
T2
OPTO
INTVCC
RT
VIN
150V TO
400V C1
2.2µF
630V
92
91
90
89
88
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
87
86
85
0
2.5
7.5
10 12.5
5
LOAD CURRENT (A)
15
17.5
3752 TA03a
Rev. C
For more information www.analog.com
45
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W No-Opto, Active Clamp Isolated Forward Converter
T1
31:5
AOUT
M2
C21
0.22µF
ISENSEP
UVLO_VSEC
R2
5.76k
OVLO
R3
2.94k
ISENSEN
LT3752-1
R14
2k
R7
100k
R6
13k
R9
78.7k
R8
107k
C3
0.22µF
C2
0.47µF
FB
HCOMP
SS2
SS1
RT
TBLNK
IVSEC
TAS
TOS
TAO
R5
40.2k
R4
95.3k
R10
22k
C4
3.3nF
R21
100Ω
R15
0.022Ω
•
C6 220pF
SOUT
INTVCC
GND
M3
IPD65R25OC6
M1
VAUX
OC
C11
2.2µF
•
R13
560Ω
R12
806Ω
+
C13
33µF
16V
×4
R22
100Ω
C27
120pF
GND
LT8311
FB
VAUX
INTVCC
R11
10k
HFB
VIN
PGOOD
SYNC
T3
C24
10nF
250V
R38
0.002
IPD60R1K4C6
OUT
SYNC
M4
RJK0653DPB
×2
C14
330µF
16V
CSP
HOUT HISENSE
R38
10k
D4
CSN
R18
0.15Ω
C8
47nF
630V
FDMS86200
×3
VOUT
12V
16.7A
COMP
VOUT
ANODE
CATHODE
VEE
•
CG
R17
499Ω
D1
VCC
•
CSW
•
R19
402Ω
SS
VAUX
R16 4.2Ω
C15
C10 INTVCC
10nF
4.7µF
630V
ACPL-W346
D3
M5
BSP300
VIN
R1
499k
•
L1
15µH
INTVCC
PMODE
TIMER
C9
10µF
C20
10µF
R34
499k
T2
FG
R36
374k
•
FSW
D5
D2
OPTO
INTVCC
R35
374k
COMP
VIN
150V TO
400V C1
2.2µF
630V
C12
4.7µF
C5
4.7µF
R20
432k
3752 TA04
2.2nF
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
VOUT vs Load Current (No-Opto)
Efficiency vs Load Current
14.0
96
95
13.5
94
93
EFFICIENCY (%)
VOUT (V)
13.0
12.5
12.0
11.5
11.0
10.0
0
2
4
6
8 10 12 14
LOAD CURRENT (A)
16
91
90
89
88
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
10.5
92
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
87
86
85
18
3752 TA04a
0
2.5
7.5
10 12.5
5
LOAD CURRENT (A)
15
17.5
3752 TA04b
Rev. C
46
For more information www.analog.com
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W, Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
T1
31:5
R14
2k
UVLO_VSEC
ISENSEN
LT3752-1
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
C2
0.47µF
R10
22k
C4
3.3nF
COMP
FB
HCOMP
SS2
SS1
C3
0.22µF
R24
22k
HFB
•
R13
560Ω
INTVCC
R11
10k
R12
806k
R23
22k
R25
C5 100Ω
4.7µF
R28
3.16k
PS2801-1
C16
1µF
R26
1.2k
CSP
CSN
LT8311
VAUX
C12
4.7µF
C17
1µF
R20
432k
C13
33µF
16V
×4
R22
100Ω
C27
120pF
R30
100k
GND
PGOOD
SYNC
T3
•
VIN
CG
C11
2.2µF
R27
100k
+
VOUT
12V
16.7A
C28
68pF
FB
R31
11.3k
C18
100pF
R29
5.11k
C19
22nF
3752 TA05
2.2nF
Efficiency vs Load Current
96
95
94
93
EFFICIENCY (%)
R9
78.7k
R8
124k
R15
0.022Ω
C6 220pF
SOUT
INTVCC
GND
R7
100k
R6
13k
R21
100Ω
IPD65R25OC6
M1
VAUX
ISENSEP
R5
40.2k
R4
95.3k
M3
COMP
C21
470pF
OUT
C14
330µF
16V
C24
10nF
250V
R38
0.002
CSW
AOUT
R38
10k
D4
M4
RJK0653DPB
×2
IPD60R1K4C6
SYNC
OVLO
FDMS86200
×3
D1
R16
10k
R37
100Ω
•
SS
•
OC
TBLNK
IVSEC
R3
2.94k
C23 3.3nF
T4
•
R18
0.15Ω
HOUT HISENSE
TAS
TOS
R2
5.76k
R17
499Ω
VIN
TAO
R1
499k
C22
220nF
M5
BSP300
•
L1
15µH
INTVCC
PMODE
TIMER
•
C20
10µF
C15
10nF
630V
VAUX
C10
4.7µF
•
FG
R36
374k
R34
499k
•
FSW
D2
C9
D5
10µF
R19
402Ω
C8
47nF
630V
M2
OPTO
INTVCC
R35
374k
C1
2.2µF
630V
D3
T2
RT
VIN
150V TO
400V
92
91
90
89
88
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
87
86
85
0
2.5
7.5
10 12.5
5
LOAD CURRENT (A)
15
17.5
3752 TA05a
Rev. C
For more information www.analog.com
47
LT3752/LT3752-1
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A 200W, No-Opto, Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
T1
31:5
R3
2.94k
HOUT HISENSE
VIN
R16
10k
D1
C21
470pF
R21
100Ω
IPD65R25OC6
M1
VAUX
OUT
OC
SYNC
ISENSEP
UVLO_VSEC
ISENSEN
LT3752-1
OVLO
M3
IPD60R1K4C6
AOUT
R14
2k
R15
0.022Ω
•
C6 220pF
SOUT
C11
2.2µF
R13
560Ω
R7
100k
R6
13k
R9
78.7k
R8
107k
C3
0.22µF
C2
0.47µF
R10
22k
C4
3.3nF
COMP
FB
HCOMP
SS2
SS1
RT
TBLNK
IVSEC
TAS
TOS
TAO
R5
40.2k
R4
95.3k
HFB
R11
10k
R12
806Ω
C5
4.7µF
C13
33µF
16V
×4
GND
C12
4.7µF
2.2nF
+
R22
100Ω
C27
120pF
LT8311
FB
VAUX
INTVCC
GND
VIN
PGOOD
SYNC
T3
•
C24
10nF
250V
R38
0.002Ω
C14
330µF
16V
VOUT
12V
16.7A
CSP
R37
100Ω
D4
M4
RJK0653DPB
×2
CSN
R18
0.15Ω
•
R38
10k
COMP
R2
5.76k
R17
499Ω
•
FDMS86200
×3
CG
M5
BSP300
•
L1
15µH
SS
R1
499k
C22
C23 3.3nF
220nF T4
•
CSW
•
C20
10µF
C15
10nF
630V
VAUX
C10
4.7µF
•
INTVCC
PMODE
TIMER
R36
374k
R34
499k
•
FG
D2
C9
D5
10µF
R19
402Ω
C8
47nF
630V
M2
FSW
INTVCC
R35
374k
C1
2.2µF
630V
D3
T2
OPTO
VIN
150V TO
400V
3752 TA06
R20
432k
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
VOUT vs Load Current (No-Opto)
Efficiency vs Load Current
14.0
96
95
13.5
94
93
EFFICIENCY (%)
VOUT (V)
13.0
12.5
12.0
11.5
11.0
10.0
0
2
4
6
8 10 12 14
LOAD CURRENT (A)
16
91
90
89
88
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
10.5
92
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
87
86
85
18
3752 TA06a
0
2.5
7.5
10 12.5
5
LOAD CURRENT (A)
15
17.5
3752 TA06b
Rev. C
48
For more information www.analog.com
LT3752/LT3752-1
TYPICAL APPLICATIONS
75V to 150V, 24V/14A 340W Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
T1
10:6
R16
10k
R37
100Ω
C21
470pF
ISENSEN
LT3752-1
R7
80.1k
R6
10k
R9
52.3k
R8
82.5k
T1: CHAMPS LT80R2-12AC-1006
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
COMP
FB
HCOMP
SS2
SS1
C3
0.22µF
C2
0.47µF
R10
22k
C4
3.3nF
R24
22k
HFB
•
R13
560Ω
INTVCC
R11
10k
R12
806Ω
R25
C5 100Ω
4.7µF
PS2801-1
C16
1µF
R26
1.2k
R23
22k
R28
3.16k
R30
100k
CG
LT8311
VAUX
C12
4.7µF
C13
22µF
25V
×4
R22
100Ω
GND
PGOOD
SYNC
T3
+
VOUT
24V
14A
C28
68pF
FB
C17
0.33µF
R20
365k
R31
5.36k
C18
100pF
R29
5.11k
C19
22nF
3752 TA07
2.2nF
Efficiency vs Load Current
96
95
94
EFFICIENCY (%)
R5
53k
R4
93.1k
•
C6 220pF
SOUT
INTVCC
GND
R15
0.0075Ω
VIN
SS
R14
2k
UVLO_VSEC
C11
2.2µF
R27
100k
C27
120pF
CSN
ISENSEP
CSW
SYNC
C14
470µF
25V
C24
10nF
250V
R38
0.003Ω
M3
IPB200N25N3
M1
VAUX
OUT
R38
10k
D4
M4
BSC047N08NS3
×2
R21
100Ω
AOUT
OVLO
IPB072N15N3G
CSP
D1
•
COMP
•
OC
TBLNK
IVSEC
R3
5.76k
C23 3.3nF
T4
•
R18
0.15Ω
HOUT HISENSE
TAS
TOS
R2
6.04k
R17
499Ω
VIN
TAO
R1
6.98k
C22
220nF
M5
BSP300
•
INTVCC
PMODE
TIMER
•
C20
10µF
C15
4.7nF
250V
VAUX
C10
4.7µF
•
FG
R36
102k
R34
698k
•
L1
15µH
FSW
D2
C9
D5
10µF
R19
1k
C8
15nF
250V
M2
IRFL214
OPTO
INTVCC
R35
102k
C1
2.2µF
250V
D3
T2
RT
VIN
75V TO
150V
93
92
91
90
89
VIN = 75V
VIN = 100V
VIN = 125V
VIN = 150V
88
87
86
0
2.5
5
7.5
10
LOAD CURRENT (A)
12.5
15
3752 TA07a
Rev. C
For more information www.analog.com
49
LT3752/LT3752-1
PACKAGE DESCRIPTION
FE Package
Package Variation: FE38 (31)
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1665 Rev B)
Exposed Pad Variation AB
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
19
PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AB) TSSOP REV B 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev. C
50
For more information www.analog.com
LT3752/LT3752-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
06/14
Minor typographical changes throughout data sheet.
All
B
07/15
C
06/19
PAGE NUMBER
Changed Absolute Maximum SS2 rating to 16V.
3
Changed Absolute Maximum SS1 rating to 3V.
3
Changed Output Low Level in Shutdown conditions to INTVCC = 3V.
3
Changed AOUT Rise and Fall Times.
5
Changed SOUT Rise and Fall Times.
6
Changed SS2 Discharge Current conditions to SS2 = 2.5V.
6
Changed SS2 Charge Current conditions to SS2 = 1.5V.
6
Changed HOUT Rise and Fall Times.
7
Added AEC-Q100 Qualification and W Flow Part Numbers
1, 3, 4
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
51
LT3752/LT3752-1
TYPICAL APPLICATION
75V to 150V, 24V/14A 340W No-Opto, Active Clamp Isolated Forward Converter
T1
10:6
D1
C21
470pF
AOUT
IPB200N25N3
M1
VAUX
OC
ISENSEP
ISENSEN
LT3752-1
OVLO
R14
2k
C3
0.1µF
C2
0.47µF
COMP
FB
HCOMP
SS2
SS1
R9
52.3k
R8
75k
HFB
R10
22k
C4
3.3nF
•
C6 220pF
C11
2.2µF
VIN
PGOOD
SYNC
T3
•
R13
560Ω
LT8311
C5
4.7µF
R20
432k
2.2nF
VOUT vs Load Current (No-Opto)
T1: CHAMPS LT80R2-12AC-1006
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
Efficiency vs Load Current
28
96
27
95
94
26
25
VOUT (V)
FB
3752 TA08
C12
4.7µF
R12
806Ω
24
23
22
VIN = 75V
VIN = 100V
VIN = 125V
VIN = 150V
21
20
C13
22µF
25V
×4
R22
100Ω
C27
120pF
INTVCC
R11
10k
+
GND
EFFICIENCY (%)
R7
80.1k
R6
10k
RT
TBLNK
IVSEC
TAS
TOS
GND
TAO
R15
0.0075Ω
SOUT
INTVCC
R5
53k
R4
93.1k
M3
OUT
UVLO_VSEC
R3
5.76k
R38
0.003Ω
R21
100Ω
SYNC
R2
6.04k
M4
BSC047N08NS3
×2
C14
470µF
25V
CSP
R37
100Ω
R16
10k
C24
10nF
250V
CSN
HOUT HISENSE
VIN
R1
6.98k
R18
0.15Ω
•
D4
VOUT
24V
14A
COMP
R17
499Ω
•
R38
10k
IPB072N15N3G
SS
C20
10µF
R34
698k
C22
C23 3.3nF
220nF T4
M5
BSP300
•
CG
•
•
CSW
C9
10µF
VAUX
C10
4.7µF
•
FG
R36
•
R19
1k
C8
15nF
250V
M2
IRFL214
FSW
D5
D2
C15
4.7nF
250V
INTVCC
PMODE
TIMER
INTVCC
R35
C1
2.2µF
250V
D3
T2
L1, 15µH
OPTO
VIN
75V TO
150V
0
2
4
6
8
10 12
LOAD CURRENT (A)
14
93
92
91
90
89
VIN = 75V
VIN = 100V
VIN = 125V
VIN = 150V
88
87
16
86
0
2.5
5
7.5
10
LOAD CURRENT (A)
3752 TA08a
12.5
15
3752 TA08b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT8311
Preactive Secondary Synchronous and
Opto Control for Forward Converters
Optimized for Use with Primary-Side LT3752/-1, LT3753 and LT8310 Controllers
LTC3765/LTC3766
Synchronous No-Opto Forward Controller
Chip Set with Active Clamp Reset
Direct Flux Limit, Supports Self Starting Secondary Forward Control
LTC3722/LTC3722-2
Synchronous Full Bridge Controllers
Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable
Synchronous Rectification Timing
LT3748
100V Isolated Flyback Controller
5V ≤ VIN ≤ 100V, No Opto Flyback , MSOP-16 with High Voltage Spacing
LT3798
Off-Line Isolated No-Opto Flyback
Controller with Active PFC
VIN and VOUT Limited Only by External Components
Rev. C
52
06/19
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For more information www.analog.com
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