LTC3853
Triple Output,
Multiphase Synchronous
Step-Down Controller
DESCRIPTION
FEATURES
Triple, 120° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n Configurable as a 180° Dual Phase Controller Plus a
Single Phase Controller
n The Third Phase Can Regulate Up to a 13.5V Output
n High Efficiency: Up to 92%
n R
SENSE or DCR Current Sensing
n ±0.75% 0.8V Output Voltage Accuracy
n Phase-Lockable Fixed Frequency 250kHz to 750kHz
n Supports Pre-Biased Outputs
n Dual N-Channel MOSFET Synchronous Drive
n Wide V Range: 4.5V to 24V Operation (28V Abs Max)
IN
n Adjustable Soft-Start Current Ramping or Tracking
n Foldback Output Current Limiting
n Output Overvoltage Protection
n Dual Power Good Output Voltage Monitors
n 40-Lead 6mm × 6mm QFN Package
The LTC®3853 is a high performance triple output stepdown switching regulator controller that drives all Nchannel synchronous power MOSFET stages. Power loss
and supply noise are minimized by operating the output
stages out of phase. The part can be configured as a dual
phase controller plus a single phase controller if needed.
The part can also be configured to provide a single 3-phase
output for even higher output currents.
n
A wide 4.5V to 24V (28V maximum) input voltage supply range encompasses most battery chemistries and
intermediate bus voltages. Phase 3 can regulate output
voltages up to 13.5V. A constant-frequency current mode
architecture allows for a phase-lockable frequency up to
750kHz.
Independent TK/SS pins for each output ramps the output
voltages and can be configured for coincident or ratiometric
tracking. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. The MODE/PLLIN pin
selects among Burst Mode® operation, pulse-skipping or
continuous inductor current modes.
L, LT, LTC, LTM, Linear Technology, Burst Mode, Polyphase and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678,
6144194, 6177787, 6304066, 6580258.
TYPICAL APPLICATION
High Efficiency Triple 5V/3.3V/1.2V Step-Down Converter
4.7µF
VIN
INTVCC
TG1
PGOOD12
PGOOD3
SW1
2.2µH
fIN
500kHz
0.1µF
SENSE1–
VFB1
105k
1500pF
+
220pF
100µF
10V
20k
15k
BOOST1,2,3
ITH1,2,3
VFB3
SGND
VIN
7V TO 24V
0.1µF
2.2µH
SW1,2,3
1µH
SW2
BG2
0.1µF
SENSE2+
SENSE2–
VFB2
63.4k
10nF
RUN1,2,3
1k
2.2k
MODE/PLLIN
PGND
ILIM
FREQ/PLLFLTR
SENSE1+
VOUT1
5V
5A
TG2
LTC3853
BG1
2.2k
22µF
50V
10k
20k
TG3
SW3
BG3
SENSE3+
SENSE3–
TK/SS1,2,3
0.1µF
+
VOUT2
3.3V
5A
100µF
6V
10k
20k
VOUT3
1.2V
5A
+ 100µF
6V
0.1µF
3853fc
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1
LTC3853
SW1
TG1
BOOST1
RUN3
RUN2
RUN1
MODE/PLLIN
FREQ/PLLFLTR
ILIM
TOP VIEW
TK/SS1
40 39 38 37 36 35 34 33 32 31
TK/SS2 1
30 BG1
TK/SS3 2
29 DRVCC12
SENSE1
+
3
28 BG2
SENSE1– 4
27 SW2
SENSE2+ 5
26 TG2
41
SENSE2– 6
25 BOOST2
SENSE3+ 7
24 VIN
SENSE3– 8
23 EXTVCC
VFB1 9
22 INTVCC
ITH1 10
21 BG3
SW3
TG3
BOOST3
PGOOD12
PGOOD3
ITH3
VFB3
11 12 13 14 15 16 17 18 19 20
ITH2
Input Supply Voltage (VIN).......................... 28V to –0.3V
Topside Driver Voltages
BOOST1, BOOST2, BOOST3................... 34V to –0.3V
Switch Voltage (SW1, SW2, SW3)................. 28V to –5V
INTVCC, RUN1, RUN2, RUN3, PGOOD12, PGOOD3,
DRVCC12, EXTVCC, (BOOST1-SW1),
(BOOST2-SW2), (BOOST3-SW3).................. 6V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
SENSE2– Voltages..................................... 5.7V to –0.3V
SENSE3+, SENSE3–.................................... 14V to –0.3V
VFB2........................................................300µA Max IFB2
MODE/PLLIN, ILIM,TK/SS1,
TK/SS2, TK/SS3 Voltages...................... INTVCC to –0.3V
ITH1, ITH2, ITH3, VFB1, VFB3 Voltages....... INTVCC to –0.3V
INTVCC Peak Output Current.................................150mA
Operating Junction Temperature Range (Note 3)
E-Grade, I-Grade................................. –40°C to 125°C
H-Grade.............................................. –40°C to 150°C
MP-Grade........................................... –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
VFB2
(Note 1)
SGND
ABSOLUTE MAXIMUM RATINGS
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3853EUJ#PBF
LTC3853EUJ#TRPBF
LTC3853UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
LTC3853IUJ#PBF
LTC3853IUJ#TRPBF
LTC3853UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
LTC3853HUJ#PBF
LTC3853HUJ#TRPBF
LTC3853UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 150°C
LTC3853MPUJ#PBF
LTC3853MPUJ#TRPBF
LTC3853UJ
40-Lead (6mm × 6mm) Plastic QFN
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3853fc
2
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LTC3853
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3), VIN = 15V, VRUN1,2,3 = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Channels 1, 2
0.8
TYP
MAX
UNITS
Main Control Loops
Output Voltage Range
Channel 3
VFB1,2,3
IQ
UVLO
Regulated Feedback Voltage
ITH1,2,3 Voltage = 1.2V, –55°C to 150°C (Note 4)
ITH1,2,3 Voltage = 1.2V, –40°C to 125°C (Note 4)
ITH1,2,3 Voltage = 1.2V, 0°C to 85°C (Note 4)
Feedback Current
(Note 4)
Reference Voltage Line Regulation
VIN = 6V to 24V (Note 4)
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop;
DITH Voltage = 1.2V to 0.7V
Measured in Servo Loop;
DITH Voltage = 1.2V to 1.6V
0.8
l
l
0.790
0.792
0.794
VRUN1,2,3
V
13.5
V
0.810
0.808
0.806
V
V
V
–10
–50
nA
0.002
0.02
%/V
l
0.01
0.1
%
l
–0.01
–0.1
%
Transconductance Amplifier gm
ITH1,2,3 = 1.2V, Sink/Source 5µA (Note 4)
2.2
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V
VRUN1,2,3 = 0V
4.1
42
Undervoltage Lockout on INTVCC
VINTVCC Ramping Down
3.35
V
0.5
V
UVLO Hysteresis
ISENSE
0.800
0.800
0.800
5.5
Feedback Overvoltage Lockout
Measured at VFB1,2,3 (H-Grade, MP-Grade)
Measured at VFB1,2,3
Sense Pin Current
VSENSE = 3.3V
Soft-Start Charge Current
VTK/SS1,2,3 = 0V
RUN Pin ON Threshold
VRUN1, VRUN2, VRUN3 Rising
l
l
l
0.84
0.84
70
mA
µA
0.86
0.86
0.89
0.88
V
V
±1
±2
µA
0.9
1.3
1.7
µA
1.1
1.2
1.35
V
RUN Pin Hysteresis
Maximum Current Sense Threshold
mmho
80
mV
ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = 0V
ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = 0V (H-, MPGrade)
l
l
22
21
30
30
38
39
mV
mV
ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = Float
ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = Float (H-, MPGrade)
l
l
42
41
50
50
58
59
mV
mV
ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = INTVCC
ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = INTVCC (H-,
MP-Grade)
l
l
65
64
75
75
85
86
mV
mV
Maximum Duty Factor
In Dropout
TG Driver Pull-Up On-Resistance
TG High
97
98
%
2.6
Ω
TG Driver Pull-Down On-Resistance
TG Low
1.5
Ω
BG Driver Pull-Up On-Resistance
BG High
2.4
Ω
BG Driver Pull-Down On-Resistance
BG Low
1.1
Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
30
ns
Top Gate Off to Bottom Gate On Delay (Note 6)
Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver
3853fc
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LTC3853
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3), VIN = 15V, VRUN1,2,3 = 5V, unless otherwise noted.
SYMBOL
tON(MIN)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bottom Gate Off to Top Gate On Delay (Note 6)
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
Minimum On-Time
90
ns
(Note 7)
INTVCC Linear Regulator
VINTVCC
VEXTVCC
Internal VCC Voltage
7V < VIN < 24V
INTVCC Load Regulation
ICC = 0mA to 50mA
4.8
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
l
4.5
5
5.2
V
0.5
2
%
4.7
30
EXTVCC Hysteresis
V
75
200
mV
mV
Oscillator and Phase-Locked Loop
Nominal Frequency
VFREQ = 1.2V
450
500
550
kHz
Lowest Frequency
VFREQ = 0V
210
250
290
kHz
Highest Frequency
VFREQ ≥ 2.4V
670
750
830
Channel 2-Channel 1 Phase
Channel 3-Channel 2 Phase
Channel 1-Channel 3 Phase
Channel 2-Channel 1 Phase
Channel 3-Channel 2 Phase
Channel 1-Channel 3 Phase
VFB2 Tied to VIN Through 200kΩ
MODE/PLLIN Input Resistance
IFREQ
kHz
120
120
120
Deg
Deg
Deg
180
60
120
Deg
Deg
Deg
250
kΩ
µA
µA
Phase Detector Output Current
Sinking Capability
Sourcing Capability
fMODE < fOSC
fMODE > fOSC
–13
13
PGOOD Voltage Low
IPGOOD = 2mA
0.1
PGOOD Leakage Current
VPGOOD = 5V
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
PGOOD Outputs
IPGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The junction temperature, TJ , is calculated from the ambient
temperature TA and power dissipation PD according to the following
formulas:
LTC3853UJ: TJ = TA + (PD • 33°C/W)
Note 3: The LTC3853 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3853E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3853I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3853H is guaranteed over the –40°C to 150°C
operating junction temperature range and the LTC3853MP is tested and
–5
5
– 7.5
7.5
0.3
V
±2
µA
–10
10
%
%
guaranteed over the –55°C to 150°C operating junction temperature range.
High junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. The maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 4: The LTC3853 is tested in a feedback loop that servos VITH1,2,3 to a
specified voltage and measures the resultant VFB1,2,3.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 6: Rise and fall times are measured using 10% and 90% levels.
Delay times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
3853fc
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LTC3853
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
90
80
80
70
70
40
DCM
EFFICIENCY (%)
50
BURST
CCM
30
20
10
0
0.01
VIN = 12V
VOUT = 1.8V
FIGURE 15 MODIFIED
WITH DCR SENSING
0.1
1
LOAD CURRENT (A)
10
BURST
CCM
DCM
30
10
0.1
1
LOAD CURRENT (A)
EFFICIENCY
1.2
1.0
80
3853 G02
60
0.8
POWER LOSS
75
0.6
VOUT = 3.3V
IOUT = 2A
FIGURE 15 MODIFIED
WITH DCR SENSING
65
10
1.4
85
70
VIN = 12V
VOUT = 3.3V
FIGURE 15 MODIFIED
WITH DCR SENSING
20
3853 G01
1.6
90
50
0
0.01
1.8
95
60
40
2.0
100
EFFICIENCY (%)
100
60
Efficiency and Power Loss
vs Input Voltage
Efficiency vs Output Current
and Mode
0
5
10
20
15
INPUT VOLTAGE (V)
25
POWER LOSS (mW)
EFFICIENCY (%)
Efficiency vs Output Current
and Mode
0.4
0.2
30
0
3853 G03
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
ILOAD
2A/DIV
ILOAD
2A/DIV
IL
2A/DIV
IL
2A/DIV
VOUT
100mV/DIV
AC COUPLED
VOUT
100mV/DIV
AC COUPLED
40µs/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 0A TO 3A
FIGURE 15 CIRCUIT
40µs/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 0A TO 3A
FIGURE 15 CIRCUIT
3853 G04
Load Step
(Pulse Skip Mode)
3853 G05
Inductor Current at Light Load
ILOAD
2A/DIV
FORCED
CONTINUOUS
MODE
2A/DIV
IL
2A/DIV
Burst Mode
OPERATION
2A/DIV
VOUT
100mV/DIV
AC COUPLED
PULSE SKIPPING
MODE
2A/DIV
40µs/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 0A TO 3A
FIGURE 15 CIRCUIT
3853 G06
1µs/DIV
VIN = 12V
VOUT = 1.8V
ILOAD = 100mA
FIGURE 15 CIRCUIT
3853 G07
3853fc
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LTC3853
TYPICAL PERFORMANCE CHARACTERISTICS
Tracking Up and Down
with External Ramp
Coincident Tracking
Prebiased Output at 2V
VOUT
1V/DIV
VTK/SS
500mV/DIV
VFB
500mV/DIV
VOUT1,2,3
1V/DIV
VIN = 12V
VOUT1 = 3.3V
VOUT2 = 2.5V
VOUT3 = 1.8V
Quiescent Current
vs Input Voltage Without EXTVCC
3853 G09
10ms/DIV
VIN = 12V
VOUT1 = 3.3V
VOUT2 = 2.5V
VOUT3 = 1.8V
5.0
4.5
5.25
80
5.00
60
4.75
VSENSE (mV)
5.5
4.50
4.25
5
15
10
20
3.50
25
0
5
10
15
ILIM = GND
20
10
0
1
2
4
3
VSENSE COMMON MODE VOLTAGE (V)
5
3853 G14
1
VITH (V)
1.5
90
80
ILIM = INTVCC
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
10
0
0
20
40
60
DUTY CYCLE (%)
2
Maximum Current Sense Voltage vs
Feedback Voltage (Current Foldback)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
CURRENT SENSE THRESHOLD (mV)
CURRENT SENSE THRESHOLD (mV)
ILIM = FLOAT
0.5
3853 G13
Maximum Current Sense
Threshold vs Duty Cycle
100
ILIM = INTVCC
40
0
0
3853 G12
80
30
ILIM = GND
INPUT VOLTAGE (V)
Maximum Current Sense Threshold
vs Common Mode Voltage
50
20
–40
25
20
3853 G11
60
ILIM = FLOAT
40
–20
INPUT VOLTAGE (V)
70
ILIM = INTVCC
0
4.00
3.75
4.0
3853 G10
5ms/DIV
Current Sense Threshold
vs ITH Voltage
Internal VCC Line Regulation
INTERNAL VCC (V)
SUPPLY CURRENT (mA)
VOUT1,2,3
1V/DIV
3853 G08
50ms/DIV
6.0
RUN1
2V/DIV
TK/SS1
TK/SS2
TK/SS3
2V/DIV
80
100
3853 G15
80
ILIM = INTVCC
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FEEDBACK VOLTAGE (V)
3853 G16
3853fc
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LTC3853
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown (RUN) Threshold
vs Temperature
1.4
1.55
1.3
1.50
1.45
1.40
806
ON
1.2
OFF
1.1
1.0
1.35
0.9
–60 –40 –20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3853 G18
1.30
–60 –40 –20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3853 G17
Oscillator Frequency
vs Temperature
4.25
900
VFREQ = INTVCC
INTVCC VOLTAGE (V)
600
VFREQ = 1.2V
500
400
800
798
796
500
450
RISING
3.75
3.50
FALLING
400
350
3.25
300
802
Oscillator Frequency
vs Input Voltage
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
4.00
700
804
794
–60 –40 –20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3853 G19
FREQUENCY (kHz)
800
FREQUENCY (kHz)
Regulated Feedback Voltage
vs Temperature
REGULATED FEEDBACK VOLTAGE (mV)
1.60
RUN PIN VOLTAGE (V)
TK/SS CURRENT (µA)
TK/SS Pull-Up Current
vs Temperature
VFREQ = 0V
3.00
–50 –25
200
–60 –40 –20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3853 G20
0
300
25 50
75 100 125 150
TEMPERATURE (°C)
30
40
35
30
25
20
5
10
15
20
25
INPUT VOLTAGE (V)
20
–60 –40 –20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3853 G24
5.5
QUIESCENT CURRENT (mA)
SHUTDOWN CURRENT (µA)
INPUT CURRENT (µA)
40
45
25
6.0
55
50
20
Quiescent Current
vs Temperature Without EXTVCC
60
50
15
3853 G22
Shutdown Current
vs Temperature
60
10
INPUT VOLTAGE (V)
3853 G21
Shutdown Current
vs Input Voltage
5
5.0
4.5
4.0
3.5
3.0
–60 –40 –20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3853 G25
3853 G23
3853fc
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LTC3853
PIN FUNCTIONS
SENSE1+, SENSE2+, SENSE3+ (Pins 3, 5, 7): Current Sense
Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks or
current sensing resistors. SENSE3+ common modes up
to 13.5V, allowing higher VOUT voltages on channel 3.
INTVCC (Pin 22): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Also
provides channel 3 driver power. Decouple this pin to
PGND with a minimum of 4.7µF low ESR tantalum or
ceramic capacitor.
SENSE1–, SENSE2–, SENSE3– (Pins 4, 6, 8): Current
Sense Comparator Inputs. The (–) inputs to the current
comparators are connected to the outputs. SENSE3– common modes up to 13.5V, allowing higher VOUT voltages
on channel 3.
EXTVCC (Pin 23): External Power Input to an Internal Switch
Connected to INTVCC. This switch closes and supplies the
IC power, bypassing the internal low dropout regulator,
whenever EXTVCC is higher than 4.7V. Do not exceed 6V
on this pin and ensure VIN > VEXTVCC at all times.
VFB1, VFB2, VFB3 (Pins 9, 12, 14): Error Amplifier Feedback
Inputs. These pins receive the remotely sensed feedback
voltages for each channel from external resistive dividers
across the outputs. Connecting VFB2 to VIN through a 200k
resistor enables dual output (2 + 1) mode.
VIN (Pin 24): Main Input Supply. Decouple this pin to
PGND with a capacitor (0.1µF to 1µF).
ITH1, ITH2, ITH3 (Pins 10, 13, 15): Current Control Thresholds and Error Amplifier Compensation Points. Each associated channels’ current comparator tripping threshold
increases with its ITH control voltage. In dual output
(2 + 1) mode, ITH1 and ITH2 need to be shorted externally.
SGND (Pin 11): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
PGOOD3 (Pin 16): Power Good Indicator Output for Phase
3. Open-drain logic out that is pulled to ground when any
channel output exceeds the ±7.5% regulation window,
after the internal 17µs power bad mask timer expires.
PGOOD12 (Pin 17): Power Good Indicator Output for
Phases 1 and 2. Open-drain logic out that is pulled to
ground when any channel output exceeds the ±7.5%
regulation window, after the internal 17µs power bad
mask timer expires.
DRVCC12 (Pin 29): Driver Voltage Input for Channels 1 and
2. Do not exceed 6V on this pin. This pin must be tied to
INTVCC externally.
BG1, BG2, BG3 (Pins 30, 28, 21): Bottom Gate Driver
Outputs. These pins drive the gates of the bottom Nchannel MOSFETs between PGND and INTVCC/DRVCC12.
SW1, SW2, SW3 (Pins 31, 27, 20): Switch Node Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to VIN.
TG1, TG2, TG3 (Pins 32, 26, 19): Top Gate Driver Outputs.
These are the outputs of floating drivers with a voltage
swing equal to INTVCC superimposed on the switch nodes
voltages.
BOOST1, BOOST2, BOOST3 (Pins 33, 25, 18): Boosted
Floating Driver Supplies. The (+) terminal of the bootstrap capacitors connect to these pins. These pins swing
from a diode voltage drop below INTVCC up to VIN +
INTVCC.
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LTC3853
PIN FUNCTIONS
RUN1, RUN2, RUN3 (Pins 36, 35, 34): Run Control Inputs. A voltage above 1.2V on any RUN pin turns on the
IC. However, forcing any of these pins below 1.2V causes
the IC to shut down the circuitry required for that particular
channel. There are 0.5µA pull-up currents for these pins.
Once the RUN pin rises above 1.2V, an additional 4.5µA
pull-up current is added to the pin.
MODE/PLLIN (Pin 37): Force Continuous Mode, Burst
Mode, or Pulse Skip Mode Selection Pin and External
Synchronization Input to Phase Detector Pin. Connect
this pin to SGND to force all channels into the continuous
mode of operation. Connect to INTVCC to enable pulse
skip mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force
the controller into continuous mode of operation and
synchronize the internal oscillator.
FREQ/PLLFLTR (Pin 38): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can
be driven with a DC voltage to vary the frequency of the
internal oscillator.
ILIM (Pin 39): Current Comparator Sense Voltage Range
Inputs. This pin is to be programmed to SGND, FLOAT or
INTVCC to set the maximum current sense threshold to
three different levels.
TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2): Output Voltage
Tracking and Soft-Start Inputs. When one particular channel
is configured to be the master, a capacitor to ground at
this pin sets the ramp rate for the master channel’s output
voltage. When the channel is configured to be the slave,
the VFB voltage of the master channel is reproduced by a
resistor divider and applied to this pin. Internal soft-start
currents of 1.3µA are charging the soft-start capacitors.
In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to
be shorted externally.
PGND (Exposed Pad Pin 41): Power Ground. Connect this
pin close to the sources of the bottom N-channel MOSFETs,
the (–) terminal of CVCC and the (–) terminal of CIN.
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9
LTC3853
FUNCTIONAL DIAGRAM
FREQ/PLLFLTR
MODE/PLLIN
EXTVCC
VIN
+
4.7V
–
+
F
0.8V
MODE/SYNC
DETECT
–
PLL-SYNC
F
VIN
CIN
5V
REG
+
INTVCC
INTVCC
BOOST
OSC
BURSTEN
S
R
ON
3k
+
–
ICMP
+
–
IREV
CB
TG
FCNT
Q
M1
SW
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
SENSE+
DB
L1
VOUT
SENSE–
+
RUN
OV
M2
CVCC
SLOPE
COMPENSATION
ILIM
PGND
PGOOD
INTVCC
UVLO
+
SLOPE RECOVERY
ACTIVE CLAMP
1
51k
ITHB
–
0.74V
VFB
+
–
–
+
SS
+
–
RUN
–
+
R2
R1
OV
0.86V
SGND
1.3µA
EA
– + +
0.8V
REF
UV
SLEEP
VIN
COUT
BG
0.64V
1.2V
0.5µA
0.55V
ITH
RC
CC1
RUN
TK/SS
CSS
3853 FD
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LTC3853
OPERATION
Main Control Loop
The LTC3853 is a constant-frequency, current mode
step-down controller with three channels operating 120
degrees out-of-phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, ICMP , resets the RS latch. The peak inductor
current at which ICMP resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of each error
amplifier, EA. The VFB pin receives the voltage feedback
signal, which is compared to the internal reference voltage
by the EA. When the load current increases, it causes a
slight decrease in VFB relative to the 0.8V reference, which
in turn causes the ITH voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator IREV , or the
beginning of the next cycle.
INTVCC/EXTVCC/DRVCC12 Power
Power for the top and bottom MOSFET drivers of phase 3
and most other internal circuitry is derived from the
INTVCC pin. DRVCC12 provides driver power for phase 1
and phase 2. This pin must be externally tied to INTVCC.
If EXTVCC is taken above 4.7V, the 5V regulator is turned
off and an internal switch is turned on connecting EXTVCC.
Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one
of the LTC3853 switching regulator outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If the input voltage, VIN, decreases to a voltage
close to VOUT, the loop may enter dropout and attempt to
turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about
one-twelfth of the clock period every fifth cycle to allow
CB to recharge. However, it is recommended that there is
always a load be present during the dropout transition to
ensure CB is recharged.
Shutdown and Start-Up (RUN1, RUN2, RUN3 and TK/
SS1, TK/SS2, TK/SS3 Pins)
The three channels of the LTC3853 can be independently
shut down using the RUN1, RUN2 and RUN3 pins. Pulling
any of these pins below 1.2V shuts down the main control
loop for that controller. Pulling all pins low disables all
three controllers and most internal circuits, including the
INTVCC regulator. Releasing any RUN pin allows an internal
0.5µA current to pull up the pin and enable that controller.
Alternatively, the RUN pin may be externally pulled up
or driven directly by logic. Be careful not to exceed the
absolute maximum rating of 6V on this pin.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the TK/SS1, TK/SS2 and
TK/SS3 pins. When the voltage on the TK/SS pin is less
than the 0.8V internal reference, the LTC3853 regulates
the VFB voltage to the TK/SS pin voltage instead of the
0.8V reference. This allows the TK/SS pin to be used to
program a soft-start by connecting an external capacitor
from the TK/SS pin to SGND. An internal 1.3µA pull-up
current charges this capacitor, creating a voltage ramp on
the TK/SS pin. As the TK/SS voltage rises linearly from
0V to 0.8V (and beyond), the output voltage VOUT rises
smoothly from zero to its final value. Alternatively the TK/
SS pin can be used to cause the start-up of VOUT to “track”
that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the
other supply to ground (see the Applications Information
section). When the corresponding RUN pin is pulled low
to disable a controller, or when INTVCC drops below its
undervoltage lockout threshold of 3.35V, the TK/SS pin
is pulled low by an internal MOSFET. When in undervoltage lockout, all controllers are disabled and the external
MOSFETs are held off.
Light Load Current Operation (Burst Mode Operation,
Pulse Skipping or Continuous Conduction)
The LTC3853 can be enabled to enter high efficiency Burst
Mode operation, constant-frequency pulse skipping mode,
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
voltage below 0.8V (e.g., SGND). To select pulse skipping
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11
LTC3853
OPERATION
mode of operation, tie the MODE/PLLIN pin to INTVCC. To
select Burst Mode operation, float the MODE/PLLIN pin.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.5V, the internal
sleep signal goes high (enabling sleep mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When the controller
is enabled for Burst Mode operation, the inductor current
is not allowed to reverse. The reverse current comparator
(IREV) turns off the bottom external MOSFET just before the
inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous mode has the advantages of lower output
ripple and less interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTVCC, the
LTC3853 operates in PWM pulse skipping mode at light
loads. At very light loads, the current comparator, ICMP ,
may remain tripped for several cycles and force the external
top MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of
the LTC3853’s controllers can be selected using the FREQ/
PLLFLTR pin. If the MODE/PLLIN pin is not being driven
by an external clock source, the FREQ/PLLFLTR pin can
be used to program the controller’s operating frequency
from 250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3853
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized. A series R-C should be connected
between the FREQ/PLLFLTR pin and SGND to serve as
the PLL’s loop filter.
Power Good (PGOOD12 and PGOOD3 Pins)
The PGOOD12 pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD12 pin low when either VFB1 or VFB2 pin
voltage is not within ±7.5% of the 0.8V reference voltage.
The PGOOD12 pin is also pulled low when either RUN1
or RUN2 pin is below 1.2V or when the LTC3853 is in the
soft-start or tracking phase. When the VFB pin voltage
is within the ±7.5% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source of up to 6V. The PGOOD12 pin will
flag power good immediately when both VFB1 and VFB2
pins are within the ±7.5% window. However, there is an
internal 17µs power bad mask when either VFB is out of
the ±7.5% window. PGOOD3 monitors VFB3 and is also
pulled low when RUN3 is below 1.2V.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
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LTC3853
OPERATION
Triple vs Dual (2 + 1) Operation
The LTC3853 can be used to regulate three different outputs. It can also be used as a dual output controller with
a high current 2-phase output and a single phase output.
Tying VFB2 to VIN through a 200k resistor switches the
controller from triple to dual (2 + 1) operation. Do not exceed the absolute maximum current rating for the VFB2 pin.
In dual (2 + 1) mode, phase 1 and phase 2 are 180 degrees
apart (instead of 120 degrees) with phase 3 remaining at
240 degrees from phase 1. The ITH1 and ITH2 pins must be
shorted together externally and so must the TK/SS1 and
TK/SS2 pins for proper operating of the 2 phase portion
of the controller. RUN2 should be grounded. RUN1 will
now control both phases 1 and 2, while RUN3 continues
to control the turn on of phase 3.
Phase 3 is also capable of regulating up to a 13.5V output
in either mode, while phases 1 and 2 are limited to a 5.3V
output.
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3853
application circuit. LTC3853 can be configured to use either
DCR (inductor resistance) sensing or low value resistor
sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption, and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resistors and is more power efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is
used) and inductor value. Next, the power MOSFETs are
selected. Finally, input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is either
grounded, floated or tied to INTVCC, the typical value for
the maximum current sense threshold will be 30mV, 50mV
or 75mV, respectively.
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will
allow for the use of very low DCR inductors or sense
resistors, but at the expense of current limit accuracy.
The 50mV setting is a good balance between the two. For
single output dual phase applications ((2 + 1) mode), use
the 50mV or 75mV setting for optimal current sharing.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5.3V for phases 1 and
2, and 0V to 13.5V for phase 3. Both SENSE pins are high
impedance inputs with small base currents of less than
1µA. When the SENSE pins ramp up from 0V to 1.4V, the
small base currents flow out of the SENSE pins. When
the SENSE pins ramp down from the maximum common
mode voltage to 1.1V, the small base currents flow into
the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However,
care must be taken not to float these pins during normal
operation.
Filter components mutual to the sense lines should be
placed close to the LTC3853, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
TO SENSE FILTER,
NEXT TO THE CONTROLLER
COUT
INDUCTOR OR RSENSE
3853 F01
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
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13
LTC3853
APPLICATIONS INFORMATION
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
close to the switching node, to prevent noise from coupling
into sensitive small-signal nodes. The capacitor C1 should
be placed close to the IC pins.
VIN
INTVCC
VIN
BOOST
TG
RSENSE
L1
SW
LTC3853
RS
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold sets the peak of the inductor current,
yielding a maximum average output current IMAX equal to
the peak value less half the peak-to-peak ripple current,
DIL. To calculate the sense resistor value, use the equation:
ESL
RSENSE =
BG
PGND
SENSE+
SENSE–
SGND
RF
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 15mV ∆VSENSE voltage is recommended
as a conservative number to start with, either for RSENSE
or DCR sensing applications.
CF RF
FILTER COMPONENTS
PLACED NEAR SENSE PINS
3853 F02a
(2a) Using a Resistor to Sense Current
VIN
INTVCC
VIN
BOOST
INDUCTOR
TG
LTC3853
L
SW
DCR
VOUT
BG
PGND
R1
SENSE+
C1*
R2
SENSE–
SGND
*PLACE C1 NEAR SENSE+,
SENSE– PINS
R1||R2 • C1 =
L
R2
RSENSE(EQ) = DCR
DCR
R1 + R2
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
VSENSE(MAX)
∆I
I(MAX) + L
2
3853 F02b
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
the LTC1628 / LTC3728 family) that the voltage drop across
the parasitic inductance of the sense resistor represented
a relatively small error. For today’s highest current density
solutions, however, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be as low
as 20mV. In addition, inductor ripple currents greater than
50% with operation up to 1MHz are becoming more common. Under these conditions the voltage drop across the
sense resistor’s parasitic inductance is no longer negligible.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of capacitive and inductive noise coupled in
the sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
This same RC filter, with minor modifications, can be
used to extract the resistive component of the current
sense signal in the presence of parasitic inductance.
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LTC3853
APPLICATIONS INFORMATION
For example, Figure 3 illustrates the voltage waveform
across a 2mΩ sense resistor with a 2010 footprint for the
1.2V/15A converter operating at 100% load. The waveform
is the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
ESL =
VESL(STEP) tON • tOFF
∆IL
tON + tOFF
If the RC time constant is chosen to be close to the parasitic
inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 4.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
VSENSE
20mV/DIV
VESL(STEP)
500ns/DIV
3853 F03
Figure 3. Voltage Waveform Measured
Directly Across The Sense Resistor
VSENSE
20mV/DIV
500ns/DIV
3853 F04
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
the equation above to determine the ESL. However, do not
over-filter. Keep the RC time constant less than or equal
to the inductor time constant to maintain a high enough
ripple voltage on VRSENSE.
The above generally applies to high density/high current
applications where I(MAX) > 10A and low values of inductors are used. For applications where I(MAX) < 10A, set
RF to 10Ω and CF to 1000pF. This will provide a good
starting point.
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin connected to the sense
resistor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3853 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost several points of efficiency compared to DCR sensing.
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
Figure 4. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω
RSENSE(EQUIV) =
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VSENSE(MAX)
∆I
I(MAX) + L
2
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LTC3853
APPLICATIONS INFORMATION
To ensure that the application will deliver full load current over the full operating temperature range, choose
the minimum value for the Maximum Current Sense
Threshold (VSENSE(MAX)) in the Electrical Characteristics
table (22mV, 42mV, or 65mV, depending on the state of
the ILIM pin).
Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually
given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RSENSE(EQUIV)
RD =
DCR(MAX) at TL(MAX)
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1||R2 to around 2kΩ, reducing
error that might have been caused by the SENSE pins’
±1µA current.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1|| R2 =
(DCR at 20°C) • C1
The sense resistor values are:
IN(MAX)
)
− VOUT • VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
16
∆VSENSE =
VIN – VOUT
VOUT
•
R1• C1
VIN • fOSC
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constantfrequency architectures by preventing subharmonic
oscillations at high duty cycles. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
this results in a reduction of maximum inductor peak current for duty cycles >40%. However, the LTC3853 uses
a patented scheme that counteracts this compensating
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
(V
R1|| R2
R1• RD
R1=
; R2 =
RD
1− RD
PLOSS R1=
However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at
heavy loads. Peak efficiency is about the same with either
method. To maintain a good signal-to-noise ratio for the
current sense signal, use a minimum ∆VSENSE of 10mV
to 15mV. For a DCR sensing application, the actual ripple
voltage will be determined by:
IRIPPLE =
VOUT VIN – VOUT
VIN fOSC • L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L ≥ VIN – VOUT • VOUT
fOSC •IRIPPLE VIN
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3853fc
LTC3853
APPLICATIONS INFORMATION
Inductor Core Selection
Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
The peak-to-peak drive levels are set by the INTVCC/
DRVCC12 voltage. This voltage is typically 5V during startup (see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
Synchronous Switch Duty Cycle =
VIN – VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
( ) (1+ δ )R
VOUT
IMAX
VIN
2
DS(ON) +
IMAX
(RDR )(CMILLER ) •
2
( VIN )2
1
1
+
• fOSC
VINTVCC – VTH(MIN) VTH(MIN)
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3853: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
VOUT
VIN
PSYNC =
VIN – VOUT
2
IMAX ) (1+ δ )RDS(ON)
(
VIN
where d is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
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LTC3853
APPLICATIONS INFORMATION
The optional Schottky diodes conduct during the dead time
between the conduction of the two power MOSFETs. These
prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
Soft-Start and Tracking
The LTC3853 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
external supply. When one particular channel is configured
to soft-start by itself, a capacitor should be connected to
its TK/SS pin. This channel is in the shutdown state if its
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1.3µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.8V on the
TK/SS pin. The total soft-start time can be calculated as:
tSOFTSTART = 0.8 •
CSS
1.3µA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse skipping mode up
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.74V. The output ripple is
minimized during the 100mV forced continuous mode
window ensuring a clean PGOOD signal.
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the
ramp rate of the other supply’s voltage. Note that the
small soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider value to be small
enough to make this error negligible.
In order to track down another channel or supply after
the soft-start phase expires, the LTC3853 is forced into
continuous mode of operation as soon as VFB is below the
undervoltage threshold of 0.74V regardless of the setting
of the MODE/PLLIN pin. However, the LTC3853 should
always be set in force continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, its
channel will operate in discontinuous mode.
Output Voltage Tracking
The LTC3853 allows the user to program how its output ramps up and down by means of the TK/SS pins.
Through these pins, the output can be set up to either coincidentally or ratiometrically track another
supply’s output, as shown in Figure 5. In the following
discussions, VOUT1 refers to the LTC3853’s output 1 as a
master channel and VOUT2 refers to the LTC3853’s output 2
as a slave channel. In practice though, any phase can be
used as the master. To implement the coincident tracking in Figure 5a, connect an additional resistive divider to
VOUT1 and connect its midpoint to the TK/SS pin of the
slave channel. The ratio of this divider should be the same
as that of the slave channel’s feedback divider shown in
Figure 6a. In this tracking mode, VOUT1 must be set higher
than VOUT2. To implement the ratiometric tracking, the ratio
of the slave’s divider should be exactly the same as the
master channel’s feedback divider. By selecting different
resistors, the LTC3853 can achieve different modes of
tracking including the two in Figure 5.
So which mode should be programmed? While either
mode in Figure 6 satisfies most practical applications, there
are some trade-offs. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. This can be better understood with the help
of Figure 7. At the input stage of the slave channel’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
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VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME
VOUT2
TIME
3853 F05a
(5a) Coincident Tracking
3853 F05b
(5b) Ratiometric Tracking
Figure 5. Two Different Modes of Output Voltage Tracking
VOUT1
VOUT2
TO
TK/SS2
PIN
R3
R1
R4
R2
TO
VFB1
PIN
R3
TO
VFB2
PIN
R4
VOUT1
VOUT2
TO
TK/SS2
PIN
R1
TO
VFB1
PIN
R2
TO
VFB2
PIN
R3
R4
3853 F06
(6a) Coincident Tracking Setup
(6b) Ratiometric Tracking Setup
Figure 6. Setup for Coincident and Ratiometric Tracking
I
I
+
TK/SS2
0.8V
D1
D2
EA2
–
3853 F07
of output voltage deviation. Furthermore, when the master
channel’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
INTVCC Regulators and EXTVCC
D3
VFB2
Figure 7. Equivalent Input Circuit of Error Amplifier
coincident mode, the TK/SS voltage is substantially higher
than 0.8V at steady state and effectively turns off D1. D2
and D3 will therefore conduct the same current and offer
tight matching between VFB2 and the internal precision
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady state. D1 will divert part of the bias
current to make VFB2 slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
The LTC3853 features an NPN linear regulator that supplies
power to INTVCC from the VIN supply. INTVCC powers the
gate drivers and much of the LTC3853’s internal circuitry.
The linear regulator regulates the voltage at the INTVCC pin
to 5V when VIN is greater than 6.5V. EXTVCC connects to
INTVCC through a P-channel MOSFET and can supply the
needed power when its voltage is higher than 4.7V. Each
of these can supply a peak current of 150mA and must
be bypassed to ground with a minimum of 1µF ceramic
capacitor or low ESR electrolytic capacitor. No matter
what type of bulk capacitor is used, an additional 0.1µF
ceramic capacitor placed directly adjacent to the INTVCC
and PGND pins is highly recommended. Good bypassing
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LTC3853
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is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3853 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5V linear
regulator or EXTVCC. When the voltage on the EXTVCC pin
is less than 4.7V, the linear regulator is enabled. Power
dissipation for the IC in this case is highest and is equal
to VIN • IINTVCC. The gate charge current is dependent
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can
be estimated by using the equations given in Note 3 of
the Electrical Characteristics. For example, the LTC3853
INTVCC current is limited to less than 50mA from a 24V
supply in the UJ package and not using the EXTVCC supply:
TJ = 85°C + (50mA)(24V)(33°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN =
SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC linear regulator is turned
off and the EXTVCC is connected to the INTVCC. The EXTVCC
remains on as long as the voltage applied to EXTVCC remains
above 4.5V. Using the EXTVCC allows the MOSFET driver
and control power to be derived from one of the LTC3853’s
switching regulator outputs during normal operation and
from the INTVCC when the output is out of regulation
(e.g., start-up, short-circuit). If more current is required
through the EXTVCC than is specified, an external Schottky
diode can be added between the EXTVCC and INTVCC pins.
Do not apply more than 6V to the EXTVCC pin and make
sure that EXTVCC < VIN.
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive INTVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause
INTVCC to be powered from the internal 5V regulator
resulting in an efficiency penalty of up to 10% at high
input voltages.
2. EXTVCC connected directly to VOUT. This is the
normal connection for a 5V regulator and provides
the highest efficiency.
3. EXTVCC connected to an external supply. If a 5V
external supply is available, it may be used to power
EXTVCC providing it is compatible with the MOSFET
gate drive requirements.
4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators,
efficiency gains can still be realized by connecting
EXTVCC to an output-derived voltage that has been
boosted to greater than 4.7V.
For applications where the main input power is 5V, tie
the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 8 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET
which is typically 4.5V for logic-level devices.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
LTC3853
VIN
INTVCC
RVIN
1Ω
CINTVCC
4.7µF
+
5V
CIN
3853 F08
Figure 8. Setup for a 5V Input
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 85°C + (50mA)(5V)(33°C/W) = 94°C
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Topside MOSFET Driver Supply (CB, DB)
CIN and COUT Selection
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged
though external diode, DB, from INTVCC when the SW
pin is low. When one of the topside MOSFETs is to be
turned on, the driver places the CB voltage across the
gate source of the desired MOSFET. This enhances the
MOSFET and turns on the topside switch. The switch
node voltage, SW, rises to VIN and the BOOST pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply: VBOOST = VIN + VINTVCC. The value of
the boost capacitor, CB, needs to be 100 times that of
the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external Schottky diode
must be greater than VIN(MAX). When adjusting the gate
drive level, the final arbiter is the total input current for
the regulator. If a change is made and the input current
decreases, then the efficiency has improved. If there is
no change in input current, then there is no change in
efficiency.
The selection of CIN is simplified by the 3-phase architecture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controllers will actually decrease the input
RMS ripple current from its maximum value. The out-ofphase technique typically reduces the input capacitor’s
RMS ripple current by a factor of 30% to 70% when
compared to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
Undervoltage Lockout
The LTC3853 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTVCC is below
3.35V. To prevent oscillation when there is a disturbance
on the INTVCC, the UVLO comparator has 500mV of precision hysteresis.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pins have a
precision turn-on reference of 1.2V, one can use a
resistor divider to VIN to turn on the IC when VIN is
high enough. An extra 4.5µA of current flows out of the
RUN pin once the RUN pin voltage passes 1.2V. One
can program the hysteresis of the run comparator by
adjusting the values of the resistive divider. For accurate
VIN undervoltage detection using the RUN pin, VIN needs
to be higher than 4V.
IMAX
V IN
1/2
( VOUT ) ( VIN – VOUT )
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3853, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3853 3-phase operation can be calculated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if all controller channels switched on at the same
time. The total RMS power lost is lower when more than
one controller is operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
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LTC3853
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dual or triple controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 3-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3853, is also
suggested. A 2.2Ω to 10Ω resistor placed between CIN and
the VIN pin provides further isolation between the channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (DVOUT) is approximated by:
1
∆VOUT ≈ IRIPPLE ESR +
8fCOUT
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
The LTC3853 output voltages are each set by an external
feedback resistive divider carefully placed across the output, as shown in Figure 9. The regulated output voltage
is determined by:
R
VOUT = 0.8V • 1+ B
RA
To improve the frequency response, a feed-forward capacitor, CFF , may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
VOUT
RB
1/3 LTC3853
CFF
VFB
RA
3853 F09
Figure 9. Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3853 includes current foldback to help limit load
current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3853 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The shortcircuit ripple current is determined by the minimum ontime tON(MIN) of the LTC3853 (≈ 90ns), the input voltage
and inductor value:
∆IL(SC) = tON(MIN) •
VIN
L
The resulting short-circuit current is:
ISC =
1/3 VSENSE(MAX)
RSENSE
–
1
∆I
2 L(SC)
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Phase-Locked Loop and Frequency Synchronization
The LTC3853 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The phase
detector is an edge sensitive digital type that provides
zero degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
specified in the Electrical Characteristics table. Note that
the LTC3853 can only be synchronized to an external
clock whose frequency is within range of the LTC3853’s
internal VCO. This is guaranteed to be between 250kHz and
750kHz. A simplified block diagram is shown in Figure 11.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, or if the external clock’s phase
lags the internal oscillator, then current is sourced from
the phase detector output, pulling up the FREQ/PLLFLTR
pin. When the external clock frequency is less than fOSC,
or if the external clock’s phase leads the internal oscillator, current is sunk, pulling down the FREQ/PLLFLTR pin.
The voltage on the FREQ/PLLFLTR pin is adjusted until the
phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase
detector output is high impedance and the filter capacitor,
CLP , holds the voltage.
The loop filter components, CLP and RLP , smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low threshold
is 1V.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3853 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
V
tON(MIN) < OUT
VIN (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
2.4V
800
RLP
FREQUENCY (kHz)
700
600
EXTERNAL
OSCILLATOR
500
MODE/
PLLIN
CLP
FREQ/
PLLFLTR
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
400
300
200
0
0.5
1
1.5
2
FREQ/PLLFLTR PIN VOLTAGE (V)
3853 F11
2.5
3853 F10
Figure 11. Phase-Locked Loop Block Diagram
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
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LTC3853
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The minimum on-time for the LTC3853 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV to 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. However, as the peak sense voltage decreases the
minimum on-time gradually increases to 130ns. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with
correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3853 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typically results in a small (1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
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LTC3853
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PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 12 illustrates the current waveforms present in the various branches of the 3-phase synchronous
regulators operating in the continuous mode. Check the
following in your layout:
1. Are the top N-channel MOSFETs located within 1 cm of
each other with a common drain connection at CIN? Do
not attempt to split the input decoupling for the three
channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as
possible. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have
short leads and PC trace lengths. The output capacitor
(–) terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3853 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE+ and SENSE– leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor or inductor,
whichever is used for current sensing.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers current
peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW), top gate nodes (TG),
and boost nodes (BOOST) away from sensitive smallsignal nodes, especially from another channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the “output side” of the LTC3853
and occupy minimum PC trace area. If DCR sensing
is used, place the top resistor (Figure 2b, R1) close to
the switching node.
7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
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SW1
L1
VOUT1
RSENSE1
COUT1
D1
SW2
VIN
RIN
+
L2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENTS.
KEEP LINES TO A
MINIMUM LENGTH.
COUT2
D2
SW3
L3
+
RL2
VOUT3
RSENSE3
D3
RL1
VOUT2
RSENSE2
CIN
+
COUT3
+
RL3
3853 F12
Figure 12. Branch Current Waveforms
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LTC3853
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PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope to
the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if
regulator bandwidth optimization is not required. Only after
each controller is checked for its individual performance
should all controllers be turned on at the same time. A
particularly difficult region of operation is when one controller channel is nearing its current comparator trip point
when another channel is turning on its top MOSFET. This
occurs around 33% and 66% duty cycle on a channel in
triple mode, due to the phasing of the internal clocks and
may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
28
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Design Example
As a design example for a three channel medium current regulator, assume VIN = 12V(nominal), VIN =
20V(maximum), VOUT1 = 5V, VOUT2 = 3.3V, VOUT3 = 1.2V,
IMAX1,2,3 = 5A, and f = 500kHz (see Figure 13).
The regulated output voltages are determined by:
R
VOUT = 0.8V • 1+ B
RA
Using 20k 1% resistors from both VFB nodes to ground,
the top feedback resistors are (to the nearest 1% standard
value) 105k, 63.4k and 10k.
The minimum on-time occurs on channel 3 at the maximum
VIN, and should not be less than 90ns:
tON (MIN) =
VOUT
V IN (MAX) f
=
1.2V
= 120ns
20V(500kHz)
The frequency is set by biasing the FREQ/PLLFLTR pin to
1.2V (see Figure 10), using a divider from INTVCC. This
voltage will decrease as VIN approaches 5V, lowering the
switching frequency. If a separate 5V supply is connected
to EXTVCC, INTVCC will remain at 5V even if VIN decreases.
The inductance values are based on a 35% ripple current
assumption (1.75A for each channel) at nominal input
voltage:
VOUT
VOUT
L=
1−
f • ∆IL(NOM)
V IN(NOM)
Channel 1 will require 3.3µH, channel 2 will require 2.8µH
and channel 3 will require 1.25µH. The next highest
standard values are 3.3µH, 3.3µH and 1.5µH. At the
maximum input voltage (20V), the ripple will be:
∆IL(MAX) =
For more information www.linear.com/LTC3853
VOUT
f •L
VOUT
1−
VIN(MAX)
3853fc
LTC3853
APPLICATIONS INFORMATION
4.7µF
M1
VIN DRVCC12 INTVCC
TG2
TG1
PGOOD12
PGOOD3
SW1
3.3µH
+
0.1µF
1430Ω
SENSE1–
VFB1
105k
1%
10pF
+
330µF
10V
ITH1,2,3
RITH1,2,3
CP1,2,3
20k
1%
CITH1,2,3
M2
VIN
7V TO 20V
M3
CB1,2,3 0.1µF
3.3µH
SW1,2,3
SW2
1.5µH
4.75k
0.1µF
BG2
PGND
MODE/PLLIN
ILIM
FREQ/PLLFLTR
SENSE1
VOUT1
5V
5A
DB1,2,3
BOOST1,2,3
LTC3853
BG1
4.75k
22µF
50V
10k
SENSE2+
–
INTVCC
SENSE2
VFB2
1430Ω
63.4k
1%
RUN1,2,3
3.16k
1nF
TG3
SW3
BG3
SGND
SENSE3+
EXTVCC
SENSE3–
TK/SS1,2,3
2.43k
0.068µF
10pF
20k
1%
VFB3
1.82k
VOUT2
3.3V
5A
+
VOUT3
1.2V
5A
10k
1%
330µF
6V
20k
1%
+
330µF
6V
CSS1,2,3
0.1µF
3853 F13
M1, M2, M3: Si4816BDY
CHANNEL 1: RITH1 = 15k, CITH1 = 1.5nF, CP1 = 220pF
CHANNEL 2: RITH2 = 18k, CITH2 = 1.5nF, CP2 = 220pF
CHANNEL 3: RITH3 = 10k, CITH3 = 1.5nF, CP3 = 330pF
FOR CHANNEL 3, 0.068µF WAS SUBSTITUTED FOR 0.1µF AND 2.43k WAS SUBSTITUTED
FOR 2.21k TO MEET MINIMUM 15mV RIPPLE AT SENSE INPUT REQUIREMENT
Figure 13. High Efficiency Triple 5V/3.3V/1.2V Step-Down Converter
Channel 1 will have ~2.3A (46%) ripple, and both channel
2 and channel 3 will have ~1.75A (35%) ripple. The peak
inductor current will be the maximum DC value plus onehalf the ripple current, or 6.15A for channel 1 and 5.88A
for channels 2 and 3.
The Vishay IHLP2525CZER3R3M01 (30mΩ DCRMAX at
20°C) and IHLP2525CZER1R5M01 (15mΩ DCRMAX at
20°C,) are chosen. At 100°C, the estimated maximum DCR
values are 39.6mV and 19.8mV. The divider ratios are:
RD =
With ILIM high, the equivalent RSENSE resistor value can be
calculated by using the minimum value for the maximum
current sense threshold (65mV).
VSENSE(MIN)
∆IL(NOM)
ILOAD(MAX) +
2
65mV
=
≅ 9mΩ
∆IL(MAX)
1.2 • 5A +
2
RSENSE(EQUIV) =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
and
=
9mΩ
= 0.23;
39.6mΩ
9mΩ
≅ 0.45
19.8mΩ
For each channel, 0.1µF is selected for C1.
R1|| R2 =
(DCRMAX
L
3.3µH
=
at 20°C) • C1 30mΩ • 0.1µF
= 1100Ω and
1.5µH
= 1000Ω
15mΩ • 0.1µF
The 1.2 factor adds margin for component variation and
overcurrent headroom during full load transients.
The equivalent RSENSE is the same for channels 1, 2 and 3.
3853fc
For more information www.linear.com/LTC3853
29
LTC3853
APPLICATIONS INFORMATION
For channel 1, the DCRSENSE filter/divider values are:
R1=
R1|| R2 1100Ω
=
≅ 4.75k;
RD
0.23
R2 =
R1• RD 4.75k • 0.23
=
≅ 1430Ω
1− 0.23
1− RD
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Siliconix Si4816BDY dual MOSFET
results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER @ 100pF.
At maximum input voltage with T(estimated) = 50°C:
5V
(5)2 [1+ (0.005)(50°C – 25°C)] •
20V
5A
(0.023Ω ) + (20V )2 (2Ω )(100pF ) •
2
PMAIN =
The power loss in R1 at the maximum input voltage is:
PLOSS R1=
(VIN(MAX) − VOUT ) • VOUT
R1
(20V − 5V) • 5V
=
= 15.8mW
4.75k
The respective values for Channel 2 are R1 = 4.75k, R2 =
1430Ω; and PLOSSR1 = 11.6mW. And for Channel 3 are
R1 = 2.21k, R2 = 1.82k; and PLOSSR1 = 10.2mW.
Burst Mode operation is chosen for high light load efficiency
(Figure 14) by floating the MODE/PLLIN pin. Power loss
due to the DCR sensing network is slightly higher at light
loads than would have been the case with a suitable sense
resistor (9mΩ). At heavier loads, DCR sensing provides
higher efficiency.
100
EFFICIENCY (%)
1
DCR
0.1
60
40
0.01
EFFICIENCY
POWER LOSS
0.1
1
LOAD CURRENT (A)
10
0.01
POWER LOSS (mW)
9mΩ
70
50
ISC =
(1/ 3) 75mV – 1 90ns(20V) = 2.5A
0.009Ω
2
3.3µH
with a typical value of RDS(ON) and d = (0.005/°C)(25)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
20V – 5V
(2.5A )2 (1.125)(0.016Ω )
20V
= 84mW
PSYNC =
which is less than under full-load conditions.
90
80
A short-circuit to ground will result in a folded back current of:
10
DCR
1
1
5 – 2.3 + 2.3 ( 500kHz ) = 243mW
CIN is chosen for an RMS current rating of at least 2A at
temperature assuming only one channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (DIL) = 0.02Ω(1.5A) = 30mVP-P
3853 F14
Figure 14. Design Example Efficiency vs Load
3853fc
30
For more information www.linear.com/LTC3853
LTC3853
APPLICATIONS INFORMATION
4.7µF
M1
VIN DRVCC12 INTVCC
TG1
PGOOD12
PGOOD3
SW1
1.5µH
VOUT1
2.5V
5A
+
SENSE1
1000pF*
SENSE1–
VFB1
43.2k
1%
10pF
ITH1,2,3
RITH1,2,3
CP1,2,3
+
220µF
4V
20k
1%
CITH1,2,3
M2
M3
CB1,2,3 0.1µF
1.5µH
SW1,2,3
2.2µH
SW2
BG2
PGND
MODE/PLLIN
ILIM
FREQ/PLLFLTR
10Ω*
DB1,2,3
BOOST1,2,3
LTC3853
BG1
0.008Ω
5%
10Ω*
TG2
VIN
7V TO 24V
33µF
35V
10k
SENSE2+
10Ω*
INTVCC
10Ω*
1000pF*
SENSE2–
24.9k
1%
VFB2
RUN1,2,3
3.16k
TG3
SW3
BG3
SGND
SENSE3+
EXTVCC
SENSE3–
TK/SS1,2,3
0.008Ω
5%
10Ω*
1000pF
20k
1%
VFB3
1000pF*
10Ω*
VOUT2
1.8V
5A
+
0.008Ω
5%
VOUT3
3.3V
5A
63.4k
1%
10pF
220µF
4V
20k
1%
+
220µF
4V
CSS1,2,3
0.1µF
M1, M2, M3: Si4816BDY
CHANNEL 1: RITH1 = 18k, CITH1 = 1500pF, CP1 = 220pF
CHANNEL 2: RITH2 = 12k, CITH2 = 1500pF, CP2 = 220pF
CHANNEL 3: RITH3 = 18k, CITH3 = 1500pF, CP3 = 220pF
3853 F15
*THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC
Figure 15. Triple 2.5V/1.8V/3.3V 5A Step-Down Converter with RSENSE, fSW = 500kHz
3853fc
For more information www.linear.com/LTC3853
31
LTC3853
TYPICAL APPLICATIONS
Triple 3.3V/2.5V/12V, 5A Step-Down Converter with RSENSE Synchronized at 400kHz
4.7µF
M1
VIN DRVCC12 INTVCC
TG1
PGOOD12
PGOOD3
SW1
3.3µH
TG2
ILIM
0.008Ω
5%
10Ω*
1000pF*
BG2
PLLIN
400kHz
SENSE1+
SENSE2+
MODE/PLLIN
SENSE2–
SENSE1–
6.8µH
0.008Ω
5%
10Ω*
10Ω*
RITH1,2,3
43.2k
1%
RUN1,2,3
10pF
+
20k
1%
1000pF
10k
TG3
SW3
BG3
SGND
SENSE3+
EXTVCC
SENSE3–
TK/SS1,2,3
CITH1,2,3
CSS1,2,3
0.1µF
1000pF*
10Ω*
VOUT2
2.5V
5A
VFB3
CP1,2,3
20k
1%
10Ω*
1000pF*
VFB2
ITH1,2,3
220µF
4V
2.2µH
SW1,2,3
PGND
VFB1
63.4k
1%
10pF
+
M3
FREQ/PLLFLTR
10Ω*
VOUT1
3.3V
5A
M2
CB1,2,3 0.1µF
SW2
LTC3853
BG1
DB1,2,3
BOOST1,2,3
VIN
13V TO 24V
33µF
35V
0.011Ω
5%
VOUT3
12V
4A
140k
1%
22pF
220µF
4V
+
10k
1%
220µF
16V
10nF
3853 TA02
M1, M2, M3: Si4816BDY
CHANNEL 1: RITH1 = 18k, CITH1 = 1500pF, CP1 = 220pF
CHANNEL 2: RITH2 = 18k, CITH2 = 1500pF, CP2 = 220pF
CHANNEL 3: RITH3 = 43k, CITH3 = 470pF, CP3 = 330pF
*THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC
Triple 1.8V/1.2V/2.5V, 15A High Current Step-Down Converter with RSENSE, fSW = 400kHz
4.7µF
M1
0.56µH
M2
VOUT1
1.8V
15A
+
SENSE1
1000pF*
SENSE1–
ITH1,2,3
RITH1,2,3
CP1,2,3
+
660µF
2.5V
20k
1%
CITH1,2,3
DB1,2,3
M3
CB1,2,3 0.1µF
M5
0.47µH
SW1,2,3
BOOST1,2,3
0.78µH
SW2
M4
BG2
PGND
MODE/PLLIN
ILIM
FREQ/PLLFLTR
VFB1
24.9k
1%
22pF
TG2
LTC3853
BG1
100Ω*
0.002Ω
5%
100Ω*
VIN DRVCC12 INTVCC
TG1
PGOOD12
PGOOD3
SW1
VIN
6.5V TO 14V
180µF
16V
10k
SENSE2+
2.55k
TG3
SW3
BG3
SGND
SENSE3+
SENSE3–
EXTVCC
TK/SS1,2,3
100Ω*
100Ω*
10k
1%
VFB2
RUN1,2,3
M6
INTVCC
1000pF*
SENSE2–
0.002Ω
5%
100Ω*
1000pF
20k
1%
VFB3
1000pF*
100Ω*
VOUT2
1.2V
15A
47pF
+
0.002Ω
5%
VOUT3
2.5V
15A
43.2k
1%
660µF
2.5V
20k
1%
+
660µF
4V
CSS1,2,3
0.1µF
M1, M3, M5: RJK0305DPB
M2, M4, M6: RJK0301DPB
CHANNEL 1: RITH1 = 15k, CITH1 = 1500pF, CP1 = 330pF
CHANNEL 2: RITH2 = 10k, CITH2 = 1500pF, CP2 = 220pF
CHANNEL 3: RITH3 = 13k, CITH3 = 1500pF, CP3 = 330pF
3853 TA03
*THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC
3853fc
32
For more information www.linear.com/LTC3853
LTC3853
TYPICAL APPLICATIONS
Dual 1.2V/2.5V High Current Step-Down Converter with RSENSE
4.7µF
VIN DRVCC12 INTVCC
TG1
PGOOD12
PGOOD3
SW1
0.47µH
BG1
VOUT1
1.2V
30A
1000pF*
+
660µF
2.5V
×2
SENSE2+
EXTVCC
SENSE2–
20k
1%
CITH1,3
100Ω*
10k
0.78µH
1000pF*
VFB2
RUN2
0.002Ω
5%
100Ω*
INTVCC
100Ω*
1000pF*
100Ω*
VOUT1
200k
RUN1,3
ITH1,2,3
RITH1,3
0.47µH
SW1,2,3
BG2
SENSE1+
SENSE1–
CP1,3
CB1,2,3 0.1µF
SW2
LTC3853
VFB1
10k
1%
47pF
DB1,2,3
BOOST1,2,3
PGND
MODE/PLLIN
ILIM
FREQ/PLLFLTR
100Ω*
0.002Ω
5%
100Ω*
TG2
VIN
6.5V TO 14V
180µF
16V
2.55k
43.2k
1%
1000pF
TG3
SW3
BG3
SENSE3+
SENSE3–
TK/SS3
VFB3
SGND
TK/SS1
CSS1
0.22µF
0.002Ω
5%
VOUT3
2.5V
15A
20k
1%
+
660µF
4V
CSS3
0.1µF
3853 TA04
CHANNEL 1: RITH1 = 10k, CITH1 = 1500pF, CP1 = 220pF
CHANNEL 2: ITH1 AND ITH2 SHORTED TOGETHER,
TK/SS1 AND TK/SS2 SHORTED TOGETHER
CHANNEL 3: RITH3 = 13k, CITH3 = 1500pF, CP3 = 330pF
*THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC
3853fc
For more information www.linear.com/LTC3853
33
LTC3853
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ±0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
3853fc
34
For more information www.linear.com/LTC3853
LTC3853
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/10
Change to Operating Temperature Range
2
Updated Order Information Part Marking
2
Edits made to Note 2 and 3
4
Changes to graphs G01 and G02
5
Updated Related Parts table
B
8/14
Added H- and MP-grade parts
C
3/15
Corrected IC pin names
Added VOUT range
36
2, 3, 4, 7
2
3
Corrected typographical errors
5, 21, 22 and
30
3853fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC3853
35
LTC3853
TYPICAL APPLICATION
Three Phase 2.5V Output High Current Step-Down Converter with RSENSE
4.7µF
0.78µH
1000pF*
BG2
100Ω*
CP1
RITH1
20k
1%
CITH1
10k
SENSE2+
EXTVCC
0.78µH
SENSE2
VFB1
VFB2
VFB3
RUN1
RUN2
RUN3
ITH1
ITH2
ITH3
TG3
SW3
BG3
SENSE3+
SENSE3–
SGND
2.55k
0.002Ω
5%
100Ω*
INTVCC
1000pF*
–
SENSE1–
43.2k
1%
47pF
0.78µH
SW1,2,3
VIN
6.5V TO 14V
SW2
SENSE1+
0.002Ω
5%
100Ω*
660µF
4V
×3
CB1,2,3 0.1µF
BOOST1,2,3
PGND
MODE/PLLIN
ILIM
FREQ/PLLFLTR
100Ω*
+
TG2
LTC3853
BG1
VOUT1
2.5V
40A
DB1,2,3
VIN DRVCC12 INTVCC
TG1
PGOOD12
PGOOD3
SW1
180µF
16V
100Ω*
1000pF*
100Ω*
VOUT1
0.002Ω
5%
VOUT1
1000pF
3853 TA05
TK/SS1
CSS1
0.33µF
RITH1 = 3.9k, CITH1 = 10nF, CP1 = 470pF • 3
SHORT TK/SS1, TK/SS2 AND TK/SS3 TOGETHER
*THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3850/LTC3850-1/
LTC3850-2
Dual Output Synchronous Step-Down DC/DC Controller
RSENSE or DCR Current Sensing
Phase-Lockable Fixed 250kHz to 780kHz Frequency,
4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
LTC3861
Dual Output Synchronous Step-Down DC/DC Controller with
Diff Amp, DCR Current Sense, PolyPhase® and Three-State
Output Drive
Operates with Power Blocks, DRMOS Devices or External
MOSFETs 3V ≤ VIN ≤ 24V
LTC3855
Dual Output Synchronous Step-Down DC/DC Controller with
Diff Amp, PolyPhase and DCR Temperature Compensation
Phase-Lockable Fixed Frequency 250kHz to 770kHz,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V
LTC3829
3-Phase, Single Output Synchronous Step-Down DC/DC
Controller with Diff Amp, PolyPhase and DCR Temperature
Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V
LTC3856
2-Phase, Single Output Synchronous Step-Down DC/DC
Controller with Diff Amp, PolyPhase and DCR Temperature
Compensation
Phase-Lockable Fixed Frequency 250kHz to 770kHz,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V
LTC3851A/
LTC3851A-1
Single Output Synchronous Step-Down DC/DC Controller
RSENSE or DCR Current Sensing
Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E 3mm × 3mm
QFN-16, SSOP-16
3853fc
36 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3853
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