LTC1198-2ACS8

LTC1196/LTC1198 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options FEATURES s s s s s DESCRIPTIO s s s s s s s High Sampling Rates: 1MHz (LTC1196) 750kHz (LTC1198) Low Cost SO-8 Plastic Package Single Supply 3V and 5V Specifications Low Power: 10mW at 3V Supply 50mW at 5V Supply Auto-Shutdown: 1nA Typical (LTC1198) ±1/2LSB Total Unadjusted Error over Temperature 3-Wire Serial I/O 1V to 5V Input Span Range (LTC1196) Converts 1MHz Inputs to 7 Effective Bits Differential Inputs (LTC1196) 2-Channel MUX (LTC1198) The LTC1196/LTC1198 are 600ns, 8-bit A/D converters with sampling rates up to 1MHz. They are offered in 8-pin SO packages and operate on 3V to 6V supplies. Power dissipation is only 10mW with a 3V supply or 50mW with a 5V supply. The LTC1198 automatically powers down to a typical supply current of 1nA whenever it is not performing conversions. These 8-bit switched-capacitor successive approximation ADCs include sample-and-holds. The LTC1196 has a differential analog input; the LTC1198 offers a software selectable 2-channel MUX. The 3-wire serial I/O, SO-8 packages, 3V operation and extremely high sample rate-to-power ratio make these ADCs an ideal choice for compact, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans below 1V full scale (LTC1196) allow direct connection to signal sources in many applications, eliminating the need for gain stages. The A grade devices are specified with total unadjusted error of ±1/2LSB maximum over temperature. APPLICATI s s s s S High Speed Data Acquisition Disk Drives Portable or Compact Instrumentation Low Power or Battery-Operated Systems TYPICAL APPLICATI Single 5V Supply, 1MSPS, 8-Bit Sampling ADC 1µF 5V Effective Bits and S/(N + D) vs Input Frequency 8 EFFECTIVE NUMBER OF BITS (ENOBs) 7 6 5 4 3 2 1 0 1k VREF = VCC = 2.7V fSMPL = 383kHz (LTC1196) fSMPL = 287kHz (LTC1198) VREF = VCC = 5V fSMPL = 1MHz (LTC1196) fSMPL = 750kHz (LTC1198) 1 2 ANALOG INPUT 0V TO 5V RANGE CS +IN VCC 8 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP, OR SHIFT REGISTERS 7 LTC1196 CLK (SO-8) 3 6 –IN DOUT 4 5 GND VREF 1196/98 TA01 TA = 25°C 10k 100k INPUT FREQUENCY (Hz) 1M 1196/98 G24 U 50 44 S/(N + D) (dB) UO UO 1 LTC1196/LTC1198 ABSOLUTE AXI U RATI GS (Notes 1, 2) Operating Temperature Range LTC1196-1AC, LTC1198-1AC, LTC1196-1BC, LTC1198-1BC, LTC1196-2AC, LTC1198-2AC, LTC1196-2BC, LTC1198-2BC................ 0°C to 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C Supply Voltage (VCC) to GND .................................... 7V Voltage Analog Reference ...................... –0.3V to VCC + 0.3V Digital Inputs.......................................... –0.3V to 7V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation ............................................. 500mW PACKAGE/ORDER I FOR ATIO TOP VIEW CS 1 +IN 2 –IN 3 GND 4 8 7 6 5 VCC CLK DOUT VREF ORDER PART NUMBER* TOP VIEW LTC1196-1ACS8 LTC1196-1BCS8 LTC1196-2ACS8 LTC1196-2BCS8 S8 PART MARKING 1961A 1961B 1962A 1962B S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 150°C, θJA = 175°C/W *Parts available in N8 package. Consult factory for N8 samples. RECO SYMBOL VCC fCLK tCYC tSMPL thCS tsuCS thDI E DED OPERATI G CO DITIO S CONDITIONS LTC1196-1 LTC1198-1 MIN TYP MAX 2.7 0.01 0.01 12 16 2.5 10 20 LTC1198 20 6 14.4 12.0 LTC1196-2 LTC1198-2 MIN TYP MAX 2.7 0.01 0.01 12 16 2.5 13 26 26 6 12.0 9.6 UNITS V MHz MHz CLK CLK CLK ns ns ns PARAMETER Supply Voltage Clock Frequency VCC = 5V Operation q Total Cycle Time Analog Input Sampling Time Hold Time CS Low After Last CLK↑ Setup Time CS↓ Before First CLK↑ (See Figures 1, 2) Hold Time DIN After CLK↑ LTC1196 LTC1198 2 U U U U U W WW U W ORDER PART NUMBER* CS/ 1 SHUTDOWN CH0 2 CH1 3 GND 4 8 7 6 5 VCC (VREF) CLK DOUT DIN LTC1198-1ACS8 LTC1198-1BCS8 LTC1198-2ACS8 LTC1198-2BCS8 S8 PART MARKING 1981A 1981B 1982A 1982B S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 150°C, θJA = 175°C/W U WW LTC1196/LTC1198 RECO SYMBOL tsuDI tWHCLK tWLCLK tWHCS tWLCS E DED OPERATI G CO DITIO S CONDITIONS LTC1198 fCLK = fCLK(MAX) fCLK = fCLK(MAX) LTC1196 LTC1198 LTC1196-1 LTC1198-1 MIN TYP MAX 20 40% 40% 25 11 15 LTC1196-2 LTC1198-2 MIN TYP MAX 26 40% 40% 32 11 15 UNITS ns 1/fCLK 1/fCLK ns CLK CLK PARAMETER Setup Time DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer CO VERTER A D PARAMETER No Missing Codes Resolution Offset Error Linearity Error Full-Scale Error Total Unadjusted Error (Note 4) Analog and REF Input Range Analog Input Leakage Current ULTIPLEXER CHARACTERISTICS CONDITIONS q q VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-XA LTC1198-XA MIN TYP MAX 8 ± 1/2 ± 1/2 ± 1/2 ± 1/2 – 0.05V to VCC + 0.05V q (Note 3) LTC1196, VREF = 5.000V LTC1198, VCC = 5.000V LTC1196 (Note 5) q q q DIGITAL A D DC ELECTRICAL CHARACTERISTICS VCC = 5V, VREF = 5V, unless otherwise noted. SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current, LTC1196 Supply Current CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10µA VCC = 4.75V, IO = 360µA VCC = 4.75V, IO = 1.6mA CS = High VOUT = 0V VOUT = VCC CS = VCC fSMPL = fSMPL(MAX) CS = VCC, LTC1198 (Shutdown) CS = VCC, LTC1196 fSMPL = fSMPL(MAX), LTC1196/LTC1198 q q q q q q q q q q q q q U U U WU U WW U U LTC1196-XB LTC1198-XB MIN TYP MAX 8 ±1 ±1 ±1 ±1 UNITS Bits LSB LSB LSB LSB V ±1 ±1 µA MIN 2.0 TYP MAX 0.8 2.5 – 2.5 UNITS V V µA µA V V 4.5 2.4 4.74 4.71 0.4 ±3 – 25 45 0.001 0.5 0.001 7 11 3 1 3 15 20 V µA mA mA µA mA µA mA mA 3 LTC1196/LTC1198 DY A IC ACCURACY VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL S/(N + D) THD IMD PARAMETER Signal-to-Noise Plus Distortion Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth [S/(N + D) > 44dB] CONDITIONS 500kHz/1MHz Input Signal 500kHz/1MHz Input Signal 500kHz/1MHz Input Signal fIN1 = 499.37kHz, fIN2 = 502.446kHz MIN LTC1196 TYP MAX 47/45 49/47 55/48 51 8 1 MIN LTC1198 TYP MAX 47/45 49/47 55/48 51 8 1 UNITS dB dB dB dB MHz MHz AC CHARACTERISTICS VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-1 LTC1198-1 MIN TYP MAX q SYMBOL tCONV fSMPL(MAX) Maximum Sampling Frequency tdDO tDIS ten thDO tr tf CIN RECO SYMBOL fCLK tCYC tSMPL thCS tsuCS E DED OPERATI G CO DITIO S CONDITIONS q VCC = 2.7V Operation LTC1196-1 LTC1198-1 MIN TYP MAX 0.01 0.01 12 16 2.5 20 40 5.4 4.6 LTC1196-2 LTC1198-2 MIN TYP MAX 0.01 0.01 12 16 2.5 40 78 4 3 PARAMETER Clock Frequency Total Cycle Time Analog Input Sampling Time Hold Time CS Low After Last CLK↑ Setup Time CS↓ Before First CLK↑ (See Figures 1, 2) LTC1196 LTC1198 4 U U U U WW WU PARAMETER Conversion Time (See Figures 1, 2) CONDITIONS LTC1196-2 LTC1198-2 MIN TYP MAX 710 900 1.00 0.80 0.75 0.60 UNITS ns ns MHz MHz MHz MHz 600 710 1.20 1.00 0.90 0.75 55 64 73 120 50 30 15 15 LTC1196 LTC1196 LTC1198 LTC1198 CLOAD = 20pF q q q Delay Time, CLK↑ to DOUT Data Valid Delay Time CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↑ DOUT Fall Time DOUT Rise Time Input Capacitance 68 88 43 55 10 10 30 5 5 78 94 150 63 ns ns ns ns ns q 70 30 30 45 5 5 30 5 5 CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF Analog Input On Channel Analog Input Off Channel Digital Input q q q q 20 20 ns ns pF pF pF UNITS MHz MHz CLK CLK CLK ns ns LTC1196/LTC1198 RECO SYMBOL thDI tsuDI tWHCLK tWLCLK tWHCS tWLCS E DED OPERATI G CO DITIO S CONDITIONS LTC1198 LTC1198 fCLK = fCLK(MAX) fCLK = fCLK(MAX) LTC1196 LTC1198 LTC1196-1 LTC1198-1 MIN TYP MAX 40 40 40% 40% 50 11 15 LTC1196-2 LTC1198-2 MIN TYP MAX 78 78 40% 40% 96 11 15 UNITS ns ns 1/fCLK 1/fCLK ns CLK CLK VCC = 2.7V Operation PARAMETER Hold Time DIN After CLK↑ Setup Time DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer CO VERTER A D PARAMETER No Missing Codes Resolution Offset Error Linearity Error Full-Scale Error Total Unadjusted Error (Note 4) Analog and REF Input Range Analog Input Leakage Current ULTIPLEXER CHARACTERISTICS CONDITIONS q q VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-XA LTC1198-XA MIN TYP MAX 8 ± 1/2 ± 1/2 ± 1/2 ± 1/2 – 0.05V to VCC + 0.05V q (Note 3) LTC1196, VREF = 2.500V LTC1198, VCC = 2.700V LTC1196 (Note 5) q q q DIGITAL A D DC ELECTRICAL CHARACTERISTICS VCC = 2.7V, VREF = 2.5V, unless otherwise noted. SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current, LTC1196 Supply Current CONDITIONS VCC = 3.6V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10µA VCC = 2.7V, IO = 360µA VCC = 2.7V, IO = 400µA CS = High VOUT = 0V VOUT = VCC CS = VCC fSMPL = fSMPL(MAX) CS = VCC = 3.3V, LTC1198 (Shutdown) CS = VCC = 3.3V, LTC1196 fSMPL = fSMPL(MAX), LTC1196/LTC1198 q q q q q q q q q q q q q U U U WU U WW U U LTC1196-XB LTC1198-XB MIN TYP MAX 8 ±1 ±1 ±1 ±1 UNITS Bits LSB LSB LSB LSB V ±1 ±1 µA MIN 1.9 TYP MAX 0.45 2.5 – 2.5 UNITS V V µA µA V V 2.3 2.1 2.60 2.45 0.3 ±3 – 10 15 0.001 0.25 0.001 1.5 2.0 3.0 0.5 3.0 4.5 6.0 V µA mA mA µA mA µA mA mA 5 LTC1196/LTC1198 DY A IC ACCURACY VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL S/(N + D) THD IMD PARAMETER Signal-to-Noise Plus Distortion Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth [S/(N + D) > 44dB] CONDITIONS 190kHz/380kHz Input Signal 190kHz/380kHz Input Signal 190kHz/380kHz Input Signal fIN1 = 189.37kHz, fIN2 = 192.446kHz MIN LTC1196 TYP MAX 47/45 49/47 53/46 51 5 0.5 MIN LTC1198 TYP MAX 47/45 49/47 53/46 51 5 0.5 UNITS dB dB dB dB MHz MHz AC CHARACTERISTICS VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-1 LTC1198-1 MIN TYP MAX q SYMBOL tCONV fSMPL(MAX) Maximum Sampling Frequency tdDO tDIS ten thDO tr tf CIN The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 6 WU PARAMETER Conversion Time (See Figures 1, 2) CONDITIONS LTC1196-2 LTC1198-2 MIN TYP MAX 2.13 2.84 333 250 250 187 UNITS µs µs kHz kHz kHz kHz 1.58 1.85 450 383 337 287 100 150 180 220 130 45 30 30 LTC1196 LTC1196 LTC1198 LTC1198 CLOAD = 20pF q q q Delay Time, CLK↑ to DOUT Data Valid Delay Time CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↑ DOUT Fall Time DOUT Rise Time Input Capacitance 130 120 100 120 15 15 30 5 5 200 250 250 200 ns ns ns ns ns q 110 80 45 90 10 10 30 5 5 CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF Analog Input On Channel Analog Input Off Channel Digital Input q q q q 40 40 ns ns pF pF pF Note 4: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. Note 5: Channel leakage current is measured after the channel selection. LTC1196/LTC1198 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Clock Rate 9 8 VCC = 5V SUPPLY CURRENT (mA) 6 5 4 3 2 1 0 0 2 4 6 8 10 12 FREQUENCY (MHz) 14 16 VCC = 2.7V TA = 25°C CS = 0V VREF = VCC 10 8 6 4 2 “ACTIVE” MODE CS = 0V LTC1196 LTC1198 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 7 Supply Current vs Temperature 10 9 8 CS = 0V MAGNITUDE OF OFFSET (LSB = 1 × VREF) 256 MAGNITUDE OF OFFSET (LSB) SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0 –55 –35 –15 VCC = 5V VCC = 2.7V 5 25 45 65 85 105 125 TEMPERATURE (°C) 1196/98 G04 Linearity Error vs Reference Voltage 1.0 0.9 0.8 LINEARITY ERROR (LSB) 0.3 LINEARITY ERROR (LSB) MAGNITUDE OF GAIN ERROR (LSB) TA = 25°C VCC = 5V fCLK = 12MHz 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G07 UW 1196/98 G01 Supply Current vs Supply Voltage 14 TA = 25°C 12 Supply Current vs Sample Rate 10 LT1196 VCC = 5V 1 LT1196 VCC = 2.7V 0.1 LT1198 VCC = 5V 0.01 LT1198 VCC = 2.7V 0.000002 LTC1198 0 2.5 3.0 “SHUTDOWN” MODE CS = VCC 5.5 6.0 TA = 25°C 0.001 100 1k 10k 100k SAMPLE RATE (Hz) 1M 1196/98 G03 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 1196/98 G02 Offset vs Reference Voltage 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G05 Offset vs Supply Voltage 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 TA = 25°C VREF = VCC fCLK = 3MHz TA = 25°C VCC = 5V fCLK = 12MHz 1196/98 G06 Linearity Error vs Supply Voltage 0.5 0.4 TA = 25°C VREF = VCC fCLK = 3MHz 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 Gain Error vs Reference Voltage TA = 25°C VCC = 5V fCLK = 12MHz 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G09 1196/98 G08 7 LTC1196/LTC1198 TYPICAL PERFOR A CE CHARACTERISTICS Gain vs Supply Voltage 0.5 MAXIMUM CLOCK FREQUENCY (MHz) MAGNITUDE OF GAIN ERROR (LSB) 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2.5 15 13 11 9 7 5 2.5 CLOCK FREQUENCY (MHz) TA = 25°C fCLK = 3MHz VREF = VCC 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Minimum Clock Rate for 0.1LSB* Error 100 MINIMUM CLOCK FREQUENCY (kHz) 90 80 70 60 50 40 30 20 10 PEAK-TO-PEAK ADC NOISE (LSB) VCC = 5V VREF = 5V 0.25 0.20 0.15 0.10 0.05 0 2.5 S&H ACQUISITION TIME (ns) 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1196/98 G13 Digital Input Logic Threshold vs Supply Voltage 1.9 1.7 LOGIC THRESHOLD (V) 140 TA = 25°C 120 DOUT DELAY TIME, t dDO (ns) 100 80 60 40 20 0 2.5 DOUT DELAY TIME, t dDO (ns) 1.5 1.3 1.1 0.9 0.7 0.5 2.5 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) *AS THE FREQUENCY IS DECREASED FROM 12MHz, MINIMUM CLOCK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 12MHz VALUE IS FIRST DETECTED. 8 UW 5.5 6.0 1196/98 G10 Maximum Clock Frequency vs Supply Voltage 19 17 TA = 25°C VREF = VCC 18 16 14 12 10 8 6 4 2 0 Maximum Clock Frequency vs Source Resistance VIN + IN –IN RSOURCE– TA = 25°C VCC = VREF = 5V 1 10 10k 1k 100 SOURCE RESISTANCE (Ω) 100k 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 1196/98 G11 1196/98 G12 ADC Noise vs Reference and Supply Voltage 0.35 0.30 TA = 25°C VREF = VCC 10000 Sample-and-Hold Acquisition Time vs Source Resistance TA = 25°C VCC = VREF = 5V RSOURCE+ VIN + IN –IN 1000 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 100 1 100 10 1k SOURCE RESISTANCE (Ω) 10k 1196/98 G15 1196/98 G14 DOUT Delay Time vs Supply Voltage 160 DOUT Delay Time vs Temperature TA = 25°C VREF = VCC 140 120 100 80 60 40 20 VCC = 5V VREF = VCC VCC = 2.7V 5.5 6.0 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 0 – 60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1196/98 G18 1196/98 G16 1196/98 G17 LTC1196/LTC1198 TYPICAL PERFOR A CE CHARACTERISTICS Input Channel Leakage Current vs Temperature 1000 100 10 ON CHANNEL 1 OFF CHANNEL 0.1 INTEGRAL NONLINEARITY ERROR (LSB) VCC = 5V VREF = 5V LEAKAGE CURRENT (nA) VCC = 5V VREF = 5V fCLK = 12MHz DIFFERENTIAL NONLINEARITY ERROR (LSB) 0.01 – 60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1196/98 G19 Integral Nonlinearity vs Code at 2.7V 0.5 VCC = 2.7V VREF = 2.5V fCLK = 3MHz INL ERROR (LSB) DIFFERENTIAL NONLINEARITY ERROR (LSB) EFFECTIVE NUMBER OF BITS (ENOBs) 0 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G22 4096 Point FFT Plot at 5V 0 –10 –20 VCC = 5V fIN = 29kHz fSMPL = 882kHz MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 100 300 200 FREQUENCY (kHz) 400 500 1196/98 G25 UW Integral Nonlinearity vs Code at 5V 0.5 0.5 Differential Nonlinearity vs Code at 5V VCC = 5V VREF = 5V fCLK = 12MHz 0 0 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G20 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G21 Differential Nonlinearity vs Code at 2.7V 0.5 VCC = 2.7V VREF = 2.5V fCLK = 3MHz 8 7 6 5 4 3 2 1 0 Effective Bits and S/(N + D) vs Input Frequency 50 VREF = VCC = 2.7V fSMPL = 383kHz (LTC1196) fSMPL = 287kHz (LTC1198) VREF = VCC = 5V fSMPL = 1MHz (LTC1196) fSMPL = 750kHz (LTC1198) 44 S/(N + D) (dB) 0 TA = 25°C 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1196/98 G24 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G23 4096 Point FFT at 2.7V 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 50 150 100 FREQUENCY (kHz) 200 1196/98 G26 FFT Output of 455kHz AM Signal Digitized at 1MSPS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100 300 200 FREQUENCY (kHz) 400 500 1196/98 G27 VCC = 2.7V fIN = 29kHz fSMPL = 340kHz VCC = 5V fIN = 455kHz WITH 20kHz AM fSMPL = 1MHz 9 LTC1196/LTC1198 TYPICAL PERFOR A CE CHARACTERISTICS Power Supply Feedthrough vs Ripple Frequency 0 –10 TA = 25°C VCC (VRIPPLE = 20mV) fCLK = 12MHz –10 FEEDTHROUGH(dB) –20 –30 –40 –50 –60 –70 TA = 25°C VCC (VRIPPLE = 10mV) fCLK = 5MHz SIGNAL TO NOISE PLUS DISTORTION (dB) FEEDTHROUGH (dB) –20 –30 –40 –50 –60 –70 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M 1196/98 G28 Intermodulation Distortion at 2.7V 0 –10 –20 MAGNITUDE (dB) MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 50 VCC = 2.7V f1 = 100kHz f2 = 110kHz fSMPL = 420kHz –10 –20 –30 –40 –50 –60 –70 –80 –90 VCC = 5V f1 = 200kHz f2 = 210kHz fSMPL = 750kHz SIGNAL TO NOISE-PLUS-DISTORTION (dB) 150 100 FREQUENCY (kHz) Output Amplitude vs Input Frequency 100 SPURIOUS-FREE DYNAMIC RANGE (dB) PEAK-TO-PEAK OUTPUT (%) 80 VREF = VCC = 5V 60 VREF = VCC = 2.7V 40 20 0 1k 100k 10k 1M INPUT FREQUENCY (Hz) 10 UW 200 250 1196/98 G31 Power Supply Feedthrough vs Ripple Frequency 0 S/(N + D) vs Reference Voltage and Input Frequency 50 fIN = 500kHz 45 fIN = 200kHz fIN = 100kHz 40 35 30 VCC = 5V 25 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 REFERENCE VOLTAGE (V) 1196/98 G30 - 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M 1196/98 G29 Intermodulation Distortion at 5V 0 50 S/(N + D) vs Input Level VREF = VCC = 5V fIN = 500kHz fSMPL = 1MHz 40 30 20 10 –100 0 100 300 200 FREQUENCY (kHz) 400 1196/98 G32 0 –40 –35 –30 –25 –20 –15 –10 INPUT LEVEL (dB) –5 0 1196/98 G33 Spurious-Free Dynamic Range vs Frequency 70 60 50 40 30 20 10 TA = 25°C 0 10M 1196/98 G34 VCC = 5V fCLK = 12MHz VCC = 3V fCLK = 5MHz 1k 10k 100k FREQUENCY (Hz) 1M 10M 1196/98 G35 LTC1196/LTC1198 PI FU CTIO S LTC1196 CS (Pin 1): Chip Select Input. A logic low on this input enables the LTC1196. A logic high on this input disables the LTC1196. IN + (Pin 2): Analog Input. This input must be free of noise with respect to GND. IN – (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. LTC1198 CS/SHUTDOWN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1198. A logic high on this input disables the LTC1198 and DISCONNECTS THE POWER TO THE LTC1198. CHO (Pin 2): Analog Input. This input must be free of noise with respect to GND. CH1 (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this input. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC(VREF)(Pin 8): Power Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. BLOCK DIAGRA IN – (CH1) GND PIN NAMES IN PARENTHESES REFER TO THE LTC1198 + – W U U U VCC (VCC/VREF) CS (CS/SHUTDOWN) CLK BIAS AND SHUTDOWN CIRCUIT IN + (CH0) SERIAL PORT DOUT CSMPL SAR HIGH SPEED COMPARATOR CAPACITIVE DAC VREF (DIN) 1196/98 BD 11 LTC1196/LTC1198 TEST CIRCUITS On and Off Channel Leakage Current 5V ION A IOFF A ON CHANNEL Load Circuit for t dDO, t r and t f 1.4V 3k DOUT 100pF TEST POINT • • • • POLARITY OFF CHANNEL 1196/98 TC02 1196/98 TC01 Voltage Waveform for DOUT Rise and Fall Times, tr, tf Voltage Waveform for DOUT Delay Time, tdDO and thDO DOUT VOH CLK VOL tr tf VIH tdDO thDO 1196/98 TC04 VOH DOUT VOL 1196/98 TC03 Load Circuit for tdis and ten CS Voltage Waveforms for tdis VIH TEST POINT DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2) 10% 90% 3k DOUT 20pF VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1 1196/98 TC05 NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1196/98 TC06 12 LTC1196/LTC1198 TEST CIRCUITS Voltage Waveforms for ten LTC1196 CS CLK 1 2 3 4 DOUT VOL ten B7 1196/98 TC07 Voltage Waveforms for ten LTC1198 CS DIN START CLK 1 2 3 4 5 6 7 DOUT ten B7 VOL 1196/98 TC08 13 LTC1196/LTC1198 APPLICATI OVERVIEW The LTC1196/LTC1198 are 600ns sampling 8-bit A/D converters packaged in tiny 8-pin SO packages and operating on 3V to 6V supplies. The ADCs draw only 10mW from a 3V supply or 50mW from a 5V supply. Both the LTC1196 and the LTC1198 contain an 8-bit, switched-capacitor ADC, a sample-and-hold, and a serial port (see Block Diagram). The on-chip sample-and-holds have full-accuracy input bandwidths of 1MHz. Although they share the same basic design, the LTC1196 and LTC1198 differ in some respects. The LTC1196 has a differential input and has an external reference input pin. It can measure signals floating on a DC common-mode voltage and can operate with reduced spans below 1V. The S I FOR ATIO CS tsuCS CLK tdDO DOUT B0 tSMPL Hi-Z NULL BITS B7 B6 B5 B4 B3 B2 B1 B0* tSMPL Hi-Z NULL BITS *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. 1196/98 F01 Figure 1. LTC1196 Operating Sequence CS tsuCS CLK START DIN SGL/ DIFF DOUT HI-Z tSMPL (2.5CLKs) DUMMY NULL BITS B7 B6 B5 B4 ODD/ SIGN DUMMY DON’T CARE tdDO B3 B2 B1 B0* *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. 1196/98 F02 Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH 1, CH 0) 14 U LTC1198 has a 2-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. It also automatically powers down when not performing conversion, drawing only leakage current. SERIAL INTERFACE The LTC1196/LTC1198 will interface via three or four wires to ASICs, PLDs, microprocessors, DSPs, or shift registers (see Operating Sequence in Figures 1 and 2). To run at their fastest conversion rates (600ns), they must be clocked at 14.4MHz. HC logic families and any high speed ASIC or PLD will easily interface to the ADCs at that speed (see Data Transfer and Typical Application sections). Full speed operation from a 3V supply can still be achieved with 3V ASICs, PLDs or HC logic circuits. tCYC (12 CLKs) tCONV (8.5 CLKs) tCYC (16 CLKs) POWER DOWN Hi-Z tCONV (8.5CLKs) W U UO LTC1196/LTC1198 APPLICATI S I FOR ATIO Connection to a microprocessor or a DSP serial port is quite simple (see Data Transfer section). It requires no additional hardware, but the speed will be limited by the clock rate of the microprocessor or the DSP which limits the conversion time of the LTC1196/LTC1198. Data Transfer Data transfer differs slightly between the LTC1196 and the LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK and DOUT. A falling CS initiates data transfer as shown in the LTC1196 Operating Sequence. After CS falls, the first CLK pulse enables DOUT. After two null bits, the A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1196 for the next data exchange. The LTC1198 can transfer data with 3 or 4 wires. The additional input, DIN, is used to select the 2-channel MUX configuration. The data transfer between the LTC1198 and the digital systems can be broken into two sections: Input Data Word and A/D Conversion Result. First, each bit of the input data word is captured on the rising CLK edge by the LTC1198. Second, each bit of the A/D conversion result on the DOUT line is updated on the rising CLK edge by the LTC1198. This bit should be captured on the next rising CLK edge by the digital systems (see A/D Conversion Result section). Data transfer is initiated by a falling chip select (CS) signal as shown in the LTC1198 Operating Sequence. After CS falls the LTC1198 looks for a start bit. After the start bit is received, the 4-bit input word is shifted into the DIN input. The first two bits of the input word configure the LTC1198. The last two bits of the input word allow the ADC to acquire the input voltage by 2.5 clocks before the conversion starts. After the conversion starts, two null bits and the CS DIN1 DOUT1 SHIFT MUX ADDRESS IN 2 NULL BITS SHIFT A/D CONVERSION RESULT OUT 1196/98 AI01 DIN2 DOUT2 U conversion result are output on the DOUT line. At the end of the data exchange CS should be brought high. This resets the LTC1198 in preparation for the next data exchange. Input Data Word The LTC1196 requires no DIN word. It is permanently configured to have a single differential input. The conversion result is output on the DOUT line in an MSB-first sequence, followed by zeros indefinitely if clocks are continuously applied with CS low. The LTC1198 clocks data into the DIN input on the rising edge of the clock. The input data word is defined as follows: START SGL/ DIFF ODD/ SIGN DUMMY DUMMY DUMMY BITS 119698 AI02 W U UO MUX ADDRESS Start Bit The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1198 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. Multiplexer (MUX) Address The 2 bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND. LTC1198 Channel Selection MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 CHANNEL # 0 1 + + + – – + GND – – SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE 1196/98 AI03 15 LTC1196/LTC1198 APPLICATI Dummy Bits The last 2 bits of the input word following the MUX Address are dummy bits. Either bit can be a “logical one” or a “logical zero.” These 2 bits allow the ADC 2.5 clocks to acquire the input signal after the channel selection. A/D Conversion Result Both the LTC1196 and the LTC1198 have the A/D conversion result appear on the DOUT line after two null bits (see Operating Sequence in Figures 1 and 2). Data on the DOUT line is updated on the rising edge of the CLK line. The DOUT data should also be captured on the rising CLK edge by the digital systems. Data on the DOUT line remains valid for a minimum time of thDO (30ns at 5V) to allow the capture to occur (see Figure 3). CLK VIH tdDO thDO VOH DOUT VOL 1196/98 TC03 S I FOR ATIO Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO Unipolar Transfer Curve The LTC1196/LTC1198 are permanently configured for unipolar only. The input span and code assignment for this conversion type are shown in the following figures. Unipolar Transfer Curve 11111111 11111110 • • • 00000001 00000000 VIN 16 U Unipolar Output Code OUTPUT CODE 11111111 11111110 • • • 00000001 00000000 INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V INPUT VOLTAGE (VREF = 5.000V) 4.9805V 4.9609V • • • 0.0195V 0V 1196/98 AI05 W U UO Operation with DIN and DOUT Tied Together The LTC1198 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the digital systems. Data is transmitted in both directions on a single wire. The pin of the digital systems connected to this data line should be configurable as either an input or an output. The LTC1198 will take control of the data line and drive it low on the 5th falling CLK edge after the start bit is received (see Figure 4). Therefore the port line of the digital systems must be switched to an input before this happens to avoid a conflict. REDUCING POWER CONSUMPTION The LTC1196/LTC1198 can sample at up to a 1MHz rate, drawing only 50mW from a 5V supply. Power consumption can be reduced in two ways. Using a 3V supply lowers the power consumption on both devices by a factor of five, to 10mW. The LTC1198 can reduce power even further because it shuts down whenever it is not converting. Figure 5 shows the supply current versus sample rate for the LTC1196 and LTC1198 on 3V and 5V. To achieve such a low power consumption, especially for the LTC1198, several things must be taken into consideration. Shutdown (LTC1198) Figure 2 shows the operating sequence of the LTC1198. The converter draws power when the CS pin is low and powers itself down when that pin is high. For lowest power consumption in shutdown, the CS pin should be driven with CMOS levels (0V to VCC) so that the CS input buffer of the converter will not draw current. 0V 1LSB VREF – 1LSB VREF VREF – 2LSB 1196/98 AI04 LTC1196/LTC1198 APPLICATI CS S I FOR ATIO 1 CLK 2 3 DATA (DIN/DOUT) START SGL/DIFF ODD/SIGN THE DIGITAL SYSTEM CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1198 THE DIGITAL SYSTEM MUST RELEASE DATA LINE AFTER 5TH RISING CLK AND BEFORE THE 5TH FALLING CLK Figure 4. LTC1198 Operation with DIN and DOUT Tied Together 10 LT1196 VCC = 5V 1 LT1196 VCC = 2.7V SUPPLY CURRENT (mA) 0.1 LT1198 VCC = 5V 0.01 LT1198 VCC = 2.7V 0.001 100 1k 10k 100k SAMPLE RATE (Hz) 1M 1196/98 F05 Figure 5. Supply Current vs Sample Rate for LTC1196/ LTC1198 Operating on 5V and 2.7V Supplies When the CS pin is high (= supply voltage), the LTC1198 is in shutdown mode and draws only leakage current. The status of the DIN and CLK input has no effect on the supply current during this time. There is no need to stop DIN and CLK with CS = high; they can continue to run without drawing current. U DUMMY BITS LATCHED BY LTC1198 4 5 DUMMY DUMMY B7 B6 LTC1198 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO THE DIGITAL SYSTEM LTC1198 TAKES CONTROL OF DATA LINE ON 5TH FALLING CLK 1196/98 F04 W U UO Minimize CS Low Time (LTC1198) In systems that have significant time between conversions, lowest power drain will occur with the minimum CS low time. Bringing CS low, transfering data as quickly as possible, then bringing it back high will result in the lowest current drain. This minimizes the amount of time the device draws power. OPERATING ON OTHER THAN 5V SUPPLIES The LTC1196/LTC1198 operate from single 2.7V to 6V supplies. To operate the LTC1196/LTC1198 on other than 5V supplies, a few things must be kept in mind. Input Logic Levels The input logic levels of CS, CLK and DIN are made to meet TTL on 5V supply. When the supply voltage varies, the input logic levels also change (see typical curve of Digital Input Logic Threshold vs Supply Voltage). For these two ADCs to sample and convert correctly, the digital inputs have to be in the logical low and high relative to the operating supply voltage. If achieving micropower consumption is desirable on the LTC1198, the digital inputs must go rail-to-rail between supply voltage and ground (see Reducing Power Consumption section). 17 LTC1196/LTC1198 APPLICATI S I FOR ATIO Clock Frequency The maximum recommended clock frequency is 14.4MHz at 25°C for the LTC1196/LTC1198 running off a 5V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve of Maximum Clock Rate vs Supply Voltage). If the supply is reduced, the clock rate must be reduced also. At 3V the devices are specified with a 5.4MHz clock at 25°C. Mixed Supplies It is possible to have a digital system running off a 5V supply and communicate with the LTC1196/LTC1198 operating on a 3V supply. Achieving this reduces the outputs of DOUT from the ADCs to toggle the equivalent input of the digital system. The CS, CLK and DIN inputs of the ADCs will take 5V signals from the digital system without causing any problem (see typical curve of Digital Input Logic Threshold vs Supply Voltage). With the LTC1196 operating on a 3V supply, the output of DOUT only goes between 0V and 3V. This signal easily meets TTL levels (see Figure 6). 3V 4.7µF MPU (e.g., 8051) CS DIFFERENTIAL INPUTS COMMON-MODE RANGE 0V TO 3V +IN –IN GND LTC1196 VCC CLK DOUT VREF 3V P1.4 P1.3 P1.2 Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System BOARD LAYOUT CONSIDERATIONS Grounding and Bypassing The LTC1196/LTC1198 are easy to use if some care is taken. They should be used with an analog ground plane and single-point grounding techniques. The GND pin should be tied directly to the ground plane. 18 U The VCC pin should be bypassed to the ground plane with a 1µF tantalum with leads as short as possible. If the power supply is clean, the LTC1196/LTC1198 can also operate with smaller 0.1µF surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single-point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. SAMPLE-AND-HOLD Both the LTC1196 and the LTC1198 provide a built-in sample-and-hold (S&H) function to acquire the input signal. The S&H acquires the input signal from “+” input during tSMPL as shown in Figures 1 and 2. The S&H of the LTC1198 can sample input signals in either single-ended or differential mode (see Figure 7). Single-Ended Inputs The sample-and-hold of the LTC1198 allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins as the bit preceding the first DUMMY bit is shifted in and continues until the falling CLK edge after the second DUMMY bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. Differential Inputs With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 8.5 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input, this error would be: VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 8.5/fCLK Where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the 5V 1196/98 F06 W U UO LTC1196/LTC1198 APPLICATI S I FOR ATIO U SAMPLE “+” INPUT MUST SETTLE DURING THIS TIME CS tSMPL tCONV HOLD ODD/SIGN DUMMY DUMMY DON’T CARE B7 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME 1196/98 F07 CLK DIN START DOUT “+” INPUT “–” INPUT Figure 7. LTC1198 “+” and “–” Input Settling Windows CLK. VERROR is proportional to f(“–”) and inversely proportional to fCLK. For a 60Hz signal on the “–” input to generate a 1/4LSB error (5mV) with the converter running at CLK = 12MHz, its peak value would have to be 18.7V. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1196/ LTC1198 have one capacitive switching input current spike per conversion. These current spikes settle quickly and do not cause a problem. However, if source resistances larger than 100Ω are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. W U UO SGL/DIFF “+” Input Settling The input capacitor of the LTC1196 is switched onto “+” input at the end of the conversion and samples the input signal until the conversion begins (see Figure 1). The input capacitor of the LTC1198 is switched onto “+” input during the sample phase (tSMPL, see Figure 7). The sample phase is 2.5 CLK cycles before conversion starts. The voltage on the “+” input must settle completely within tSMPL for the LTC1196/LTC1198. Minimizing RSOURCE+ will improve the input settling time. If a large “+” input source resistance must be used, the sample time can be increased by allowing more time between conversions for the LTC1196 or by using a slower CLK frequency for the LTC1198. 19 LTC1196/LTC1198 APPLICATI S I FOR ATIO “–” Input Settling At the end of the tSMPL, the input capacitor switches to the “–” input and conversion starts (see Figures 1 and 7). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settle completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– will improve settling time. If a large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figures 1 and 7). Again, the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. To achieve the full sampling rate, the analog input should be driven with a low impedance source ( 7) 5V 50mW 1MHz 600ns 0.5LSB 7.9 at 300kHz 1MHz 50mW 15µW 750kHz 600ns 0.5LSB 7.9 at 300kHz 1MHz 3V 10mW 383kHz 1.6µs 0.5LSB 7.9 at 100kHz 500kHz 10mW 9µW 287kHz 1.6µs 0.5LSB 7.9 at 100kHz 500kHz W UO U UO LTC1198-1 PDISS PDISS (Shutdown) Max f SMPL Min tCONV INL (Max) Typical ENOBs Linear Input Bandwidth (ENOBs > 7) 1µF ENA EPM5064 CLK DATA B7 + – CS 2 3 4 1196/98 F13 Figure 13. Intefacing the LTC1196 to the Altera EPM5064 PLD 23 LTC1196/LTC1198 TYPICAL APPLICATI DATA CLK CS B7 B6 B5 B4 B3 B2 B1 B0 70 Interfacing the LTC1198 to the TMS320C25 DSP Figure 15 illustrates the interface between the LTC1198 8-bit data acquisition system and the TMS320C25 digital signal processor (DSP). The interface, which is optimized for speed of transfer and minimum processor supervision, can complete a conversion and shift the data in 4µs with fCLK = 5MHz. The cycle time, 4µs, of each conversion is limited by maximum clock frequency of the serial port of the TMS320C25 which is 5MHz. The supply voltage for 5MHz CLK CLKX CLKR FSR TMS320C25 FSX DX DR Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP 24 UO 140 S 210 280 350 420 490 560 630 TIME (ns) 700 770 840 910 980 1050 1120 1196/98 F14 Figure 14. The Timing Diagram the LTC1198 in Figure 15 can be 2.7V to 6V with fCLK = 5MHz. At 2.7V, fCLK = 5MHz will work at 25°C. See Recommended Operating Conditions for limits over temperature. Hardware Description The circuit works as follows: the LTC1198 clock line controls the A/D conversion rate and the data shift rate. Data is transferred in a synchronous format over DIN and DOUT. The serial port of the TMS320C25 is compatible with that of the LTC1198. The data shift clock lines (CLKR, CLKX) are inputs only. The data shift clock comes from an external source. Inverting the shift clock is necessary because the LTC1198 and the TMS320C25 clock the input data on opposite edges. The schematic of Figure 15 is fed by an external clock source. The signal is fed into the CLK pin of the LTC1198 directly. The signal is inverted with a 74HC04 and then applied to the data shift clock lines (CLKR, CLKX). The framing pulse of the TMS320C25 is fed directly to the CS of the LTC1198. DX and DR are tied directly to DIN and DOUT respectively. CLK CH0 CH1 LTC1198 CS DIN DOUT 1196/98 F15 LTC1196/LTC1198 TYPICAL APPLICATI The timing diagram of Figure 16 was obtained from the circuit of Figure 15. The CLK was 5MHz for the timing diagram and the TMS320C25 clock rate was 40MHz. Figure 17 shows the timing diagram with the LTC1198 running off a 2.7V supply and 5MHz CLK. CS VERTICAL: 5V/DIV CLK DIN DOUT NULL BITS MSB (B7) HORIZONTAL: 1500ns/DIV 1196/98 F16 Figure 16. Scope Trace the LTC1198 Running Off 5V Supply in the Circuit of Figure 15 CS VERTICAL: 5V/DIV CLK DIN DOUT NULL BITS MSB (B7) HORIZONTAL: 500ns/DIV 1196/98 F17 Figure 17. Scope Trace the LTC1198 Running Off 2.7V Supply in the Circuit of Figure 15 UO S Software Description The software configures and controls the serial port of the TMS320C25. The code first sets up the interrupt and reset vectors. On reset the TMS320C25 starts executing code at the label INIT. Upon completion of a 16-bit data transfer, an interrupt is generated and the DSP will begin executing code at the label RINT. In the beginning, the code initializes registers in the TMS320C25 that will be used in the transfer routine. The interrupts are temporarily disabled. The data memory page pointer register is set to zero. The auxiliary register pointer is loaded with one and auxiliary register one is loaded with the value 200 hexadecimal. This is the data memory location where the data from the LTC1198 will be stored. The interrupt mask register (IMR) is configured to recognize the RINT interrupt, which is generated after receiving the last of 16 bits on the serial port. This interrupt is still disabled at this time. The transmit framing synchronization pin (FSX) is configured to be an output. The F0 bit of the status register ST1, is initialized to zero which sets up the serial port to operate in the 16-bit mode. Next, the code in TXRX routine starts to transmit and receive data. The DIN word is loaded into the ACC and shifted left eight times so that it appears as in Figure 18. This DIN word configures the LTC1198 for CH0 with respect to CH1. The DIN word is then put in the transmit register and the RINT interrupt is enabled. The NOP is repeated 3 times to mask out the interrupts and minimize the cycle time of the conversion to be 20 clock cycles. All clocking and CS functions are performed by the hardware. B15 LSB (B0) LSB (B0) 0 1 START 0 S/D 0 O/S 0 1 DUMMY DUMMY 0 B8 0 L1196/98 F18 Figure 18. DIN Word in ACC of TMS320C25 for the Circuit in Figure 15 25 LTC1196/LTC1198 TYPICAL APPLICATI Once RINT is generated the code begins execution at the label RINT. This code stores the DOUT word from the LTC1198 in the ACC and then stores it in location 200 hex. The data appears in location 200 hex right-justified as shown in Figure 19. The code is set up to continually loop, so at this point the code jumps to label TXRX and repeats from here. LABEL MNEMONIC AORG B AORG B 0 INIT >26 RINT >32 >0 >1 AR1,>200 >10 >4 0 >44 7 >1 2 >0 *, 0 TXRX INIT AORG DINT LDPK LARP LRLK LACK SACL STXM FORT LACK SFSM RPTK SFL SACL EINT RPTK NOP TXRX RINT ZALS SACL B END 26 UO S MSB X X X X X X X X 7 6 5 4 3 2 1 LSB 0 > 200 DOUT FROM LTC1198 STORED IN TMS320C25 RAM L1196/98 F19 Figure 19. Memory Map for the Circuit in Figure 15 COMMENTS ON RESET CODE EXECUTION STARTS AT 0 BRANCH TO INITIALIZATION ROUTINE ADDRESS OF RINT INTERRUPT VECTOR BRANCH TO RINT SERVICE ROUTINE MAIN PROGRAM STARTS HERE DISABLE INTERRUPTS SET DATA MEMORY PAGE POINTER TO 0 SET AUXILIARY REGISTER POINTER TO 1 SET AUXILIARY REGISTER 1 TO >200 LOAD IMR CONFIG WORD INTO ACC STORE IMR CONFIG WORD INTO IMR CONFIGURE FSX AS AN OUTPUT SET SERIAL PORT TO 16-BIT MODE LOAD LTC1198 DIN WORD INTO ACC FSX PULSES GENERATED ON XSR LOAD REPEAT NEXT INSTRUCTION 8 TIMES SHIFTS DIN WORD TO RIGHT POSITION PUT DIN WORD IN TRANSMIT REGISTER ENABLE INTERRUPT (DISABLED ON RINT) MINIMIZE THE CONVERSION CYCLE TIME TO BE 20 CLOCK CYCLES STORE LTC1198 DOUT WORD IN ACC STORE ACC IN LOCATION >200 BRANCH TO TRANSMIT RECEIVE ROUTINE Figure 20. TMS320C25 Code for the Circuit in Figure 15 LTC1196/LTC1198 PACKAGE DESCRIPTIO 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.016 – 0.050 0.406 – 1.270 0°– 8° TYP Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimension in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic SOIC 0.189 – 0.197 (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157 (3.810 – 3.988) 1 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC SO8 0493 27 LTC1196/LTC1198 U.S. Area Sales Offices NORTHEAST REGION Linear Technology Corporation One Oxford Valley 2300 E. Lincoln Hwy.,Suite 306 Langhorne, PA 19047 Phone: (215) 757-8578 FAX: (215) 757-5631 Linear Technology Corporation 266 Lowell St., Suite B-8 Wilmington, MA 01887 Phone: (508) 658-3881 FAX: (508) 658-2701 SOUTHEAST REGION Linear Technology Corporation 17060 Dallas Parkway Suite 208 Dallas, TX 75248 Phone: (214) 733-3071 FAX: (214) 380-5138 CENTRAL REGION Linear Technology Corporation Chesapeake Square 229 Mitchell Court, Suite A-25 Addison, IL 60101 Phone: (708) 620-6910 FAX: (708) 620-6977 SOUTHWEST REGION Linear Technology Corporation 22141 Ventura Blvd. Suite 206 Woodland Hills, CA 91364 Phone: (818) 703-0835 FAX: (818) 703-0517 NORTHWEST REGION Linear Technology Corporation 782 Sycamore Dr. Milpitas, CA 95035 Phone: (408) 428-2050 FAX: (408) 432-6331 International Sales Offices FRANCE Linear Technology S.A.R.L. Immeuble "Le Quartz" 58 Chemin de la Justice 92290 Chatenay Malabry France Phone: 33-1-41079555 FAX: 33-1-46314613 GERMANY Linear Techonolgy GMBH Untere Hauptstr. 9 D-85386 Eching Germany Phone: 49-89-3197410 FAX: 49-89-3194821 JAPAN Linear Technology KK 5F YZ Bldg. 4-4-12 Iidabashi, Chiyoda-Ku Tokyo, 102 Japan Phone: 81-3-3237-7891 FAX: 81-3-3237-8010 KOREA Linear Technology Korea Branch Namsong Building, #505 Itaewon-Dong 260-199 Yongsan-Ku, Seoul Korea Phone: 82-2-792-1617 FAX: 82-2-792-1619 SINGAPORE Linear Technology Pte. Ltd. 101 Boon Keng Road #02-15 Kallang Ind. Estates Singapore 1233 Phone: 65-293-5322 FAX: 65-292-0398 TAIWAN Linear Technology Corporation Rm. 801, No. 46, Sec. 2 Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: 886-2-521-7575 FAX: 886-2-562-2285 UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-276-677676 FAX: 44-276-64851 World Headquarters Linear Technology Corporation 1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507 08/16/93 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 LT/GP 0893 10K REV 0 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1993