LTC2222UK-11

LTC2222-11 11-Bit, 105Msps ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Sample Rate: 105Msps 65.4dB SNR up to 140MHz Input 80dB SFDR up to 150MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 475mW CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 48-Pin 7mm × 7mm QFN Package The LTC®2222-11 is a 105Msps, sampling 11-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2222-11 is perfect for demanding communications applications with AC performance that includes 65.4dB SNR and 80dB spurious free dynamic range for signals up to 150MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ± 0.15LSB INL (typ), ± 0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V. The ENC+ and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment TYPICAL APPLICATIO REFH REFL FLEXIBLE REFERENCE 3.3V VDD 0.5V TO 3.3V OVDD 95 90 4th OR HIGHER 85 SFDR (dBFS) 80 75 70 65 2nd OR 3rd + ANALOG INPUT INPUT S/H – 11-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS D10 • • • D0 OGND CLOCK/DUTY CYCLE CONTROL 222211 TA01 60 55 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 ENCODE INPUT U SFDR vs Input Frequency 222211 TA01b U U 222211f 1 LTC2222-11 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW 48 GND 47 VDD 46 VDD 45 GND 44 VCM 43 SENSE 42 MODE 41 OF 40 D10 39 D9 38 OGND 37 OVDD OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2222-11C .......................................... 0°C to 70°C LTC2222-11I .......................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AIN+ 1 AIN– 2 REFHA 3 REFHA 4 REFLB 5 REFLB 6 REFHB 7 REFHB 8 REFLA 9 REFLA 10 VDD 11 VDD 12 49 36 D8 35 D7 34 D6 33 OVDD 32 OGND 31 D5 30 D4 29 D3 28 OVDD 27 OGND 26 D2 25 D1 UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49), MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 29°C/W ORDER PART NUMBER LTC2222CUK-11 LTC2222IUK-11 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V Differential Analog Input (Note 5) Differential Analog Input Single-Ended Analog Input (Note 5) Single-Ended Analog Input (Note 6) External Reference ● ● CONDITIONS ● ● ● GND 13 VDD 14 GND 15 ENC + 16 ENC – 17 SHDN 18 OE 19 CLOCKOUT 20 NC 21 OGND 22 OVDD 23 D0 24 UK PART MARKING* LTC2222UK-11 MIN 11 –1 –0.8 TYP ±0.15 ±0.1 ±0.5 ±0.1 MAX 1 0.8 UNITS Bits LSB LSB LSB LSB –37 –2.5 ±3 ±0.5 ±10 ±30 ±15 0.25 37 2.5 %FS µV/°C ppm/°C ppm/°C LSBRMS 222211f 2 U mV W U U WW W U LTC2222-11 A ALOG I PUT SYMBOL VIN VIN, CM IIN ISENSE IMODE tAP tJITTER CMRR The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ Analog Input Leakage Current SENSE Input Leakage MODE Pin Pull-Down Current to GND Sample and Hold Acquisition Delay Time Sample and Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth Figure 8 Test Circuit + AIN–)/2 CONDITIONS 3.1V < VDD < 3.5V Differential Input Drive Single Ended Input Drive 0 < AIN+, AIN– < VDD 0V < SENSE < 1V ● ● ● ● ● DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) SFDR Spurious Free Dynamic Range 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) S/(N+D) Signal-to-Noise Plus Distortion Ratio 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) IMD Intermodulation Distortion fIN1 = 138MHz, fIN2 = 140MHz ● ● ● U WU U MIN 1 0.5 –1 –1 TYP ±0.5 to ±1 1.6 1.6 MAX 1.9 2.1 1 1 UNITS V V V µA µA µA ns psRMS dB MHz 10 0 0.15 80 775 MIN 64.3 TYP 62.5 65.7 62.5 65.7 62.2 65.4 61.8 64.9 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc 71 84 84 84 84 81 81 77 77 88 88 88 88 88 88 85 85 64 62.5 65.6 62.5 65.6 81 222211f 3 LTC2222-11 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 3.1V < VDD < 3.5V –1mA < IOUT < 1mA CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VID VICM RIN CIN VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3.3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 3.3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance (Note 7) VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) CONDITIONS ENCODE INPUTS (ENC +, ENC –) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● LOGIC INPUTS (OE, SHDN) ● ● ● 4 U U U U U (Note 4) MIN 1.575 TYP 1.600 ±25 3 4 MAX 1.625 UNITS V ppm/°C mV/V Ω TYP MAX UNITS V 0.2 1.1 1.6 1.6 6 3 2 0.8 –10 3 10 2.5 Internally Set Externally Set (Note 7) ● V V kΩ pF V V µA pF 3 50 50 ● ● pF mA mA V V 0.4 V V V V V V 3.1 3.295 3.29 0.005 0.09 2.49 0.09 1.79 0.09 222211f LTC2222-11 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Analog Supply Current Power Dissipation Shutdown Power Nap Mode Power SHDN = High, OE = High, No CLK SHDN = High, OE = Low, No CLK CONDITIONS ● ● ● ● POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fS tL tH tAP tOE tD tC Pipeline Latency Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 105MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. PARAMETER Sampling Frequency ENC Low Time ENC High Time Sample-and-Hold Aperture Delay Output Enable Delay ENC to DATA Delay ENC to CLOCKOUT Delay DATA to CLOCKOUT Skew (Note 7) (Note 7) (Note 7) (tC - tD) (Note 7) ● ● ● ● TI I G CHARACTERISTICS UW MIN 3.1 0.5 TYP 3.3 3.3 144 475 2 35 MAX 3.5 3.6 162 535 UNITS V V mA mW mW mW UW CONDITIONS ● MIN 1 4.5 3 4.5 3 ● ● ● ● TYP 4.76 4.76 4.76 4.76 0 5 MAX 105 500 500 500 500 10 4 4 0.6 UNITS MHz ns ns ns ns ns ns ns ns ns Cycles Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On 1.3 1.3 –0.6 2.1 2.1 0 5 Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 000 0000 0000 and 111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 105MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. 222211f 5 LTC2222-11 TYPICAL PERFOR A CE CHARACTERISTICS INL, 2V Range 1.0 0.8 0.6 0.4 ERROR (LSB) ERROR (LSB) 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 512 1024 OUTPUT CODE 222211 G01 COUNT 1536 SNR vs Input Frequency, –1dB, 2V Range 68 67 66 SNR (dBFS) SNR (dBFS) 65 64 63 62 61 60 0 100 300 200 400 500 INPUT FREQUENCY (MHz) 600 70 69 68 67 66 65 64 63 62 61 60 SFDR (dBFS) SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range 100 95 90 85 SFDR (dBFS) SFDR (dBFS) 80 75 70 65 60 55 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 100 95 90 SFDR (dBFS) 6 UW 222211 G04 222211 G07 DNL, 2V Range 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2048 0 512 1024 OUTPUT CODE 222211 G02 Noise Histogram 140000 127161 120000 100000 80000 60000 40000 20000 0 1536 2048 0 1020 1186 1021 1022 CODE 222211 G03 2725 1023 0 1024 SNR vs Input Frequency, –1dB, 1V Range 100 95 90 85 80 75 70 65 60 55 0 100 300 400 500 200 INPUT FREQUENCY (MHz) 600 SFDR (HD2 and HD3) vs Input Frequency, –1dB, 2V Range 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 222211 G05 222211 G06 SFDR (HD4+) vs Input Frequency, –1dB, 2V Range 100 95 90 85 80 75 70 65 60 55 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 SFDR (HD4+) vs Input Frequency, –1dB, 1V Range 85 80 75 70 65 60 55 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 222211 G08 222211 G09 222211f LTC2222-11 TYPICAL PERFOR A CE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB 90 85 SFDR SFDR AND SNR (dBFS) 80 75 70 SNR SFDR AND SNR (dBFS) 75 70 65 60 IVDD (mA) 65 60 0 20 80 60 100 40 SAMPLE RATE (Msps) 10 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 100 90 8 SFDR (dBc AND dBFS) IOVDD (mA) 6 4 2 0 0 20 UW 120 SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, –1dB 90 85 80 SFDR IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 160 150 140 130 120 110 100 SNR 140 0 20 222211 G10 80 60 100 40 SAMPLE RATE (Msps) 120 140 0 20 222211 G11 80 120 60 100 40 SAMPLE RATE (Msps) 222211 G12 SFDR vs Input Level, f IN = 70MHz, 2V Range dBFS 80 70 60 50 dBc 40 30 20 10 40 60 80 SAMPLE RATE (Msps) 100 120 0 –60 –50 222211 G13 –30 –20 –40 INPUT LEVEL (dBFS) –10 0 222211 F14 222211f 7 LTC2222-11 TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, f IN = 5MHz, –1dB, 2V Range 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 222211 G15 FREQUENCY (MHz) AMPLITUDE (dB) –40 8192 Point FFT, f IN = 70MHz, –1dB, 2V Range 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 222211 G17 AMPLITUDE (dB) –40 8 UW 8192 Point FFT, f IN = 30MHz, –1dB, 2V Range –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 222211 G16 8192 Point FFT, f IN = 140MHz, –1dB, 2V Range –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 222211 G18 222211f LTC2222-11 PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN– (Pin 2): Negative Differential Analog Input. REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic capacitor. REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 3, 4 with 0.1µF ceramic chip capacitor. Do not connect to Pins 9, 10. REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor. Do not connect to Pins 3, 4. REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic capacitor. VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. Adjacent pins can share a bypass capacitor. GND (Pins 13, 15, 45, 48): ADC Power Ground. ENC + (Pin 16): Encode Input. The input is sampled on the positive edge. ENC – (Pin 17): Encode Complement Input. The input is sampled on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 18): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 19): Output Enable Pin. Refer to SHDN pin function. CLOCKOUT (Pin 20): Data Valid Output. Latch data on the falling edge of CLOCKOUT. NC (Pin 21): Do Not Connect This Pin. D0 – D10 (Pins 24, 25, 26, 29, 30, 31, 34, 35, 36, 39, 40): Digital Outputs. D10 is the MSB. OGND (Pins 22, 27, 32, 38): Output Driver Ground. OVDD (Pins 23, 28, 33, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitors. OF (Pin 41): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 42): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 43): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 44): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Exposed Pad (Pin 49): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. U U U 222211f 9 LTC2222-11 FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE AIN– SECOND PIPELINED ADC STAGE VCM 2.2µF 1.6V REFERENCE SHIFT REGISTER AND CORRECTION RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFLB REFHA 2.2µF 0.1µF 1µF Figure 1. Functional Block Diagram 10 W THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE REFL INTERNAL CLOCK SIGNALS OVDD OF DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • D10 D0 CLOCKOUT REFLA REFHB ENC 0.1µF 1µ F + 222211 F01 U U OGND ENC – M0DE SHDN OE 222211f LTC2222-11 TI I G DIAGRA S Timing Diagram tAP ANALOG INPUT N tH tL ENC – ENC + tD D0-D10, OF tC N–5 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 CLOCKOUT OE t OE DATA OF, D0-D10, CLOCKOUT t OE W UW 222211 TD01 222211f 11 LTC2222-11 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 12 U If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π) • fIN • tJITTER 222211f W U U LTC2222-11 APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2222-11 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The LTC2222-11 has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth U stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2222-11 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. LTC2222-11 VDD 15Ω CPARASITIC 1pF CSAMPLE 1.6pF CPARASITIC 1pF VDD CSAMPLE 1.6pF AIN+ VDD 15Ω AIN– 1.6V 6k ENC+ ENC– 6k 1.6V 222211 F02 W UU Figure 2. Equivalent Input Circuit 222211f 13 LTC2222-11 APPLICATIO S I FOR ATIO During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.6V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 44) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. 14 U Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2222-11 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2222-11 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω 25Ω 0.1µF 12pF 25Ω AIN– 222211 F03 W UU AIN+ LTC2222-11 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 3. Single-Ended to Differential Conversion Using a Transformer 222211f LTC2222-11 APPLICATIO S I FOR ATIO signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transVCM VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT 2.2µF AIN+ LTC2222-11 ANALOG INPUT 0.1µF 1k 1k 25Ω + CM + 12pF – – 25Ω AIN– 222211 F04 LTC6600-20, LT1993 Figure 4. Differential Drive with an Amplifier U former gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2222-11 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.6V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.6V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. 2.2µF AIN+ LTC2222-11 12pF 25Ω 0.1µF AIN– 222211 F05 W UU Figure 5. Single-Ended Drive 222211f 15 LTC2222-11 APPLICATIO S I FOR ATIO VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 12Ω 25Ω 12Ω 0.1µF 8pF AIN– AIN+ LTC2222-11 T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω AIN– 222211 F07 AIN+ 25Ω 0.1µF LTC2222-11 T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 4.7nH 25Ω 4.7nH 0.1µF 2pF AIN– 222211 F08 AIN+ LTC2222-11 T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA 16 U and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. LTC2222-11 1.6V VCM 2.2µF 4Ω 1.6V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE REFLB 0.1µF REFHA BUFFER INTERNAL ADC HIGH REFERENCE 0.5V 222211 F06 W UU TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µF 2.2µF 1µF DIFF AMP REFLA 0.1µF REFHB INTERNAL ADC LOW REFERENCE 222211 F09 Figure 9. Equivalent Reference Circuit 1.6V VCM 2.2µF SENSE 1µF LTC2222-11 12k 0.8V 12k 222211 F10 Figure 10. 1.6V Range ADC 222211f LTC2222-11 APPLICATIO S I FOR ATIO Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.2dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC2222-11 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. LTC2222-11 VDD TO INTERNAL ADC CIRCUITS 1.6V BIAS 6k ENC+ 0.1µF CLOCK INPUT 50Ω 1:4 VDD 1.6V BIAS 6k ENC– VDD Figure 11. Transformer Driven ENC+/ENC– U 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates The maximum encode rate for the LTC2222-11 is 105Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 4.5ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 20% to 80% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2222-11 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2222-11 is 1Msps. 222211 F11 W UU 222211f 17 LTC2222-11 APPLICATIO S I FOR ATIO DIGITAL OUTPUTS Digital Output Buffers Figure 13 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2222-11 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full speed operation the capacitive load should be kept under 5pF. Lower OVDD voltages will also help reduce interference from the digital outputs and improve the SNR. Data Format The LTC2222-11 parallel digital output can be selected for offset binary or 2’s complement format. The format is ENC+ 1.6V ENC– LTC2222-11 0.1µF 222211 F12a VTHRESHOLD = 1.6V Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 130Ω Q0 130Ω ENC+ ENC– LTC2222-11 83Ω 83Ω 222211 F12b D0 Q0 Figure 12b. ENC Drive Using a CMOS to PECL Translator 18 U selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 1 shows the logic states for the MODE pin. Table 1. MODE Pin Function MODE Pin 0 1/3VDD 2/3VDD VDD Output Format Offset Binary Offset Binary 2’s Complement 2’s Complement Clock Duty Cycle Stablizer Off On On Off W UU Overflow Bit The converter is either overranged or underranged when OF outputs a logic high. Output Clock The ADC has a delayed version of the ENC+ input available as a digital output, CLOCKOUT. The CLOCKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated just after CLOCKOUT rises and can be latched on the falling edge of CLOCKOUT. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied LTC2222-11 OVDD VDD VDD 0.5V TO 3.6V 0.1µF OVDD DATA FROM LATCH OE OGND PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT 222211 F13 Figure 13. Digital Output Buffer 222211f LTC2222-11 APPLICATIO S I FOR ATIO to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any voltage up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF and CLOCKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 35mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state. U GROUNDING AND BYPASSING The LTC2222-11 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown on the schematic on Page 20 of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2µF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2222-11 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. HEAT TRANSFER Most of the heat generated by the LTC2222-11 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. 222211f W UU 19 LTC2222-11 APPLICATIO S I FOR ATIO U VCC CLOCKOUT JP1 VCC CLOCKOUT R19 OPT ANALOG INPUT J1 C1 0.1µF R1* T1* R2 24.9k C2* R4 24.9k C3 0.1µF VCM R5 50Ω C4 0.1µF R6* 1 2 3 4 13 C5 1µF C6 0.1µF 15 5 C7 2.2µF 6 7 8 C8 1µF C9 0.1µF 9 10 VDD VDD 46 47 11 12 14 CLK SHDN C11 33pF CLK 16 17 18 19 44 C15 2.2µF JP4 MODE VDD R12 1k R13 1k R14 1k C22 0.1µF VDD 43 42 C10 0.1µF C12 0.1µF VDD JP2 GND C13 0.1µF JP3 SENSE VDD VDD VCM EXT REF VCM EXT REF 2/3VDD 1/3VDD C24 0.1µF GND VCC VDD ENCODE INPUT C23 J3 0.1µF R16 100Ω C27 10µF 6.3V R17 105k R18 100k C28 0.01µF U6 LT1763 1 8 OUT IN 2 7 ADJ GND 3 6 GND GND 4 5 BYP SHDN C34 1µF 20 W UU Evaluation Circuit Schematic of the LTC2222-11 34 45 VCC GND GND GND VCC 2LE 1LE 2OE 1OE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 U3 GND VCC GND GND VCC GND GND VCC 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 28 31 21 15 18 10 4 7 2 3 5 6 8 9 11 12 13 14 16 17 RN1D 33Ω RN1C 33Ω RN1B 33Ω RN1A 33Ω RN2D 33Ω RN2C 33Ω RN2B 33Ω RN2A 33Ω RN3D 33Ω RN3C 33Ω RN3B 33Ω RN3A 33Ω D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 C33 0.1µF 1 2 5 NC7SV865X 4 R3 33Ω 39 42 25 48 24 1 47 U2 3 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 C17 0.1µF 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 3201S-40G1 U1 LTC2222-11 20 AIN+ CLOCKOUT 21 AIN– NC 24 REFHA D0 25 REFHA D1 26 GND D2 29 GND D3 30 REFLB D4 31 REFLB D5 34 REFHB D6 35 REFHB D7 36 REFLA D8 39 REFLA D9 40 VDD D10 41 VDD OF 37 VDD OVDD 33 VDD OVDD 28 VDD OVDD 23 + ENC OVDD 38 ENC– OGND 32 SHDN OGND 27 OE OGND 22 VCM OGND 48 SENSE GND 45 MODE GND GND 49 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2Q4 19 2Q5 20 2Q6 2Q7 2Q8 22 23 PI74VCX16373A VCC NC7SV865X 4 5 U5 3 1 2 C16 0.1µF 1 R10 10k R9 10k R8 10k 1 8 A0 U4 VCC 2 7 A1 WP 3 6 A2 SCL 4 5 A3 SDA 24LC025 222211 AI01 VDD GND C25 4.7µF PWR GND VDD 3.3V VCC C29 0.1µF C30 0.1µF C31 0.1µF C32 0.1µF C21 0.1µF C20 0.1µF Assembly Type DC751A-M VCC U1 LTC2222CUK-11 LTC2222CUK-11 R1, R6 24.9Ω 12.4Ω C2 12pF 8.2pF T1 ETC1-1T ETC1-1-13 C19 0.1µF DC751A-N *Version Type CLK C18 0.1µF T2 ETC1-1T R15 100Ω CLK C26 0.1µF 222211f LTC2222-11 APPLICATIO S I FOR ATIO Layer 1 Component Side U Silkscreen Top Layer 2 GND Plane 222211f W UU 21 LTC2222-11 APPLICATIO S I FOR ATIO Layer 3 Power Plane 22 U Layer 4 Bottom Side 222211f W UU LTC2222-11 PACKAGE DESCRIPTIO 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 7.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP PIN 1 TOP MARK (SEE NOTE 6) PIN 1 CHAMFER Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UK Package 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704) 0.70 ± 0.05 5.15 ± 0.05 6.10 ± 0.05 7.50 ± 0.05 (4 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PACKAGE OUTLINE 47 48 0.40 ± 0.10 1 2 5.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD (UK48) QFN 1103 222211f 23 LTC2222-11 RELATED PARTS PART NUMBER LTC1747 LTC1748 LTC1749 LTC1750 LT1993 LTC2220 LTC2220-1 LTC2221 LTC2222 LTC2223 LTC2224 LTC2225 LTC2228 LTC2229 LTC2230 LTC2231 LTC2232 LTC2233 LTC2234 LTC2248 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2292 LTC2293 LTC2294 LTC2297 LTC2298 LTC2299 LT5512 LT5514 LT5522 DESCRIPTION 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps Wideband ADC High Speed Differential Op Amp 12-Bit, 170Msps ADC 12-Bit, 185Msps ADC 12-Bit, 135Msps ADC 12-Bit, 105Msps ADC 12-Bit, 80Msps ADC 12-Bit, 135Msps ADC 12-Bit, 10Msps ADC 12-Bit, 65Msps ADC 12-Bit, 80Msps ADC 10-Bit, 170Msps ADC 10-Bit, 135Msps ADC 10-Bit, 105Msps ADC 10-Bit, 80Msps ADC 10-Bit, 135Msps ADC 14-Bit, 65Msps ADC 14-Bit, 80Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps ADC Dual 12-Bit, 40Msps ADC Dual 12-Bit, 65Msps ADC Dual 12-Bit, 80Msps ADC Dual 14-Bit, 40Msps ADC Dual 14-Bit, 65Msps ADC Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 600MHz BW, 75dBc Distortion at 70MHz 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.5dB SNR, 9mm x 9mm QFN Package 660mW, 67.5dB SNR, 9mm x 9mm QFN Package 475mW, 67.9dB SNR, 7mm x 7mm QFN Package 366mW, 68dB SNR, 7mm x 7mm QFN Package 660mW, 67.5dB SNR, 7mm x 7mm QFN Package 60mW, 71.4dB SNR, 5mm x 5mm QFN Package 210mW, 71dB SNR, 5mm x 5mm QFN Package 230mW, 71.6dB SNR, 5mm x 5mm QFN Package 890mW, 61dB SNR, 9mm x 9mm QFN Package 660mW, 61dB SNR, 9mm x 9mm QFN Package 475mW, 61dB SNR, 7mm x 7mm QFN Package 366mW, 61dB SNR, 7mm x 7mm QFN Package 660mW, 61dB SNR, 7mm x 7mm QFN Package 210mW, 74dB SNR, 5mm x 5mm QFN Package 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 61.6dB SNR, 5mm x 5mm QFN Package 395mW, 61.6dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 320mW, 72.5dB SNR, 5mm x 5mm QFN Package 395mW, 72.4dB SNR, 5mm x 5mm QFN Package 240mW, 71dB SNR, 9mm x 9mm QFN Package 410mW, 71dB SNR, 9mm x 9mm QFN Package 445mW, 70.6dB SNR, 9mm x 9mm QFN Package 240mW, 74dB SNR, 9mm x 9mm QFN Package 410mW, 74dB SNR, 9mm x 9mm QFN Package 445mW, 73dB SNR, 9mm x 9mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 222211f 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/TP 0805 500 • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005