TC1301B

TC1301A/B Dual LDO with Microcontroller RESET Function Features • Dual Output LDO with Microcontroller Reset Monitor Functionality: - VOUT1 = 1.5V to 3.3V @ 300 mA - VOUT2 = 1.5V to 3.3V @ 150 mA - VRESET = 2.20V to 3.20V • Output Voltage and RESET Threshold Voltage Options Available (See Table 8-1) • Low Dropout Voltage: - VOUT1 = 104 mV @ 300 mA (typical) - VOUT2 = 150 mV @ 150 mA, (typical) • Low Supply Current: 116 µA (typical), TC1301A/B with both output voltages available • Reference Bypass Input for Low-Noise Operation • Both Output Voltages Stable with a Minimum of 1 µF Ceramic Output Capacitor • Separate Input for RESET Detect Voltage (TC1301A) • Separate VOUT1 and VOUT2 SHDN pins (TC1301B) • RESET Output Duration: 300 ms (typical) • Power-Saving Shutdown Mode of Operation • Wake-up from SHDN: 5.3 µs (typical) • Small 8-pin DFN and MSOP Package Options • Operating Junction Temperature Range: - -40°C to +125°C • Overtemperature and Overcurrent Protection Description The TC1301A/B combines two Low Dropout (LDO) regulators and a microcontroller RESET function into a single 8-pin MSOP or DFN package. Both regulator outputs feature low dropout voltage, 104 mV @ 300 mA for VOUT1, 150 mV @ 150 mA for VOUT2, low quiescent current consumption, 58 µA each and a typical regulation accuracy of 0.5%. Several fixedoutput voltage and detector voltage combinations are available. A reference bypass pin is available to further reduce output noise and improve the power supply rejection ratio of both LDOs. The TC1301A/B is stable over all line and load conditions with a minimum of 1 µF of ceramic output capacitance, and utilizes a unique compensation scheme to provide fast dynamic response to sudden line voltage and load current changes. For the TC1301A, the microcontroller RESET function operates independently of both VOUT1 and VOUT2. The input to the RESET function is connected to the VDET pin.The SHDN2 pin is used to control the output of VOUT2 only. VOUT1 will power-up and down with VIN. In the case of the TC1301B, the detect voltage input of the RESET function is connected internally to VOUT1. Both VOUT1 and VOUT2 have independent shutdown capability. Additional features include an overcurrent limit and overtemperature protection that, when combined, provide a robust design for all load fault conditions. Applications • • • • • • Cellular/GSM/PHS Phones Battery-Operated Systems Hand-Held Medical Instruments Portable Computers/PDAs Linear Post-Regulators for SMPS Pagers Package Types 8-Pin DFN/MSOP TC1301A DFN8 RESET 1 VOUT1 2 GND 3 Bypass 4 8 VDET 7 VIN 6 VOUT2 5 SHDN2 RESET 1 VOUT1 2 GND 3 Bypass 4 MSOP8 8 VDET 7 VIN 6 VOUT2 5 SHDN2 Related Literature • AN765, “Using Microchip’s Micropower LDOs”, DS00765, Microchip Technology Inc., 2002 • AN766, “Pin-Compatible CMOS Upgrades to BiPolar LDOs”, DS00766, Microchip Technology Inc., 2002 • AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application”, DS00792, Microchip Technology Inc., 2001 TC1301B DFN8 RESET 1 VOUT1 2 GND 3 Bypass 4 8 SHDN1 7 VIN 6 VOUT2 5 SHDN2 RESET 1 VOUT1 2 GND 3 Bypass 4 MSOP8 8 SHDN1 7 VIN 6 VOUT2 5 SHDN2 © 2008 Microchip Technology Inc. DS21798C-page 1 TC1301A/B Functional Block Diagrams TC1301A VIN LDO #1 300 mA VOUT1 VIN SHDN1 LDO #1 300 mA TC1301B VOUT1 VOUT2 SHDN2 LDO #2 150 mA SHDN2 LDO #2 150 mA VOUT2 Bypass Bypass VDET RESET VOUT1 RESET 2.7V to 4.2V BATTERY CIN 1 µF 2.7V to 4.2V GND Bandgap Reference 1.2V GND Bandgap Reference 1.2V Threshold Detector Time Delay 300 ms typ VDET Threshold Detector Time Delay 300 ms, typ Typical Application Circuits TC1301A System RESET 2.8V @ 300 mA COUT1 1 µF Ceramic X5R CBYPASS(Note) 10 nF Ceramic 1 RESET VDET 8 VIN 7 VOUT2 6 2.6V @ 150 mA 5 BATTERY CIN 1 µF 2V OUT1 3 4 GND Bypass SHDN2 COUT2 1 µF Ceramic X5R ON/OFF Control VOUT2 ON/OFF Control VOUT1 TC1301B System RESET 2.8V @ 300 mA COUT1 1 µF Ceramic X5R 1 RESET SHDN1 8 2V OUT1 3 4 GND VIN 7 VOUT2 6 2.6V @ 150 mA 5 Bypass SHDN2 COUT2 1 µF Ceramic X5R Note: CBYPASS is optional ON/OFF Control VOUT2 DS21798C-page 2 © 2008 Microchip Technology Inc. TC1301A/B 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD...................................................................................6.5V Maximum Voltage on Any Pin ...... (VSS – 0.3) to (VIN + 0.3)V Power Dissipation ..........................Internally Limited (Note 7) Storage temperature .....................................-65°C to +150°C Maximum Junction Temperature, TJ ........................... +150°C Continuous Operating Temperature Range ..-40°C to +125°C ESD protection on all pins, HBM, MM ..................... 4 kV, 400V DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF, CBYPASS = 10 nF, SHDN > VIH, TA = +25°C. Boldface type specifications apply for junction temperatures of -40°C to +125°C. Parameters Input Operating Voltage Maximum Output Current Maximum Output Current Output Voltage Tolerance (VOUT1 and VOUT2) Temperature Coefficient (VOUT1 and VOUT2) Line Regulation (VOUT1 and VOUT2) Load Regulation, VOUT ≥ 2.5V (VOUT1 and VOUT2) Load Regulation, VOUT < 2.5V (VOUT1 and VOUT2) Thermal Regulation Dropout Voltage (Note 6) VOUT1 ≥ 2.7V VOUT2 ≥ 2.6V Supply Current TC1301A TC1301B Note 1: 2: 3: 4: IIN(A) IIN(B) — — 103 114 180 180 µA µA SHDN2 = VIN, VDET = OPEN, IOUT1 = IOUT2 = 0 mA SHDN1 = SHDN2 = VIN, IOUT1 = IOUT2 = 0 mA VIN – VOUT VIN – VOUT — — 104 150 180 250 mV mV IOUT1 = 300 mA IOUT2 = 150 mA Sym VIN IOUT1Max IOUT2Max VOUT TCVOUT ΔVOUT/ ΔVIN ΔVOUT/ VOUT ΔVOUT/ VOUT ΔVOUT/ΔPD Min 2.7 300 150 Typ — — — Max 6.0 — — Units V mA mA % ppm/°C %/V % % %/W Note 1 VIN = 2.7V to 6.0V (Note 1) VIN = 2.7V to 6.0V (Note 1) Note 2 Note 3 (VR+1V) ≤ VIN ≤ 6V IOUTX = 0.1 mA to IOUTMax (Note 4) IOUTX = 0.1 mA to IOUTMax (Note 4) Note 5 Conditions VR – 2.5 VR±0.5 VR + 2.5 — — -1 -1.5 — 25 0.02 0.1 0.1 0.04 — 0.2 +1 +1.5 — 5: 6: The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT. VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2). TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT). Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 ms. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction-to-air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. 7: © 2008 Microchip Technology Inc. DS21798C-page 3 TC1301A/B DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF, CBYPASS = 10 nF, SHDN > VIH, TA = +25°C. Boldface type specifications apply for junction temperatures of -40°C to +125°C. Parameters Shutdown Supply Current TC1301A Shutdown Supply Current TC1301B Power Supply Rejection Ratio Output Noise Sym IIN_SHDNA IIN_SHDNB PSRR eN Min — — — — Typ 58 0.1 58 830 Max 90 1 — — Units µA µA dB nV/(Hz)½ Conditions SHDN2 = GND, VDET = OPEN SHDN1 = SHDN2 = GND f ≤ 100 Hz, IOUT1 = IOUT2 = 50 mA, CIN = 0 µF f ≤ 1 kHz, IOUT1 = IOUT2 = 50 mA, CIN = 0 µF RLOAD1 ≤ 1Ω RLOAD2 ≤ 1Ω VIN = 2.7V to 6.0V VIN = 2.7V to 6.0V VIN = 5V, IOUT1 = IOUT2 = 30 mA, See Figure 5-1 VIN = 5V, IOUT1 = IOUT2 = 50 mA, See Figure 5-2 VIN = 5V, IOUT1 = IOUT2 = 100 µA VIN = 5V TA = 0°C to +70°C TA = -40°C to +125°C Output Short-Circuit Current (Average) VOUT1 VOUT2 SHDN Input High Threshold SHDN Input Low Threshold Wake-Up Time (From SHDN mode), (VOUT2) Settling Time (From SHDN mode), (VOUT2) Thermal Shutdown Die Temperature Thermal Shutdown Hysteresis Voltage Range IOUTsc IOUTsc VIH VIL tWK tS TSD THYS VDET — — 45 — — — — — 1.0 1.2 200 140 — — 5.3 50 150 10 — — — — 15 20 — — — 6.0 6.0 mA mA %VIN %VIN µs µs °C °C V RESET Threshold VTH ΔVTH/ΔT tRPD tRPU -1.4 -2.8 — — 30 180 300 +1.4 +2.8 — — 560 % % ppm/°C µs ms VDET = VTH to (VTH – 100 mV), See Figure 5-3 VDET = VTH - 100 mV to VTH + 100 mV, ISINK = 1.2 mA, See Figure 5-3. VDET = VTHmin, ISINK = 1.2 mA, ISINK = 100 µA for VDET < 1.8V, See Figure 5-3 VDET > VTHmax, ISOURCE = 500 µA, See Figure 5-3 TA = -40°C to +125°C RESET Threshold Tempco VDET RESET Delay RESET Active Time-out Period — — 140 RESET Output Voltage Low VOL — 0.9 VDET — 0.2 V RESET Output Voltage High Note 1: 2: 3: 4: VOH — — V 5: 6: The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT. VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2). TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT). Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 ms. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction-to-air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. 7: DS21798C-page 4 © 2008 Microchip Technology Inc. TC1301A/B TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits are specified for: VIN = +2.7V to +6.0V. Parameters Temperature Ranges Operating Junction Temperature Range Storage Temperature Range Maximum Junction Temperature Thermal Package Resistances Thermal Resistance, 8LD MSOP Thermal Resistance, 8LD DFN θJA θJA — — 208 41 — — °C/W Typical 4-Layer Board °C/W Typical 4-Layer Board with Vias TA TA TJ -40 -65 — — — — +125 +150 +150 °C °C °C Transient Steady State Sym Min Typical Max Units Conditions © 2008 Microchip Technology Inc. DS21798C-page 5 TC1301A/B 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C. 350 Quiescent Current (µA) 300 250 200 150 100 50 0 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0 Input Voltage (V) 2.60 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 Input Voltage (V) 6 VOUT2 Active VOUT2 SHDN TC1301B Output Voltage (V) TJ = 25°C IOUT1 = IOUT2 = 0 µA VOUT1 Active 3.00 2.90 VOUT1 TJ = 25°C IOUT1 = 100 mA IOUT2 = 50 mA 2.80 2.70 VOUT2 FIGURE 2-1: Voltage. 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.7 3 Quiescent Current vs. Input FIGURE 2-4: Voltage. 2.90 2.85 Output Voltage (V) Output Voltage vs. Input SHDN Threshold (V) VOUT1 ON 2.80 2.75 2.70 2.65 2.60 2.55 2.50 VOUT2 TJ = +25°C IOUT1 = 300 mA IOUT2 = 100 mA OFF 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 Input Voltage (V) 6 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 Input Voltage (V) 6 FIGURE 2-2: vs. Input Voltage. 140 130 120 110 100 90 80 70 60 50 40 SHDN Voltage Threshold FIGURE 2-5: Voltage. 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0 50 Output Voltage vs. Input TC1301B VOUT2 Active Quiescent Current (µA) VIN = 4.2V IOUT1 = IOUT2 = 0 µA VOUT1 Active Dropout Voltage VOUT1 (mV) VR1 = 2.8V VR2 = 2.6V IOUT2 = 100 µA TJ = +125°C TJ = +25°C VOUT2 SHDN TJ = - 40°C -40 -25 -10 5 20 35 50 65 80 95 110 125 100 150 IOUT1 (mA) 200 250 300 Junction Temperature (°C) FIGURE 2-3: Quiescent Current vs. Junction Temperature. FIGURE 2-6: Current (VOUT1). Dropout Voltage vs. Output DS21798C-page 6 © 2008 Microchip Technology Inc. TC1301A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C. 140 120 100 80 60 IOUT1 = 100 mA Dropout Voltage VOUT1 (mV) Load Regulation (%) VR1 = 2.8V VR2 = 2.6V IOUT2 = 100 µA 0.40 IOUT1 = 300 mA 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 VR1 = 2.8V VR2 = 2.6V VIN = 4.2 VOUT2 IOUT2 = 0.1 mA to 150 mA VOUT1 IOUT1 = 0.1 mA to 300 mA 40 20 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 IOUT1 = 50 mA -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) Junction Temperature (125°C) FIGURE 2-7: Dropout Voltage vs. Junction Temperature (VOUT1). Dropout Voltage, VOUT2 (mv) 180 160 140 120 100 80 60 40 20 0 0 30 60 90 120 150 FIGURE 2-10: VOUT1 and VOUT2 Load Regulation vs. Junction Temperature. 0.045 TJ = +125°C TJ = +25°C TJ = - 40°C Line Regulation (%/V) VR1 = 2.8V VR2 = 2.6V IOUT1 = 100 µA 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0.000 VOUT1 VOUT2 VIN = 3.8V to 6.0V VR1 = 2.8V, IOUT1 = 100 µA VR2 = 2.6V, IOUT2 = 100 µA IOUT2 (mA) -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) FIGURE 2-8: Current (VOUT2). 180 160 140 120 100 80 60 40 20 0 -40 -25 -10 5 Dropout Voltage vs. Output FIGURE 2-11: VOUT1 and VOUT2 Line Regulation vs. Junction Temperature. 2.832 Dropout Voltage VOUT2 (mV) IOUT2 = 150 mA VR1 = 2.8V VR2 = 2.6V IOUT1 = 100 µA Output Voltage VOUT1 (V) 2.828 2.824 2.820 2.816 2.812 2.808 VIN = 4.2V VR1 = 2.8V VR2 = 2.6V, IOUT2 = 100 µA IOUT1 = 300 mA IOUT1 = 100 mA IOUT2 = 50 mA IOUT1 = 100 µA IOUT2 = 10 mA 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) Junction Temperature (°C) FIGURE 2-9: Dropout Voltage vs. Junction Temperature (VOUT2). FIGURE 2-12: Temperature. VOUT1 vs. Junction © 2008 Microchip Technology Inc. DS21798C-page 7 TC1301A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C. 2.856 Output Voltage VOUT1 (V) 2.848 2.840 2.832 2.824 2.816 2.808 -40 -25 -10 5 20 35 50 65 80 95 110 125 VIN = 4.2V VIN = 6.0V VR1 = 2.8V, IOUT1 = 300 mA VR2 = 2.6V, IOUT2 = 100 µA VIN = 3.0V 30 25 IVDET (µA) 20 15 10 5 0 VR1 = 2.8V VR2 = 2.6V VDET = 6.0V VDET = 4.2V VDET = 3.0V -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) Junction Temperature (°C) FIGURE 2-13: Temperature. 2.645 Output Voltage VOUT2 (V) VOUT1 vs. Junction FIGURE 2-16: Temperature. 400 RESET Active Time (ms) IDET current vs. Junction 2.640 2.635 2.630 2.625 2.620 2.615 -40 -25 -10 5 IOUT2 = 100 µA IOUT2 = 50 mA 375 350 325 300 275 250 225 200 -40 -25 -10 5 VIN = 4.2V VR1 = 2.8V VR2 = 2.6V VDET = 2.63V IOUT2 = 150 mA VIN = 4.2V VR1 = 2.8V, IOUT1 = 100 µA VR2 = 2.6V 20 35 50 65 80 95 110 125 20 35 50 65 80 95 110 125 Junction Temperature (°C) Junction Temperature (°C) FIGURE 2-14: Temperature. 2.644 Output Voltage VOUT2 (V) 2.640 2.636 2.632 2.628 2.624 -40 -25 -10 5 VOUT2 vs. Junction FIGURE 2-17: RESET Active Time vs. Junction Temperature. 2.6395 2.6390 VR1 = 2.8V, IOUT1 = 100 µA VR2 = 2.6V, IOUT2 = 150 mA VIN = 4.2V VIN = 3.0V VDET Trip Point (V) 2.6385 2.6380 2.6375 2.6370 2.6365 2.6360 2.6355 VIN = 4.2V VR1 = 2.8V VR2 = 2.6V VDET = 2.63V VIN = 6.0V 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) Junction Temperature (°C) FIGURE 2-15: Temperature. VOUT2 vs. Junction FIGURE 2-18: Temperature. VDET Trip Point vs. Junction DS21798C-page 8 © 2008 Microchip Technology Inc. TC1301A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C. 10 NOISE (μV/ Hz) 1 0.1 0.01 VIN = 4.2V VR1 = 2.8V VR2=2.6V IOUT1 = 150 mA IOUT2 = 100 mA CBYPASS = 10 nF VOUT1 VOUT2 0.001 0.01 0.1 1 10 100 1000 Frequency (KHz) FIGURE 2-19: Power Supply Rejection Ratio vs. Frequency (without bypass capacitor). FIGURE 2-22: VOUT1 and VOUT2 Noise vs. Frequency (with bypass capacitor). FIGURE 2-20: Power Supply Rejection Ratio vs. Frequency (with bypass capacitor). 10 VOUT2 FIGURE 2-23: VOUT1 and VOUT2 Power-up from Shutdown TC1301B. NOISE (μV/ Hz) 1 VIN = 4.2V VR1 = 2.8V VR2=2.6V IOUT1 = 150 mA IOUT2 = 100 mA CBYPASS = 0 nF VOUT1 0.1 0.01 0.01 0.1 1 10 100 1000 Frequency (KHz) FIGURE 2-21: VOUT1 and VOUT2 Noise vs. Frequency (without bypass capacitor). FIGURE 2-24: VOUT2 Power-up from Shutdown Input TC1301A. © 2008 Microchip Technology Inc. DS21798C-page 9 TC1301A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C. FIGURE 2-25: VOUT1 and VOUT2 Power-up from Input Voltage TC1301B. FIGURE 2-28: VOUT2. 150 mA Dynamic Load Step FIGURE 2-26: Dynamic Line Response. FIGURE 2-29: TC1301B. RESET Power-Up From VIN FIGURE 2-27: VOUT1. 300 mA Dynamic Load Step FIGURE 2-30: Down. TC1301A RESET Power- DS21798C-page 10 © 2008 Microchip Technology Inc. TC1301A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C. 0.35 0.30 RESET VOL (V) 0.25 0.20 0.15 0.10 0.05 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) IOL = 1.2 mA VR1 = 2.8V,VR2 = 2.6V VDET = VTH - 20 mV IOL = 3.2 mA 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 RESET VOH (V) VR1 = 2.8V,VR2 = 2.6V VDET = VTH + 20 mV VDET = 4.2V RESETISOURCE = 800 µA VDET = 3.0V RESETISOURCE = 500 µA -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (°C) FIGURE 2-31: RESET Output Voltage Low vs. Junction Temperature. FIGURE 2-32: RESET Output Voltage High vs. Junction Temperature. © 2008 Microchip Technology Inc. DS21798C-page 11 TC1301A/B 3.0 TC1301A PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. 1 2 3 4 5 6 7 8 TC1301A PIN FUNCTION TABLE Name RESET VOUT1 GND Bypass SHDN2 VOUT2 VIN VDET Function Push-pull output pin that will remain low while VDET is below the reset threshold and for 300 ms after VDET rises above the reset threshold. Regulated output voltage #1 capable of 300 mA. Circuit ground pin. Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce output noise and improve PSRR performance. Output #2 shutdown control Input. Regulated output voltage #2 capable of 150 mA. Unregulated input voltage pin. Input pin for Voltage Detector (VDET). 3.1 RESET Output Pin 3.5 The push-pull output pin is used to monitor the voltage on the VDET pin. If the VDET voltage is less than the threshold voltage, the RESET output will be held in the low state. As the VDET pin rises above the threshold, the RESET output will remain in the low state for 300 ms and then change to the high state, indicating that the voltage on the VDET pin is above the threshold. Output Voltage #2 Shutdown (SHDN2) ON/OFF control is performed by connecting SHDN2 to its proper level. When the input of this pin is connected to a voltage less than 15% of VIN, VOUT2 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT2 will be turned ON. 3.6 3.2 Regulated Output Voltage #1 (VOUT1) Regulated Output Voltage #2 (VOUT2) Connect VOUT1 to the positive side of the VOUT1 capacitor and load. It is capable of 300 mA maximum output current. VOUT1 output is available when VIN is available; there is no pin to turn it OFF. See TC1301B if ON/OFF control of VOUT1 is desired. Connect VOUT2 to the positive side of the VOUT2 capacitor and load. This pin is capable of a maximum output current of 150 mA. VOUT2 can be turned ON and OFF using SHDN2. 3.7 Unregulated Input Voltage Pin (VIN) 3.3 Circuit Ground Pin (GND) Connect GND to the negative side of the input and output capacitor. Only the LDO internal circuitry bias current flows out of this pin (200 µA maximum). Connect the unregulated input voltage source to VIN. If the input voltage source is located more than several inches away, or is a battery, a typical input capacitance of 1 µF to 4.7 µF is recommended. 3.4 Reference Bypass Input 3.8 By connecting an external 10 nF capacitor (typical) to the bypass input, both outputs (VOUT1 and VOUT2) will have less noise and improved Power Supply Ripple Rejection (PSRR) performance. The LDO output voltage start-up time will increase with the addition of an external bypass capacitor. By leaving this pin unconnected, the start-up time will be minimized. Input Pin for Voltage Detector (VDET) The voltage on the input of VDET is compared with the preset VDET threshold voltage. If the voltage is below the threshold, the RESET output will be low. If the voltage is above the VDET threshold, the RESET output will be high after the RESET time period. The IDET supply current is typically 9 µA at room temperature, with VDET = 3.8V. DS21798C-page 12 © 2008 Microchip Technology Inc. TC1301A/B 4.0 TC1301B PIN DESCRIPTIONS The descriptions of the pins are listed in Table 4-1. TABLE 4-1: Pin No. 1 2 3 4 5 6 7 8 TC1301B PIN FUNCTION TABLE Name RESET VOUT1 GND Bypass SHDN2 VOUT2 VIN SHDN1 Function Push-pull output pin that will remain low while VDET is below the reset threshold and for 300 ms after VOUT1 rises above the reset threshold Regulated output voltage #1 capable of 300 mA Circuit ground pin Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce output noise and improve PSRR performance Output #2 shutdown control Input Regulated output voltage #2 capable of 150 mA Unregulated input voltage pin Output #1 shutdown control input 4.1 RESET Output Pin 4.5 The push-pull output pin is used to monitor the output voltage (VOUT1). If VOUT1 is less than the threshold voltage, the RESET output will be held in the low state. As VOUT1 rises above the threshold, the RESET output will remain in the low state for 300 ms and then change to the high state, indicating that the voltage on VOUT1 is above the threshold. Output Voltage #2 Shutdown (SHDN2) ON/OFF control is performed by connecting SHDN2 to its proper level. When this pin is connected to a voltage less than 15% of VIN, VOUT2 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT2 will be turned ON. 4.2 Regulated Output Voltage #1 (VOUT1) 4.6 Regulated Output Voltage #2 (VOUT2) Connect VOUT1 to the positive side of the VOUT1 capacitor and load. It is capable of 300 mA maximum output current. For the TC1301B, VOUT1 can be turned ON and OFF using the SHDN1 input pin. Connect VOUT2 to the positive side of the VOUT2 capacitor and load. This pin is capable of a maximum output current of 150 mA. VOUT2 can be turned ON and OFF using SHDN2. 4.3 Circuit Ground Pin (GND) 4.7 Unregulated Input Voltage Pin (VIN) Connect GND to the negative side of the input and output capacitor. Only the LDO internal circuitry bias current flows out of this pin (200 µA maximum). 4.4 Reference Bypass Input Connect the unregulated input voltage source to VIN. If the input voltage source is located more than several inches away or is a battery, a typical minimum input capacitance of 1 µF and 4.7 µF is recommended. By connecting an external 10 nF capacitor (typical) to bypass, both outputs (VOUT1 and VOUT2) will have less noise and improved Power Supply Ripple Rejection (PSRR) performance. The LDO output voltage start-up time will increase with the addition of an external bypass capacitor. By leaving this pin unconnected, the start-up time will be minimized. 4.8 Output Voltage #1 Shutdown (SHDN1) ON/OFF control is performed by connecting SHDN1 to its proper level. When this pin is connected to a voltage less than 15% of VIN, VOUT1 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT1 will be turned ON. © 2008 Microchip Technology Inc. DS21798C-page 13 TC1301A/B 5.0 5.1 DETAILED DESCRIPTION Device Overview the LDO as is practical. Larger input capacitors will help reduce the input impedance and further reduce any high-frequency noise on the input and output of the LDO. The TC1301A/B is a combination device consisting of one 300 mA LDO regulator with a fixed output voltage, VOUT1 (1.5V – 3.3V), one 150 mA LDO regulator with a fixed output voltage, VOUT2 (1.5V – 3.3V), and a microcontroller voltage monitor/RESET (2.2V to 3.2V). For the TC1301A, the 300 mA output (VOUT1) is always present, independent of the level of SHDN2. The 150 mA output (VOUT2) can be turned on/off by controlling the level of SHDN2. For the TC1301B, VOUT1 and VOUT2 each have independent shutdown input pins (SHDN1 and SHDN2) to control their respective outputs. In the case of the TC1301B, the voltage detect input of the microcontroller RESET function is internally connected to the VOUT1 output of the device. 5.6 Output Capacitor 5.2 LDO Output #1 LDO output #1 is rated for 300 mA of output current. The typical dropout voltage for VOUT1 = 104 mV @ 300 mA. A 1 µF (minimum) output capacitor is needed for stability and should be located as close to the VOUT1 pin and ground as possible. A minimum output capacitance of 1 µF for each of the TC1301A/B LDO outputs is necessary for stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Electrolytic (Tantalum or Aluminum) capacitors can be used on the LDO outputs as well. The Equivalent Series Resistance (ESR) requirements on the electrolytic output capacitors are between 0 and 2 ohms. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials, X7R and X5R, have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 uF X5R 0805 capacitor has an ESR of 50 milliohms. Larger LDO output capacitors can be used with the TC1301A/B to improve dynamic performance and power supply ripple rejection performance. A maximum of 10 µF is recommended. Aluminum electrolytic capacitors are not recommended for low temperature applications of < -25°C. 5.7 Bypass Input 5.3 LDO Output #2 LDO output #2 is rated for 150 mA of output current. The typical dropout voltage for VOUT2 = 150 mV. A 1 µF (minimum) capacitor is needed for stability and should be located as close to the VOUT2 pin and ground as possible. 5.4 RESET Output The bypass pin is connected to the internal LDO reference. By adding capacitance to this pin, the LDO ripple rejection, input voltage transient response and output noise performance are all increased. A typical bypass capacitor between 470 pF to 10 nF is recommended. Larger bypass capacitors can be used, but results in a longer time-period for the LDO outputs to reach their rated output voltage when started from SHDN or VIN. The RESET output is used to detect whether the level on the input of VDET (TC1301A) or VOUT1 (TC1301B) is above or below a preset threshold. If the voltage detected is below the preset threshold, the RESET output is capable of sinking 1.2 mA (VRESET < 0.2V maximum). Once the voltage being monitored is above the preset threshold, the RESET output pin will transition from a logic-low to a logic-high after a 300 ms delay. The RESET output is a push-pull configuration and will actively pull the RESET output up to VDET when not in RESET. 5.8 GND For the optimal noise and PSRR performance, the GND pin of the TC1301A/B should be tied to a quiet circuit ground. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 5.9 SHDN1/SHDN2 Operation 5.5 Input Capacitor Low input source impedance is necessary for the two LDO outputs to operate properly. When operating from batteries or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 µF to 4.7 µF is recommended for most applications. When using large capacitors on the LDO outputs, larger capacitance is recommended on the LDO input. The capacitor should be placed as close to the input of The TC1301A SHDN2 pin is used to turn VOUT2 ON and OFF. A logic-high level on SHDN2 will enable the VOUT2 output, while a logic-low on the SHDN2 pin will disable the VOUT2 output. For the TC1301A, VOUT1 is not affected by SHDN2 and will be enabled as long as the input voltage is present. The TC1301B SHDN1 and SHDN2 pins are used to turn VOUT1 and VOUT2 ON and OFF. They operate independent of each other. DS21798C-page 14 © 2008 Microchip Technology Inc. TC1301A/B 5.10 TC1301A SHDN2 Timing 5.12 VDET and RESET Operation VOUT1 will rise independent of the level of SHDN2 for the TC1301A. Figure 5-1 is used to define the wake-up time from shutdown (tWK) and the settling time (tS). The wake-up time is dependant upon the frequency of operation. The faster the SHDN pin is pulsed, the shorter the wake-up time will be. The TC1301A/B integrates an independent voltage reset monitor that can be used for low-battery input voltage detection or a microprocessor Power-On Reset (POR) function. The input voltage for the detector is different for the TC1301A than it is for the TC1301B. For the TC1301A, the input voltage to the detector is pin 8 (VDET). For the TC1301B, the input voltage to the detector is internally connected to the output of LDO #1 (VOUT1). The detected voltage is sensed and compared to an internal threshold. When the voltage on the VDET pin is below the threshold voltage, the RESET output pin is low. When the voltage on the VDET pin rises above the voltage threshold, the RESET output will remain low for typically 300 ms (RESET time-out period). After the RESET time-out period, the RESET output voltage will transition from the low output state to the high output state if the detected voltage pin remains above the threshold voltage. The RESET output will be driven low within 180 µs of VDET going below the RESET voltage threshold. The RESET output will remain valid for detected voltages greater than 1.2V overtemperature. VIN ts twk SHDN2 VOUT1 VOUT2 5.13 TC1301A Timing. TC1301A RESET Timing FIGURE 5-1: 5.11 TC1301B SHDN1 / SHDN2 Timing Figure 5-3 shows the RESET timing waveforms for the TC1301A. This diagram is also used to define the RESET active time-out period (tRPU) and the VDET RESET delay time (tRPD). For the TC1301B, the SHDN1 input pin is used to control VOUT1. The SHDN2 input pin is used to control VOUT2, independent of the logic input on SHDN1. VTH VDET RESET Time VOH TRPD VIN ts twk SHDN1 1V VOUT1 RESET VOL FIGURE 5-3: SHDN2 TC1301A RESET Timing. VOUT2 FIGURE 5-2: TC1301B Timing. © 2008 Microchip Technology Inc. DS21798C-page 15 TC1301A/B 5.14 TC1301B RESET Timing 5.15 5.15.1 Device Protection OVERCURRENT LIMIT The timing waveforms for the TC1301B RESET output are shown in Figure 5-4. Note that the RESET threshold input for the TC1301B is VOUT1. The VOUT1 to RESET threshold detector connection is made internal in the case of the TC1301B. VIN VTH VOUT1 RESET Time VOH RESET 1V VOL TRPD In the event of a faulted output load, the maximum current the LDO output will permit to flow is limited internally for each of the TC1301A/B outputs. The peak current limit for VOUT1 is typically 1.1A, while the peak current limit for VOUT2 is typically 0.5A. During shortcircuit operation, the average current is limited to 200 mA for VOUT1 and 140 mA for VOUT2.The VDET and RESET circuit will continue to operate in the event of an overcurrent on either output for the TC1301A. The voltage detect and RESET circuit will continue to operate in the event of an overcurrent on VOUT1 (or VOUT2) for the TC1301B. In the event of an overcurrent on VOUT1, the RESET will detect the absence of VOUT1. 5.15.2 OVERTEMPERATURE PROTECTION FIGURE 5-4: TC1301B RESET Timing. If the internal power dissipation within the TC1301A/B is excessive due to a faulted load or higher-thanspecified line voltage, an internal temperature-sensing element will prevent the junction temperature from exceeding approximately 150°C. If the junction temperature does reach 150°C, both outputs will be disabled until the junction temperature cools to approximately 140°C. The device will resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The VDET and RESET circuit will continue to operate normally during an overtemperature fault condition for both the TC1301A and TC1301B. DS21798C-page 16 © 2008 Microchip Technology Inc. TC1301A/B 6.0 6.1 APPLICATION CIRCUITS/ ISSUES Typical Application EQUATION 6-1: P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) ) Where: PLDO VIN(MAX) VOUT(MIN) = = = LDO Pass device internal power dissipation Maximum input voltage LDO minimum output voltage The TC1301A/B is used for applications that require the integration of two LDO’s and a microcontroller RESET. TC1301A System RESET 2.8V @ 300 mA COUT1 1 µF Ceramic X5R Cbypass 10 nF Ceramic 1 2 3 4 RESET VOUT1 GND VDET 8 BATTERY CIN 1 µF 2.7V to 4.2V 1.8V 6 @ 150 mA VIN 7 VOUT2 Bypass SHDN2 5 COUT2 1 µF Ceramic X5R ON/OFF Control VOUT2 In addition to the LDO pass element power dissipation, there is power dissipation within the TC1301A/B as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation. The VIN pin quiescent current and the VDET pin current are both considered. The VIN current is a result of LDO quiescent current, while the VDET current is a result of the voltage detector current. EQUATION 6-2: ON/OFF Control VOUT1 TC1301B 1 System RESET RESET SHDN1 2.8V @ 300 mA 2 VIN VOUT1 COUT1 3 VOUT2 GND 1 µF Ceramic X5R 4 Bypass SHDN2 8 7 1.8V 6 @ 150 mA 5 BATTERY CIN 1 µF 2.7V to 4.2V P I ( GND ) = V IN ( MAX ) × ( I VIN + I VDET ) Where: PI(GND) VIN(MAX) IVIN = = = Total current in ground pin Maximum input voltage Current flowing in the VIN pin with no output current on either LDO output Current in the VDET pin with RESET loaded COUT2 1 µF Ceramic X5R ON/OFF Control VOUT2 IVDET = FIGURE 6-1: TC1301A/B. 6.1.1 Typical Application Circuit APPLICATION INPUT CONDITIONS Package Type = 3x3 DFN8 Input Voltage Range = 2.7V to 4.2V VIN maximum = 4.2V VIN typical = 3.6V VOUT1 = 300 mA maximum VOUT2 = 150 mA maximum System RESET Load = 10 kΩ The total power dissipated within the TC1301A/B is the sum of the power dissipated in both of the LDO’s and the P(IGND) term. Because of the CMOS construction, the typical IGND for the TC1301A/B is 116 µA. Operating at a maximum of 4.2V results in a power dissipation of 0.5 milliWatts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the TC1301A/B is 125°C. To estimate the internal junction temperature of the TC1301A/B, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RθJA) of the device. The thermal resistance from junction to ambient for the 3x3 DFN8 pin package is estimated at 41°C/W. 6.2 6.2.1 Power Calculations POWER DISSIPATION The internal power dissipation within the TC1301A/B is a function of input voltage, output voltage, output current and quiescent current. The following equation can be used to calculate the internal power dissipation for each LDO. © 2008 Microchip Technology Inc. DS21798C-page 17 TC1301A/B EQUATION 6-3: T J ( MAX ) = P TOTAL × R θ JA + T AMAX Where: TJ(MAX) PTOTAL RθJA TAMAX = = = = Maximum continuous junction temperature Total device power dissipation Thermal resistance from junctionto-ambient Maximum ambient temperature 6.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature, and maximum power dissipation are calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected. 6.3.1 POWER DISSIPATION EXAMPLE The maximum power dissipation capability for a package can be calculated given the junction to ambient thermal resistance and the maximum ambient temperature for the application. The following equation can be used to determine the package maximum internal power dissipation. EQUATION 6-4: ( T J ( MAX ) – T A ( MAX ) ) P D ( MAX ) = --------------------------------------------------R θ JA Where: PD(MAX) TJ(MAX) TAMAX RθJA = = = = Maximum device power dissipation Maximum continuous junction temperature Maximum ambient temperature Thermal resistance from junctionto-ambient EQUATION 6-5: T J ( RISE ) = P D ( MAX ) × R θ JA Where: TJ(RISE) = Rise in device junction temperature over the ambient temperature Maximum device power dissipation Thermal resistance from junctionto-ambient Package Package Type = 3x3 DFN8 Input Voltage VIN = 2.7V to 4.2V LDO Output Voltages and Currents VOUT1 = 2.8V IOUT1 = 300 mA VOUT2 = 1.8V IOUT2 = 150 mA Maximum Ambient Temperature TA(MAX) = 50°C Internal Power Dissipation Internal power dissipation is the sum of the power dissipation for each LDO pass device. PLDO1(MAX) = (VIN(MAX) - VOUT1(MIN)) x IOUT1(MAX) PLDO1 = (4.2V - (0.975 x 2.8V)) x 300 mA PLDO1 = 441.0 milliWatts PLDO2 = (4.2V - (0.975 X 1.8V)) x 150 mA PLDO2 = 366.8 milliWatts PTOTAL = PLDO1 + PLDO2 PTOTAL= 807.8 milliWatts Device Junction Temperature Rise The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. The thermal resistance from junction to ambient (RθJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7, “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages”. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, “A Method To Determine How Much Power a SOT-23 Can Dissipate in Your Application” (DS00792), for more information regarding this subject. TJ(RISE) = PTOTAL x RqJA TJRISE = 807.8 milliWatts x 41.0° C/W TJRISE = 33.1°C PD(MAX) RθJA = = EQUATION 6-6: T J = T J ( RISE ) + T A Where: TJ TJ(RISE) = = Junction Temperature Rise in device junction temperature over the ambient temperature Ambient Temperature TA = DS21798C-page 18 © 2008 Microchip Technology Inc. TC1301A/B Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: TJ = TJRISE + TA(MAX) TJ = 83.1°C Maximum Package Power Dissipation at 50°C Ambient Temperature 3X3DFN8 (41° C/W RθJA) PD(MAX) = (125°C - 50°C) / 41° C/W PD(MAX) = 1.83 Watts MSOP8 (208° C/W RθJA) PD(MAX) = (125°C - 50°C) / 208° C/W PD(MAX) = 0.360 Watts FIGURE 7-3: Example. 3x3 DFN Silk-Screen 8-lead 3X3 DFN physical layout example with bypass capacitor. 7.0 TYPICAL LAYOUT TC1301A FIGURE 7-4: Example. FIGURE 7-1: MSOP8 Silk Screen Layer. 3x3 DFN Top Metal Layer Vias represent the connection to a ground plane that is below the wiring layer. When doing the physical layout for the TC1301A/B, the highest priority is placing the input and output capacitors as close to the device pins as is practical. Figure 7-1 above represents a typical placement of the components when using SMT0805 capacitors. 8.0 ADDITIONAL OUTPUT VOLTAGE AND THRESHOLD VOLTAGE OPTIONS Output Voltage and Threshold Voltage Range 8.1 Table 8-1 describes the range of output voltage options available for the TC1301A/B. VOUT1 and VOUT2 can be factory preset from 1.5V to 3.3V in 100 mV increments. The VDET (TC1301A) or threshold voltage (TC1301B) can be preset from 2.2V to 3.2V in 10 mV increments. TABLE 8-1: CUSTOM OUTPUT VOLTAGE AND THRESHOLD VOLTAGE RANGES VOUT2 1.5V to 3.3V VDET Threshold 2.2V to 3.2V FIGURE 7-2: MSOP8 Wiring Layer. VOUT1 1.5V to 3.3V A wiring example for the TC1301A is shown. The vias represent the connection to a ground plane that is below the wiring layer. For a listing of TC1301A/B standard parts, refer to the Product Identification System on page 25. © 2008 Microchip Technology Inc. DS21798C-page 19 TC1301A/B 9.0 9.1 PACKAGING INFORMATION Package Marking Information Example: — 31A = TC1301A — F = 2.8V VOUT1 — H = 2.6V VOUT2 — A = 2.63V Reset 8-Lead DFN XXXX YYWW NNN Example: AFHA 0435 256 8-Lead MSOP XXXXXX YWWNNN 31AFHA 435256 X1 represents VOUT1 configuration: Code A B C D E F G H I VOUT1 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V Code J K L M N O P Q R VOUT1 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V Code S T U V W X Y Z VOUT1 1.5V 1.65V 2.85V 2.65V 1.85V — — — Xr represents the reset voltage range: Code A B C D E F G H I Voltage 2.63V 2.2V 2.32V 2.5V 2.4V 2.6V — — — Code J K L M N O P Q R Voltage — — — — — — — — — X2 represents VOUT2 configuration: Code A B C D E F G H I VOUT2 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V Code J K L M N O P Q R VOUT2 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Code S T U V W X Y Z VOUT2 1.5V 1.65V 2.85V 2.65V 1.85V — — — For a listing of TC1301A/B standard parts, refer to the Product Identification System section on page 25. Legend: XX...X Y YY WW NNN e3 * Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 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