ZL30107GGG

ZL30107 GbE Line Card Synchronizer Shortform Data Sheet March 2007 A full Data Sheet is available to qualified customers. To register, please send an email to TimingandSync@zarlink.com. Ordering Information ZL30107GGG 64 Pin CABGA Trays ZL30107GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper Features • Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock • Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock -40oC to +85oC • Configurable to accept a 25 MHz input reference • Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover Automatic entry into Asynchronous Holdover mode when all input references fail • Input reference is manually selectable through the serial (SPI) interface • Defaults in Asynchronous Freerun mode • Hitless input reference switching • In Asynchronous Freerun mode, the DPLL generates an output clock with a frequency accuracy equal to frequency accuracy of the external crystal oscillator (XO) or a low cost crystal (XTAL) • Lock indicator pin • Input reference status monitors • Programmable loop bandwidth of 14 Hz, 28 Hz, or 890 Hz • • In Synchronous mode, the DPLL automatically synchronizes to one of a pre-defined set of frequencies including 2 kHz, 8 kHz, 64 kHz, 1.544 MHz, 2.048 MHz, 6.48 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz. X1/CLK X2 Applications • Ethernet Line Cards Supporting Synchronous Transmission LOCK REF0 REF1 DPLL APLL CLK REF2 uP I/F Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved. ZL30107 1 1 2 IC Shortform Data Sheet 3 4 5 6 7 8 IC REF1 IC LF1 AVSS IC AVSS REF0 IC IC REF2 LF2 SCK CS VDD AVDD LF3 SO SI VSS VSS LOCK IC VSS AVCORE IC AVSS IC A B AVCORE AVDD IC C AVSS AVCORE VDD VSS VSS IC CLK VSS VSS VCORE VSS VDD VCORE VSS IC VDD VSS VDD IC IC IC RST VDD IC IC IC IC X1/CLK X2 IC NC VDD D E F G H 1 - A1 corner is identified with a marking 9 mm x 9 mm Ball Pitch 1.0 mm Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. ZL30107 Shortform Data Sheet Pin Description Pin # Name I/O Type B1 A3 B4 REF0 REF1 REF2 Id Reference Inputs (LVCMOS, Schmitt Trigger). These reference inputs are used for synchronizing the PLL. These pins are internally pulled down to Vss. D8 CLK O SONET/SDH/Ethernet Clock Output (LVCMOS). This output clock is configurable as 77.76 MHz, 25 MHz, and 50 MHz. Default is 77.76 MHz. G5 RST I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. E1 LOCK O Lock Indicator (LVCMOS). This is the lock indicator pin for the PLL. This output goes high when the DPLL’s output is frequency is phase locked to the input reference. A5 LF1 A External Analog PLL Loop Filter terminal. B5 LF2 A Analog PLL External Loop Filter Reference. C5 LF3 A Analog PLL External Loop Filter Reference. H4 X1/CLK I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (XO, XTAL). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. H5 X2 O Oscillator Master Clock Output (LVCMOS). This pin is used for connection with an crystal. This pin must be left unconnected when the X1 pin is connected to a clock oscillator. C1 SCK I Clock for Serial Interface (LVCMOS). Serial interface clock. D2 SI I Serial Interface Input (LVCMOS). Serial interface data input pin. D1 SO O Serial Interface Output (LVCMOS). Serial interface data output pin. C2 CS Iu Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This pin is internally pulled up to Vdd. F5 A1 A2 A4 A7 B8 D7 E2 G7 H1 B2 G4 G2 G3 G8 H3 F2 IC Description Internal Connection. Leave unconnected. 3 Zarlink Semiconductor Inc. ZL30107 I/O Type Shortform Data Sheet Pin # Name H6 B3 H2 IC Internal Connection. Connect to ground. H7 NC No Connection. Leave unconnected. C3 C8 E8 F6 F8 G6 H8 VDD P P P P P P P Positive Supply Voltage. +3.3 VDC nominal. E6 F3 VCORE P P Positive Supply Voltage. +1.8 VDC nominal. B7 C4 AVDD P P Positive Analog Supply Voltage. +3.3 VDC nominal. B6 C7 F1 AVCORE P P P Positive Analog Supply Voltage. +1.8 VDC nominal. D3 D4 D5 D6 E3 E4 E5 E7 F4 F7 VSS G G G G G G G G G G Ground. 0 Volts. A6 A8 C6 G1 AVSS G G G G Analog Ground. 0 Volts. IId Iu OAPG- Description Input Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground 4 Zarlink Semiconductor Inc. c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Previous package codes Package Code For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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