MP2932
6-Phase PWM Controller
with 8-Bit DAC Code for VR10 and VR11
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP2932 is a 6-phase, synchronous buck
switching regulator controller for regulating
microprocessor core voltage. MP2932 also uses
dual edge PWM mode to realize fast load
transient with fewer capacitors.
For meeting the requirement of microprocessor
output voltage drops tightly as load current
increases, output current is sensed to realize
voltage droop function. Accurate current
balancing is included in MP2932 to provide
current balance for each channel.
2-, 3-, 4-, 5- or 6-phase Operation
Channel-Current Balancing
Voltage Droop vs. Load Current
Precision Resistor or DCR Current Sensing
Adjustable Switching Frequency
Over Current Protection
Available in a 48-pin QFN6x6 Package
APPLICATIONS
8-bit ID input with selectable VR11 code and
extended VR10 code can set output voltage
dynamically.
Power Modules
Desktop, Server, Core Voltage
POLs (Memory)
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION (6-PHASE BUCK CONVERTER)
5V
Vin
Intelli-phase
Vin
PWM
FB
COMP VCC
DAC
SW
5V
EN
REF
IDROOP
BST
GND
VCC
VDIFF
VSEN
PWM1
RGND
VTT
ISEN1-
EN_VTT
Vin
Intelli-phase
Vin
ISEN1+
VR_ RDY
PWM
ID7
BST
SW
5V
EN
ID6
PWM2
ID5
GND
VCC
ISEN2-
ID4
ISEN2+
ID3
Vin
ID2
MP2932
ID1
ID0
VRSEL
OVP
SD
PWM3
PWM
ISEN3-
EN
GND
ISEN3+
IOUT
ROUT
PWM4
VR_ FAN
Intelli-phase
Vin
Vin
BST
SW
5V
VCC
Intelli-phase
ISEN4-
Vin
ISEN4+
PWM
BST
SW
5V
EN
VR_HOT
PWM5
GND
VCC
ISEN5-
Vin
ISEN5+
PWM6
EN_PWR
GND
Vin
Intelli-phase
Vin
ISEN6-
PWM
ISEN6+
EN
GND
5V
TM
OFS
FS
BST
SW
5V
VCC
SS
Intelli-phase
Vin
PWM
BST
SW
5V
EN
GND
MP2932 Rev.1.02
4/30/2012
VCC
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© 2012 MPS. All Rights Reserved.
1
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
ORDERING INFORMATION
Part Number*
MP2932GQK
Package
QFN (6 x 6mm)
Top Marking
MP2932
Free Air Temperature (TA)
–40C to +85C
* For Tape & Reel, add suffix –Z (e.g. MP2932GQK–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP2932GQK –LF–Z).
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VCC ..................................... 6V
All Other Pins ..................... -0.3V to VCC + 0.3V
Continuous Power Dissipation (TA = +25°C) (2)
............................................................. 3.9W
Junction Temperature ...............................150C
Storage Temperature .............. –65C to +150C
ESD Rating
Human Body Model .................................... 2kV
Machine Model .......................................... 200V
Charged Device Model ............................. 1.5kV
Recommended Operating Conditions
(3)
Thermal Resistance
(4)
θJA
θJC
QFN48 (6mm x 6mm) ............. 32 ...... 3.5 .. C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ (MAX)TA) /θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will
go into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply Voltage VCC ........................... +5V ±5%
Operating Junction Temp. (TJ). -40°C to +125°C
MP2932 Rev.1.02
4/30/2012
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© 2012 MPS. All Rights Reserved.
2
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
ELECTRICAL CHARACTERISTICS
Operating conditions: VCC = 5V, unless otherwise noted.
Parameter
Test conditions
Min
Typ
Max
Units
18
26
mA
14
21
mA
4.5
3.9
0.88
130
0.745
0.88
130
0.745
4.7
4.2
0.910
0.78
V
V
V
mV
V
V
mV
V
-0.5
0.5
℅ID
-0.9
0.9
℅ID
-20
0.4
VCC Supply Current
Nominal Supply
Shutdown Supply
VCC=5VDC; EN_PWR=5VDC;
RT=100kΩ,
ISEN1=ISEN2=ISEN3=ISEN4= ISEN5=
ISEN6=-70μA
VCC=5VDC; EN_PWR=0VDC;
RT=100kΩ
Power-on Reset and Enable
POR Threshold
EN_PWR Threshold
EN_VTT Threshold
VCC Rising
VCC Falling
Rising
Hysteresis
Falling
Rising
Hysteresis
Falling
Reference Voltage and DAC
System Accuracy of MP2932
(ID =1V to 1.6V, TJ=0C to +70C)
System Accuracy of MP2932
(ID =0.5V to 1V, TJ=0C to +70C)
ID Pull-Up
ID Input Low Level
ID Input High Level
VRSEL Input Low Level
VRSEL High Low Level
DAC Source Current
DAC Sink Current
Pin-adjustable Offset
Voltage at OFS Pin
Oscillators
Accuracy of Switching Frequency
setting
Adjustment Range of Switching
Frequency
Soft-Start Ramp Rate
Adjustment Range of Soft-Start
Ramp Rage
MP2932 Rev.1.02
4/30/2012
4.3
3.7
0.850
0.71
0.850
0.71
-60
-40
0.78
0.910
4
7
320
μA
V
V
V
V
mA
μA
380
400
420
mV
1.55
1.600
1.65
V
225
250
275
kHz
1.0
MHz
0.8
0.4
0.8
Offset resistor connected to
ground
Voltage below VCC, offset resistor
connected to VCC
RT=100kΩ
0.08
RS=150kΩ
1.563
0.625
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© 2012 MPS. All Rights Reserved.
mV/μs
6.25
mV/μs
3
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
ELECTRICAL CHARACTERISTICS (continued)
Operating conditions: VCC = 5V, unless otherwise noted.
Parameter
Test conditions
Error Amplifier
Maximum Output Voltage
Output High Voltage @ 2mA
Output Low Voltage @ 2mA
Remote-sense Amplifier
Bandwidth
Output High Current
VSEN-RGND=2.5V
Output High Current
VSEN-RGND=0.6
PWM Output
PWM Output Voltage Low Threshold ILOAD=±500μA
PWM Output Voltage High Threshold ILOAD=±500μA
Current Sense and Over-current Protection
ISEN1=ISEN2=ISEN3=ISEN4=
Sensed Current Tolerance(IDROOP)
ISEN5=ISEN6=50μA
Overcurrent Trip level for Average
Current
Peak Current Limit for Individual
Channel
Maximum Voltage at IDROOP and
IOUT Pins
Thermal Monitoring and Fan Control
TM Input Voltage for VR_FAN TRIP
TM Input Voltage for VR_FAN Reset
TM Input Voltage for VR_HOT Trip
TM Input Voltage for VR_HOT Reset
With externally pull-up resistor
Leakage current of VR_FAN
connected to VCC
VR_RAN Low Voltage
IVR_FAN=4mA
With externally pull-up resistor
Leakage Current of VR_HOT
connected to VCC
VR_HOT Low Voltage
IVR_HOT=4mA
VR Ready and Protection Monitors
With externally pull-up resistor
Leakage Current of VR_RDY
connected to VCC
VR_RDY Low Voltage
IVR_RDY=4mA
Undervoltage Threshold
VDIFF Falling
VR_RDY Reset Voltage
VDIFF Rising
Before Valid ID
Overvoltage Protection Threshold
After valid ID, the voltage above
ID
Overvoltage Protection Reset
Hysteresis
MP2932 Rev.1.02
4/30/2012
Min
Typ
Max
Units
3.8
3.6
4.2
4.6
1.8
V
V
V
100
100
MHz
μA
μA
20
-100
-100
0.5
V
V
4.3
47
50
53
μA
72
85
98
μA
120
μA
1.98
2.01
2.04
V
1.55
1.85
1.3
1.55
1.65
1.95
1.4
1.65
1.75
2.05
1.5
1.75
V
V
V
V
30
μA
0.4
V
30
μA
0.4
V
30
μA
V
℅ID
℅ID
V
Mv
48
58
1.250
50
60
1.275
0.4
52
62
1.300
150
175
200
100
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© 2012 MPS. All Rights Reserved.
mV
4
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
PIN FUNCTIONS
Pin #
Name
1
2
3
4
5
6
7
8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
9
VRSEL
10
OFS
11
IOUT
12
DAC
13
REF
14
15
16
17
18
19
COMP
FB
IDROOP
VDIFF
RGND
VSEN
20
SD
21
22
23
24
25
26
27
28
29
30
31
32
33
VCC
ISEN5ISEN5+
PWM5
PWM2
ISEN2+
ISEN2ISEN4ISEN4+
PWM4
PWM1
ISEN1+
ISEN1-
MP2932 Rev.1.02
4/30/2012
Description
ID inputs from microprocessor. These codes determine output regulation voltage.
Select internal ID code. When it is tied to GND, the extended VR10 is selected. When
it’s floated or tied to high, VR11 code is selected.
Offset between REF and DAC program pin. The OFS pin can be used to program a
DC offset current which will generate a DC offset voltage between the REF and DAC
pins. The polarity of the offset is selected by connecting the resistor to GND or VCC.
For no offset, the OFS pin should be left unconnected.
A resistor needs to be placed between IOUT and GND to ensure the proper operation.
The voltage at IOUT pin will be proportional to the load current.
Internal DAC reference output determined by ID codes
Error amplifier input. A capacitor 0.1uF is used between REF and GND to smooth the
voltage transition during Dynamic ID operations.
Error amplifier output pin. Tie to compensation network
Output voltage feedback pin.
Current proportional to load current is flowed out through this pin
Remote sense amplifier output. VDIFF-GND=VSEN-RGND
Remote sense amplifier input. Remote output GND
Remote sense amplifier input. Remote output.
Shutdown Intelli-phase @ Hiz state. MP2932 cooperates with MPS Intelli-phase and
SD pin is connected to the EN of Intelli-phase.
Power supply. Connect this pin directly to a +5V supply.
Phase 5 current sense amplifier differential inputs.
Phase 5 PWM output.
Phase 2 PWM output.
Phase 2 current sense amplifier differential input.
Phase 4 current sense amplifier differential input.
Phase 4 PWM output.
Phase 1 PWM output.
Phase 1 current sense amplifier differential input.
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© 2012 MPS. All Rights Reserved.
5
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
PIN FUNCTIONS (continued)
Pin #
34
35
36
37
38
39
Name
ISEN3ISEN3+
PWM3
PWM6
ISEN6+
ISEN6-
40
EN_PWR
41
42
EN_VTT
FS
43
SS
44
OVP
45
VR_RDY
46
47
VR_FAN
VR_HOT
48
TM
MP2932 Rev.1.02
4/30/2012
Description
Phase 3 current sense amplifier differential input.
Phase 3 PWM output.
Phase 6 PWM output.
Phase 6 current sense amplifier differential input
Enable pin. It is used to synchronize power-up of the controller and MOSFET driver
ICs.
Enable pin. It is controlled by output of VTT voltage regulator in the mother board.
PWM frequency set pin. A resistor from FS to GND will set the switching frequency.
Soft start oscillator frequency set pin. A resistor from SS to GND will set up the softstart ramp rate.
Overvoltage protection output indication pin. It can be pulled to VCC and is latched
when an overvoltage condition is detected.
Open drain logic output. When soft start completed and output voltage is regulated in
the value determined by ID setting, VR_RDY is logic high.
Open drain logic output. It is open when VR temperature reaches certain value
Open drain logic output. It is open when VR temperature reaches certain value
NTC resistor in this pin is used to monitor inductor temperature. Connect this pin
through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage
at this pin is reverse proportional to the VR temperature.
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6
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VID=1.2V, L=0.3µH, FSW=600kHz, 6-Phase Operation, TA = +25ºC, unless otherwise noted.
Shutdown Supply Current
vs. VCC
18
17
16
15
14
13
3.5
4
4.5
5
5.5
V CC (V)
6
6.5
Switching Frequency
vs. RT
1200
17
FREQUENCY (kHz)
19
SHUTDOWN SUPPLY CURRENT (mA)
NORMAL SUPPLY CURRENT (mA)
Normal Supply Current
vs. VCC
16
15
14
IOUT=0A
1000
800
600
400
200
13
3.5
4
4.5
5
5.5
V CC (V)
6
0
6.5
20 60 100 140 180 220 260 300 340
1.20
1.18
1.16
1.14
1.12
1.10
0 10 20 30 40 50 60 70 80 90
2.0
IOUT=60A
120
110
1.5
100
1.0
90
0.5
80
IOCP (A)
OUTPUT VOLTAGE (V)
1.22
NORMALIZED OUTPUT VOLTAGE (%)
Line Regulation
0.0
-0.5
-1.0
70
60
50
40
-1.5
30
-2.0
5
7
9
11 13 15 17 19 21
20
20
30
40
50
60
70
80
90
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
95
EFFICIENCY (%)
90
85
80
75
70
65
60
55
50
0
20
40
60
80
100
120
OUTPUT CURRENT (A)
MP2932 Rev.1.02
4/30/2012
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7
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VID=1.2V, L=0.3µH, FSW=600kHz, 6-Phase Operation, TA = +25ºC, unless otherwise noted.
MP2932 Rev.1.02
4/30/2012
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© 2012 MPS. All Rights Reserved.
8
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
BLOCK DIAGRAM
FS
OVP VDIFF VR_RDY
S
RGND
X1
OVP R
DRIVE
Q
VCC
CLOCK AND
RAMP GENETATOR
0.875
POWER-ON
RESET ( POR)
EN_ VTT
VSEN
0.875
EN_PWR
SOFT- START
AND
FAULT LOGIC
OVP
PWM
MODULATOR
+175mV
PWM1
PWM
MODULATOR
SS
PWM2
VRSEL
PWM
MODULATOR
ID7
PWM3
ID6
ID5
ID4
ID3
PWM
MODULATOR
DYNAMIC
VID
DVA
PWM4
ID2
PWM
MODULATOR
ID1
ID0
DAC
OFS
PWM5
PWM
MODULATOR
PWM6
OFFSET
REF
CHANNEL
CURRENT
BALANCE
AND PEAK
CURRENT LIMIT
E /A
FB
COMP
CHANNEL
DETECT
ISEN1+
2V
I_TRIP
ISEN1-
OC2
OC1
ISEN2+
ISEN2-
IOUT
I_TOT
1
N
ISEN3+
S
ISEN3CHANNEL
CURRENT
SENSE
IDROOP
THERMAL
MONITOR
ISEN4+
ISEN4ISEN5+
S HUTDOWN
DRIVER MOS @
Hiz STATE
ISEN5ISEN6+
ISEN6-
TM
VR_ FAN VR_HOT
SD
GND
Figure 1—Functional Block Diagram
MP2932 Rev.1.02
4/30/2012
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9
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
OPERATION
Multiphase Power Conversion
The MP2932 is a multiphase VR controller for
Intel VR11 or VR10. It can be programmed for 2-,
3-, 4-, 5- or 6 channel operation for microprocessor core supply power converters with
interleaved switching. The interleaving work of
each phase can help to reduce of ripple current
amplitude in the multiphase circuit and to reduce
input ripple current.
The MP2932 control system is based on DualEdge PWM providing the fastest load response.
Under load transition condition, the MP2932 can
turn on all phase together to improve the load
transient. It can achieve excellent transient
performance and reduce the demand on the
output capacitors.
Number of Phases
The number of operational phases is determined
by internal circuitry that monitors the PWM
outputs. Normally, the MP2932 operates as a 6phase controller. The number of active channels
is determined by the state of PWM3, PWM4,
PWM5, and PWM6. For 2-phase operation,
connect PWM3 to VCC; similarly, PWM4 for 3phase, PWM5 for 4-phase, and PWM6 for 5phase operation. Table 1 shows the phase firing
sequence.
Table 1—Phase firing sequence
Configuration
6-Phase
5-Phase
4-Phase
3-Phase
2-Phase
Phase Sequence
1-2-3-4-5-6
1-2-3-4-5
1-3-4-2
1-2-3
1-2
IL(s)
Vin
GND
L
SW
DCR
VOUT
VL
VC(s)
PWM
PWM(n)
R
COUT
C
MP2932 INTERNAL CIRCUIT
R ISEN(n)
In
CURRENT
SENSE
ISEN-(n)
ISEN+(n)
CT
Equation (2) shows the s-domain equivalent
voltage across the inductor VL.
VL IL s L DCR
(1)
Where FSW is the switching frequency of each
phase.
MP2932 Rev.1.02
4/30/2012
Intelli-Phase
Vin
Figure 2—DCR Sensing Configuration
The resistor RT can be estimated by Equation (1).
2.5 1010
600
FSW
Inductor DCR Sensing
The MP2932 can adopt a lossless current
sensing scheme, commonly referred to as
inductor DCR sensing, as shown in Figure 2.
DCR
I
SEN =IL R
ISEN
Switching Frequency
The clock frequency is set by an external resistor
RT connected from the FS pin to GND.
RT
Current Sensing
MP2932 has cycle by cycle current sense for fast
response. MP2932 adopts inductor DCR sensing,
or resistive sensing techniques. The sense
current, ISEN, is proportional to the inductor
current. The sensed current is used for current
balance, load-line regulation, and overcurrent
protection.
(2)
A simple RC network across the inductor extracts
the DCR voltage, as shown in Figure 2.
The voltage on the capacitor VC, can be shown to
be proportional to the channel current IL, see
Equation (3).
L
1 DCR IL
s
DCR
VC
s RC 1
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(3)
10
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
If the RC network components are selected
such that the RC time constant (=R*C) matches
the inductor time constant (=L/DCR), the
voltage across the capacitor VC is equal to the
voltage drop across the DCR, i.e., proportional
to the channel current.
Therefore, the current out of ISEN+ pin (ISEN), is
proportional to the inductor current and it can
be seen form Equation (4).
DCR
ISEN IL
RISEN
(4)
Resistive Sensing
For accurate current sense, a current-sense
resistor RSENSE in series with each output
inductor can also be adopted (see Figure 3).
This technique reduces overall converter
efficiency due to the additional power loss on
RSENSE.
adjustment to the PWM duty cycle of each
channel.
Output Voltage and Load-Line Regulation
The MP2932 uses an internal differential
remote-sense amplifier as shown in Figure 4.
The microprocessor voltage is sensed between
the VSEN and RGND pins.
The output of the error amplifier (VCOMP) is
compared to sawtooth waveforms to generate
the PWM signals. The typical open-loop gain of
error amplifier is no less than 80dB, and the
typical open-loop bandwidth is no less than
20MHz. The PWM signals control the timing of
the MPS Intelli-phase and regulate the
converter output to the specified reference
voltage.
EXTERNAL CIRCUIT
COMP
RC
Equation (5) shows the relationship between
the channel current to the sensed current ISEN.
RISEN(n)
IDROOP
ERROR AMPLIFIER
VDIFF
VOUT+
VSEN
VOUT-
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
Figure 4—Output Voltage and Load-line
Regulation
ISEN-(n)
ISEN+(n)
CT
R
ISEN =I L SENSE
R ISEN
Figure 3—Sense Resistor in Series with
Inductors
Channel-Current Balance
The sensed current from each active channel is
summed together and divided by the number of
active channels. The resulting average current
(IAVG) provides a measure of the total load
current. Channel current balance is achieved by
comparing the sensed current of each channel
to the average current to make an appropriate
MP2932 Rev.1.02
4/30/2012
VCOMP
IAVG
VDROOP
VOUT
COUT
CURRENT
SENSE
REF
FB
R FB
MP2932 INTERNAL CIRCUIT
In
DAC
R REF
(5)
IL
RSENSE
CC
CREF
R
ISEN IL SENSE
RISEN
L
MP2932 INTERNAL CIRCUIT
The load-line is realized by a resistor RFB
connected between FB pin and the remote
sense output (VDIFF). As shown in Figure 4,
the average current of all active channels (IAVG)
flows from FB through the load-line regulation
resistor RFB. The resulting voltage drop across
RFB can be seen form Equation (6):
VDROOP I AVGRFB
(6)
The output voltage is reduced by the droop
voltage VDROOP, and it is a function a load
current. It’s derived by combining Equation (6)
with the appropriate sensing current expression
defined by the current sense method.
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11
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
I
RX
VOUT VREF VOFS OUT
R FB
N R
ISEN
(7)
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total
output current of the converter, RISEN is the
sense resistor connected to the ISEN+ pin, and
RFB is the feedback resistor, N is the active
channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
Therefore, the loadline is defined as:
R LL
R FB
N
RX
RISEN
(8)
Output Voltage Offset Programming
In Figure 5, OFS pin is used to generate noload offset. A resistor RREF between DAC and
REF is selected, and the product (IOFS x ROFS) is
equal to the desired offset voltage.
FB
V
OFFSET
0.4 R
REF
R
OFS
Enable and Disable
While in shutdown mode, the PWM outputs are
held in a Hi-Z state, and the SD signal is pulled
low to assure the Intelli-phase remain off. The
following input conditions must be met to start
MP2932.
1. VCC must reach the internal power-on reset
(POR) rising threshold.
2. EN_PWR is used to coordinate the power
sequencing between VCC and another
voltage rail. The enable comparator holds
the MP2932 in shutdown until the voltage at
EN_PWR rises above 0.875V.
3. The voltage on EN_VTT must be higher than
0.875V to enable the controller. This pin is
typically connected to the output of VTT VR.
MP2932 INTERNAL CIRCUIT
DYNAMIC
ID D/A
DAC
EXTERNAL CIRCUIT
VCC
RREF
REF
E/A
(10)
POR
CIRCUIT
C REF
ENABLE
COMPARATOR
+12V
10kO
EN_PWR
910O
0.875V
VCC
OR
GND
EN_VTT
R OFS
1.6V
0.4V
MP2932
VCC
OFS
0.875V
GND
Figure 5—Offset Voltage Programming
Connect a resistor ROFS between OFS to VCC
to generate a positive offset. The voltage
across it is regulated to 1.6V. This causes a
proportional current (IOFS) to flow into OFS. The
positive offset is:
V
OFFSET
1.6 R
R
REF
(9)
OFS
Connect a resistor ROFS between OFS to GND
to generate a negative offset. The voltage
across it is regulated to 0.4V, and IOFS flows out
of OFS. The negative offset is:
MP2932 Rev.1.02
4/30/2012
4.
SOFT-START
AND
FAULT LOGIC
Figure 6—Power Sequencing Using
Threshold Sensitive Enable (EN) Function
When all conditions are satisfied, MP2932
begins the soft-start and ramps the output
voltage to 1.1V first. After remaining at 1.1V for
some time, MP2932 reads the ID code at ID
input pins. If the ID code is valid, MP2932 will
regulate the output to the final ID setting. If the
ID code is OFF code, MP2932 will shutdown,
and cycling VCC, EN_PWR or EN_VTT is
needed to restart.
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12
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Soft-Start
MP2932 has 4 periods during soft-start as
shown in Figure 7. After VCC, EN_VTT and
EN_PWR reach their POR/enable thresholds,
the controller will have fixed delay period td1
1.36ms. After the delay period, the VR will
begin first soft-start ramp until the output
voltage reaches 1.1V. Then, the controller will
regulate the VR voltage at 1.1V for another
fixed period td3. At the end of td3 period, MP2932
reads the ID signals. If the ID code is valid,
MP2932 will initiate the second soft-start ramp
until the voltage reaches the ID voltage minus
offset voltage.
1.1V
td2
td3
td4
td5
EN_VTT
VR_RDY
500us/DIV
Figure 7—Soft-Start Waveforms
The soft-start time is the sum of the 4 periods,
as shown in Equation (11):
tSS t d1 t d2 t d3 t d4
(11)
td1 is about 1.36ms. td3 is determined by the
fixed 85µs plus the time to obtain valid ID
voltage. If the ID is valid before the output
reaches the 1.1V, the minimum time to validate
the ID input is 500ns. Therefore the minimum
td3 is about 86µs.
During td2 and td4, MP2932 digitally controls the
DAC voltage change at 6.25mV per step. The
time for each step is determined by the
frequency of the soft-start oscillator which is
defined by the resistor RSS from SS pin to GND.
The second soft-start ramp time td2 and td4 can
be calculated based on Equations (12) and (13):
t
d2
2 1.1 R SS
(us)
3 6.25 25
MP2932 Rev.1.02
4/30/2012
d4
2 V VID 1.1 R SS
(us)
6.25 25
3
(13)
For example, when ID is set to 1.5V and the
RSS is set at 100kΩ, the first soft-start ramp time
td2 will be 469µs and the second soft-start ramp
time td4 will be 171µs.
After the DAC voltage reaches the final ID
setting, VR_RDY will be set to high with the
fixed delay td5, it’s about 85µs.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output.
It is pulled low during shutdown and releases
high after a successful soft-start. VR_RDY will
be pulled low when an under-voltage or overvoltage condition is detected, or the controller is
disabled by a reset from EN_PWR, EN_VTT,
POR, or ID OFF-code.
Under-voltage Detection
The under-voltage threshold is set at 50% of
the ID code. When the output voltage at VSEN
is below the under-voltage threshold, VR_RDY
is pulled low.
VOUT
td1
t
(12)
Over-voltage Protection (OVP)
Regardless of the VR being enabled or not, the
MP2932 OVP circuit will be active after its POR.
The OVP thresholds are different at different
operation conditions. When VR is not enabled
and during the soft-start intervals td1, td2 and td3,
the OVP threshold is 1.275V. Once the
controller detects valid ID input, the OVP trip
point will be changed to DAC + 175mV.
VR_RDY
UV
50%
SOFT-START, FAULT
AND CONTROL LOGIC
DAC
VDIFF
85uA
OC
IAVG
OV
VID + 0.175V
Figure 8—VR_RDY and Protection Circuitry
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13
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
At the beginning of an over-voltage event, all
PWM outputs are commanded low instantly
(>20ns). The Intelli-phase LS-FET is turned on.
When the VDIFF voltage falls below the DAC +
75mV, PWM signals enter a Hi-Z state, and the
SD pin is pulled low to turn off the Intelli-phase.
If the over-voltage condition reoccurs, the
MP2932 will again command the LS-FET to
turn on. The MP2932 will continue to protect the
load in this way as long as the over-voltage
condition occurs.
Once an over-voltage condition is detected,
normal PWM operation ceases until the
MP2932 is reset. Cycling the voltage on
EN_PWR, EN_VTT or VCC below the PORfalling threshold will reset the controller. Cycling
the ID codes will not reset the controller.
Over-current Protection (OCP)
MP2932 has two levels of over-current
protection. Each phase is protected from a
sustained over-current condition by limiting its
peak current, while the combined phase
currents are protected on an instantaneous
basis.
In instantaneous protection mode, the MP2932
adopts the sensed average current IAVG to
detect an over-current condition. The IAVG is
compared with a constant 85µA reference
current, as shown in Figure 8. Once IAVG
exceeds 85µA, a comparator triggers the
converter to shutdown. At the beginning of
over-current shutdown, the controller places all
PWM signals in a Hi-Z state within 20ns to turn
off the Intelli-phase. The system remains in this
state about 12ms. If the controller is still
enabled at the end of this wait period, it will
attempt a soft-start. If the fault remains, the
hiccup mode will continue indefinitely until
either controller is disabled or the fault is
cleared.
MP2932 Rev.1.02
4/30/2012
OUTPUT CURRENT
0A
OUTPUT VOLTAGE
0V
Figure 9—Over-current Behavior in HICCUP
Mode. Fsw = 600kHz
For the individual channel over-current
protection, the MP2932 continuously compares
the sensed current signal of each channel with
the 120µA reference current. If one channel
current exceeds the reference current, MP2932
will pull PWM signal of this channel to low for
the rest of the switching cycle. This PWM signal
can be turned on next cycle if the sensed
channel current is less than the 120µA
reference current. The peak current limit of
individual channel will not trigger the converter
to shutdown.
Thermal Monitoring (VR_HOT/VR_FAN)
There are two thermal signals to indicate the
temperature status of the voltage regulator:
VR_HOT and VR_FAN. Both VR_FAN and
VR_HOT pins are open-drain outputs, and
external pull-up resistors are required. Those
signals are valid only after the controller is
enabled.
The VR_FAN signal indicates that the
temperature of the voltage regulator is high and
more cooling airflow is needed. The VR_HOT
signal can be used to inform the system that the
temperature of the voltage regulator is too high
and the CPU should reduce its power
consumption.
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14
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
VCC
VR_FAN
R TM1
0.33VCC
VR_HOT
TM
R REF
°C
0.28VCC
Figure 10—Block Diagram of Thermal
Monitoring Function
Figure 10 shows the diagram of thermal
monitoring function block. One NTC resistor
should be placed close to the power stage of
the voltage regulator to sense the temperature,
and one pull-up resistor is needed to form the
voltage divider for the TM pin. As the
temperature of the power stage increases, the
resistance of the NTC will reduce, resulting in
the reduced voltage at the TM pin.
There are two comparators with hysteresis to
compare the TM pin voltage to the fixed
thresholds for VR_FAN and VR_HOT signals
respectively. The VR_FAN signal is set to high
when the TM voltage is lower than 33% of VCC
voltage, and is pulled to GND when the TM
voltage increases to above 39% of VCC voltage.
The VR_FAN signal is set to high when the TM
voltage goes below 28% of VCC voltage, and is
pulled to GND when the TM voltage goes back
to above 33% of VCC voltage. Figure 11 shows
the operation of those signals.
TM
Current Sense Output
The MP2932 has 2 current sense output pins
IDROOP and IOUT, they are identical. In typical
application, IDROOP pin is connected to FB pin
for the application where load line is required.
IOUT pin was designed for load current
measurement.
The current from the IDROOP pin is the sensed
average current. In typical application, the
IDROOP pin is connected to the FB pin for the
application where load line is required. Load
current information can be obtained by
measuring the voltage at IOUT pin with a
resistor connecting IOUT pin to the ground.
When load line function is not needed, the
IDROOP pin can be used to obtain the load
current information: with one resistor from the
IDROOP pin to GND, the voltage at the
IDROOP pin will be proportional to the load
current in Equation (14):
R
RX
VIDROOP IDROOP
I
(14)
N
RISEN LOAD
Where VIDROOP is the voltage at the IDROOP pin,
RIDROOP is the resistor between the IDROOP pin
and GND, ILOAD is the total output current of the
converter, RISEN is the sense resistor connected
to the ISEN+ pin, N is the active channel
number, and RX is the resistance of the current
sense element, either the DCR of the inductor
or RSENSE depending on the sensing method.
The resistor from the IDROOP pin to GND
should be chosen to ensure that the voltage at
the IDROOP pin is less than 2V under the
maximum load current.
If the IDROOP pin is not used, tie it to GND.
0.39*VCC
0.33*VCC
0.28*VCC
VR_FAN
VR_HOT
TEMPERATURE
T1
T2
T3
Figure 11—VR_HOT and VR_FAN Signal vs.
TM Voltage
MP2932 Rev.1.02
4/30/2012
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15
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
APPLICATION INFORMATION
Current Sensing Resistor
The resistors connected to the ISEN+ pins
determine the gains in the load-line regulation
loop and the channel-current balance loop as
well as setting the overcurrent trip point. Select
values for these resistors by using Equation
(15):
R
ISEN
I
OCP
X
85 10 6 N
R
(15)
Where RISEN is the sense resistor connected to
the ISEN+ pin, N is the active channel number,
RX is the resistance of the current sense
element, either the DCR of the inductor or
RSENSE depending on the sensing method, and
IOCP is the desired overcurrent trip point.
Typically, IOCP can be chosen to be 1.3x the
maximum load current of the specific
application.
Compensation
There are two distinct methods for achieving
the compensation.
Compensating Load-Line Regulated
Converter
The load-line regulated converter behaves in a
similar manner to a peak-current mode
controller because the two poles at the outputfilter L-C resonant frequency split with the
introduction of current information into the
control loop. The final location of these poles is
determined by the system function, the gain of
the current signal, and the value of the
compensation components, RC and CC.
Treating the system as though it were a
voltage-mode regulator by compensating the LC poles and the ESR zero of the voltage-mode.
C 2 (OPTIONAL )
Load-Line Regulation Resistor
The load-line regulation resistor is labeled RFB
in Figure 4. Its value depends on the desired
load-line requirement of the application.
The desired load-line can be calculated by
using Equation (16):
R
LL
V
DROOP
I
FL
(16)
Where IFL is the full load current of the specific
application, and VRDROOP is the desired voltage
droop under the full load condition.
Based on the desired load-line RLL, the load-line
regulation resistor can be calculated by using
Equation (17):
R
FB
NR
R
ISEN LL
R
X
(17)
Where N is the active channel number, RISEN is
the sense resistor connected to the ISEN+ pin,
and RX is the resistance of the current sense,
either the DCR of the inductor or RSENSE
depending on the sensing method.
MP2932 Rev.1.02
4/30/2012
RC
CC
COMP
FB
R FB
VDROOP
MP2932
IDROOP
VDIFF
Figure 12— Compensation Circuit for
MP2932 with Load-line Regulation
The feedback resistor, RFB, has already been
chosen as outlined in “Load-Line Regulation
Resistor”. Select a target bandwidth for the
compensated system, f0. The target bandwidth
must be large enough to assure adequate
transient performance, but smaller than 1/3 of
the per-channel switching frequency. The
values of the compensation components
depend on the relationships of f0 to the L-C pole
frequency and the ESR zero frequency.
The optional capacitor C2, (22pF to 150pF) is
sometimes needed to bypass noise away from
the PWM comparator (see Figure 12).
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16
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Compensation without Load-Line
Regulation
The non load-line regulated converter is
accurately modeled as a voltage-mode
regulator with two poles at the L-C resonant
frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 13,
provides the necessary compensation.
C2
RC
CC
COMP
FB
MP2932
C1
R1
RFB
IDROOP
VDIFF
Figure 13—Compensation Circuit for
MP2932 without Load-line Regulation
The first step is to choose the desired
bandwidth, f0, of the compensated system.
Choose a frequency high enough to assure
adequate transient performance but not higher
than 1/3 of the switching frequency. The type-III
compensator has an extra high-frequency pole,
fHF. A good general rule is to choose fHF=10f0,
but it can be higher if desired. Choosing fHF to
be lower than 10f0 can cause problems with too
much phase shift below the system bandwidth.
Output Inductor
The output inductors and the output capacitor
bank together to form a low-pass filter
responsible for smoothing the pulsating voltage
at the phase nodes. The output filter also must
provide the transient energy until the regulator
can respond.
In high-speed converters, the output capacitor
bank is usually the most costly (and often the
largest) part of the circuit. The critical load
parameters in choosing the output capacitors
are the maximum size of the load step, ΔI; the
load-current slew rate, di/dt; and the maximum
allowable output voltage deviation under
transient loading, ΔVMAX. Capacitors are
MP2932 Rev.1.02
4/30/2012
characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the
output capacitors supply all of the transient
current. The output voltage will initially deviate
by an amount approximated by the voltage drop
across the ESL. As the load current increases,
the voltage drop across the ESR increases
linearly until the load current reaches its final
value. The capacitors selected must have
sufficiently low ESL and ESR so that the total
output voltage deviation is less than the
allowable maximum. Neglecting the contribution
of inductor current and regulator response, the
output voltage initially deviates by an amount in
Equation (18):
ΔV ESL
di
ESR ΔI
dt
(18)
The filter capacitor must have sufficiently low
ESL and ESR so that ΔV < ΔVMAX.
The ESR of the bulk capacitors also creates the
majority of the output voltage ripple. As the bulk
capacitors sink and source the inductor AC
ripple current, a voltage develops across the
bulk-capacitor ESR. Thus, once the output
capacitors are selected, the maximum
allowable ripple voltage, VP-P(MAX) determines
the lower limit on the inductance.
V - NV
V
OUT OUT
L ESR IN
f V V
s IN P - PMAX
(19)
Since the capacitors are supplying a decreasing
portion of the load current while the regulator
recovers from the transient, the capacitor
voltage becomes slightly depleted. The output
inductors must be capable of assuming the
entire load current before the output voltage
decreases more than ΔVMAX. This places an
upper limit on inductance.
Input Capacitor
The input capacitors are responsible for
sourcing the AC component of the input current
flowing into the upper MOSFETs. Their RMS
current capacity must be sufficient to handle the
AC component of the current drawn by the
upper MOSFETs which is related to duty cycle
and the number of active phases.
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17
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Low capacitance, high-frequency ceramic
capacitors are needed in addition to the bulk
capacitors to suppress leading and falling edge
voltage spikes. Select low ESL ceramic
capacitors and place one as close as possible
to each upper MOSFET drain to minimize board
parasitic
impedances
and
maximize
suppression.
PC Board Layout
For best performance of the MP2932, the
following guidelines should be strictly followed:
Within the allotted implementation area, place
the switching components first. Switching
component placement should take into account
power dissipation. Align the output inductors
and MOSFETs such that space between the
components is minimized while creating the
PHASE plane. If possible, duplicate the same
placement of these components for each phase.
Next, place the input and output capacitors.
Position one high frequency ceramic input
capacitor next to each upper MOSFET drain.
Place the input capacitors as close to the upper
MOSFET drains as dictated by the component
size and dimensions. Locate the output
capacitors between the inductors and the load,
while keeping them in close proximity to the
microprocessor socket.
MP2932 Rev.1.02
4/30/2012
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18
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Table 2—VR10 ID Table (with 6.25mV
Extension)
ID4
ID3
ID2
ID1
400mV 200mV 100mV 50mV
0
1
0
1
Table 2—VR10 ID Table (with 6.25mV
Extension) continued
ID0
ID5
ID6 VOLTAGE
25mV 12.5mV 6.25mV
(V)
0
1
1
ID4
ID3
ID2
ID1
400mV 200mV 100mV 50mV
ID0
ID5
ID6 VOLTAGE
25mV 12.5mV 6.25mV
(V)
1.60000
1
0
1
0
0
0
0
1.35625
0
1
0
0
1
1
1.35000
0
1
0
1
0
1
0
1.59375
1
0
1
0
1
1
0
1
1.58750
1
0
1
0
0
1
0
1.34375
0
1
0
1
0
1
1.33750
0
1
0
1
1
0
0
1.58125
1
0
1
0
1
1
1
1
1.57500
1
0
1
0
1
0
0
1.33125
0
1
0
1
1
1
0
1.56875
1
0
1
0
1
1
1
1.32500
0
1
0
1
1
0
1.31875
0
1
1
0
0
0
1
1.56250
1
0
1
1
0
0
0
0
1.55625
1
0
1
1
0
0
1
1.31250
0
1
1
0
0
0
1.30625
0
1
1
0
0
1
1
1.55000
1
0
1
1
0
0
1
0
1.54375
1
0
1
1
0
1
1
1.30000
0
1
1
0
1
0
1
1.53750
1
0
1
1
0
1
0
1.29375
0
1
1
1
0
1
1.28750
0
1
1
0
1
0
0
1.53125
1
0
1
1
0
1
1
1
1.52500
1
0
1
1
1
0
0
1.28125
0
1
1
1
1
1
1.27500
0
1
1
0
1
1
0
1.51875
1
0
1
1
1
0
0
1
1.51250
1
0
1
1
1
1
0
1.26875
0
1
1
1
0
0
0
1.50625
1
1
0
0
0
0
1
1.26250
1
0
0
0
0
0
1.25625
0
1
1
1
0
1
1
1.50000
1
0
1
1
1
0
1
0
1.49375
1
1
0
0
0
1
1
1.25000
0
1
1
1
1
0
1
1.4875
1
1
0
0
0
1
0
1.24375
1
0
0
1
0
1
1.23750
0
1
1
1
1
0
0
1.48125
1
0
1
1
1
1
1
1
1.47500
1
1
0
0
1
0
0
1.23125
1
0
0
1
1
1
1.22500
0
1
1
1
1
1
0
1.46875
1
1
0
0
0
0
0
1
1.46250
1
1
0
0
1
1
0
1.21875
1
0
0
0
0
0
0
1.45625
1
1
0
1
0
0
1
1.21250
1
0
1
0
0
0
1.20625
1
0
0
0
0
1
1
1.45000
1
1
0
0
0
0
1
0
1.44375
1
1
0
1
0
1
1
1.20000
1
0
1
0
1
0
1.19375
1
0
0
0
1
0
1
1.43750
1
1
0
0
0
1
0
0
1.43125
1
1
0
1
1
0
1
1.18750
1
0
0
0
1
1
1
1.42500
1
1
0
1
1
0
0
1.18125
1
0
1
1
1
1
1.17500
1
0
0
0
1
1
0
1.41875
1
1
0
0
1
0
0
1
1.41250
1
1
0
1
1
1
0
1.16875
1
0
0
1
0
0
0
1.40625
1
1
1
0
0
0
1
1.16250
1
1
0
0
0
0
1.15625
1
0
0
1
0
1
1
1.40000
1
1
0
0
1
0
1
0
1.39375
1
1
1
0
0
1
1
1.15000
1
1
0
0
1
0
1.14375
1
0
0
1
1
0
1
1.38750
1
1
0
0
1
1
0
0
1.38125
1
1
1
0
1
0
1
1.13750
1
0
0
1
1
1
1
1.37500
1
1
1
0
1
0
0
1.13125
1
1
0
1
1
1
1.12500
1
1
0
1
1
0
1.11875
1
0
0
1
1
1
0
1.36875
1
1
0
1
0
0
0
1
1.36250
1
MP2932 Rev.1.02
4/30/2012
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19
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Table 2—VR10 ID Table (with 6.25mV
Extension) continued
ID4
ID3
ID2
ID1
400mV 200mV 100mV 50mV
Table 2—VR10 ID Table (with 6.25mV
Extension) continued
ID0
ID5
ID6 VOLTAGE
25mV 12.5mV 6.25mV
(V)
ID4
ID3
ID2
ID1
400mV 200mV 100mV 50mV
ID0
ID5
ID6 VOLTAGE
25mV 12.5mV 6.25mV
(V)
1
1
1
1
0
0
1
1.11250
0
0
1
1
1
1
0
0.89375
1
1
1
1
0
0
0
1.10625
0
1
0
0
0
0
1
0.88750
1
1
1
1
0
1
1
1.10000
0
1
0
0
0
0
0
0.88125
1
1
1
1
0
1
0
1.09375
0
1
0
0
0
1
1
0.87500
1
1
1
1
1
0
1
OFF
0
1
0
0
0
1
0
0.86875
1
1
1
1
1
0
0
OFF
0
1
0
0
1
0
1
0.86250
1
1
1
1
1
1
1
OFF
0
1
0
0
1
0
0
0.85625
1
1
1
1
1
1
0
OFF
0
1
0
0
1
1
1
0.85000
0
0
0
0
0
0
1
1.08750
0
1
0
0
1
1
0
0.84375
0
0
0
0
0
0
0
1.08125
0
1
0
1
0
0
1
0.83750
0
0
0
0
0
1
1
1.07500
0
1
0
1
0
0
0
0.83125
0
0
0
0
0
1
0
1.06875
0
0
0
0
1
0
1
1.06250
0
0
0
0
1
0
0
1.05625
0
0
0
0
1
1
1
1.05000
0
0
0
0
1
1
0
1.04375
0
0
0
1
0
0
1
1.03750
0
0
0
1
0
0
0
1.03125
0
0
0
1
0
1
1
1.02500
0
0
0
1
0
1
0
1.01875
0
0
0
1
1
0
1
1.01250
0
0
0
1
1
0
0
1.00625
0
0
0
1
1
1
1
1.00000
0
0
0
1
1
1
0
0.99375
0
0
1
0
0
0
1
0.9875
0
0
1
0
0
0
0
0.98125
0
0
1
0
0
1
1
0.97500
0
0
1
0
0
1
0
0.96875
0
0
1
0
1
0
1
0.9625
0
0
1
0
1
0
0
0.95625
0
0
1
0
1
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
1
1
0
Table 3—VR11 ID 8-BIT
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0 VOLTAGE
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0.95000
0
0
0
0
1
1
1
1
1.51875
0
0.94375
0
0
0
1
0
0
0
0
1.51250
0
1
0.93750
0
0
0
1
0
0
0
1
1.50625
0
0
0.93125
0
0
0
1
0
0
1
0
1.50000
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0.92500
0
0
0
1
1
0
1
0
0.91875
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
1
0
1
0.91250
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
0
0.90625
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
1
1
0.90000
MP2932 Rev.1.02
4/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
20
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Table 3—VR11 ID 8-BIT continued
ID7
ID6
ID5
ID4
ID3
ID2
ID1
0
0
0
1
0
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
Table 3—VR11 ID 8-BIT continued
ID7
ID6
ID5
ID4
ID3
ID2
ID1
1.46875
0
0
1
1
1
1
1
1
1.21875
0
1.46250
0
1
0
0
0
0
0
0
1.21250
1
1.45625
0
1
0
0
0
0
0
1
1.20625
1
0
1.45000
0
1
0
0
0
0
1
0
1.20000
0
1
1
1.44375
0
1
0
0
0
0
1
1
1.19375
1
0
0
1.43750
0
1
0
0
0
1
0
0
1.18750
1
1
0
1
1.43125
0
1
0
0
0
1
0
1
1.18125
1
1
1
1
0
1.42500
0
1
0
0
0
1
1
0
1.17500
0
1
1
1
1
1
1.41875
0
1
0
0
0
1
1
1
1.16875
1
0
0
0
0
0
1.41250
0
1
0
0
1
0
0
0
1.16250
0
1
0
0
0
0
1
1.40625
0
1
0
0
1
0
0
1
1.15625
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
1
0
1
0
1.15000
0
0
1
0
0
0
1
1
1.39375
0
1
0
0
1
0
1
1
1.14375
0
0
1
0
0
1
0
0
1.38750
0
1
0
0
1
1
0
0
1.13750
0
0
1
0
0
1
0
1
1.38125
0
1
0
0
1
1
0
1
1.13125
0
0
1
0
0
1
1
0
1.37500
0
1
0
0
1
1
1
0
1.12500
0
0
1
0
0
1
1
1
1.36875
0
1
0
0
1
1
1
1
1.11875
0
0
1
0
1
0
0
0
1.36250
0
1
0
1
0
0
0
0
1.11250
0
0
1
0
1
0
0
1
1.35625
0
1
0
1
0
0
0
1
1.10625
0
0
1
0
1
0
1
0
1.35000
0
1
0
1
0
0
1
0
1.10000
0
0
1
0
1
0
1
1
1.34375
0
1
0
1
0
0
1
1
1.09375
0
0
1
0
1
1
0
0
1.33750
0
1
0
1
0
1
0
0
1.08750
0
0
1
0
1
1
0
1
1.33125
0
1
0
1
0
1
0
1
1.08125
0
0
1
0
1
1
1
0
1.32500
0
1
0
1
0
1
1
0
1.07500
0
0
1
0
1
1
1
1
1.31875
0
1
0
1
0
1
1
1
1.06875
0
0
1
1
0
0
0
0
1.31250
0
1
0
1
1
0
0
0
1.06250
0
0
1
1
0
0
0
1
1.30625
0
1
0
1
1
0
0
1
1.05625
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
0
1.26250
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
0
1.22500
MP2932 Rev.1.02
4/30/2012
ID0 VOLTAGE
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
ID0 VOLTAGE
21
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
Table 3—VR11 ID 8-BIT continued
ID7
ID6
ID5
ID4
ID3
ID2
ID1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
Table 3—VR11 ID 8-BIT continued
ID0 VOLTAGE
ID7
ID6
ID5
ID4
ID3
ID2
ID1
0.97500
1
0
0
0
1
1
1
0
0.72500
1
0.96875
1
0
0
0
1
1
1
1
0.71875
0
0.96250
1
0
0
1
0
0
0
0
0.71250
0
1
0.95625
1
0
0
1
0
0
0
1
0.70625
0
1
0
0.95000
1
0
0
1
0
0
1
0
0.70000
1
0
1
1
0.94375
1
0
0
1
0
0
1
1
0.69375
1
1
0
0
0.93750
1
0
0
1
0
1
0
0
0.68750
0
1
1
0
1
0.93125
1
0
0
1
0
1
0
1
0.68125
1
0
1
1
1
0
0.92500
1
0
0
1
0
1
1
0
0.67500
1
1
0
1
1
1
1
0.91875
1
0
0
1
0
1
1
1
0.66875
1
1
1
0
0
0
0
0.91250
1
0
0
1
1
0
0
0
0.66250
0
1
1
1
0
0
0
1
0.90625
1
0
0
1
1
0
0
1
0.65625
0
1
1
1
0
0
1
0
0.90000
1
0
0
1
1
0
1
0
0.65000
0
1
1
1
0
0
1
1
0.89375
1
0
0
1
1
0
1
1
0.64375
0
1
1
1
0
1
0
0
0.88750
1
0
0
1
1
1
0
0
0.63750
0
1
1
1
0
1
0
1
0.88125
1
0
0
1
1
1
0
1
0.63125
0
1
1
1
0
1
1
0
0.87500
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
0
1
1
1
0.86875
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
1
0
0
0
0.86250
1
0
1
0
0
0
0
0
0.61250
0
1
1
1
1
0
0
1
0.85625
1
0
1
0
0
0
0
1
0.60625
0
1
1
1
1
0
1
0
0.85000
1
0
1
0
0
0
1
0
0.60000
0
1
1
1
1
0
1
1
0.84375
1
0
1
0
0
0
1
1
0.59375
0
1
1
1
1
1
0
0
0.83750
1
0
1
0
0
1
0
0
0.58750
0
1
1
1
1
1
0
1
0.83125
1
0
1
0
0
1
0
1
0.58125
0
1
1
1
1
1
1
0
0.82500
1
0
1
0
0
1
1
0
0.57500
0
1
1
1
1
1
1
1
0.81875
1
0
1
0
0
1
1
1
0.56875
1
0
0
0
0
0
0
0
0.81250
1
0
1
0
1
0
0
0
0.56250
1
0
0
0
0
0
0
1
0.80625
1
0
1
0
1
0
0
1
0.55625
1
0
0
0
0
0
1
0
0.80000
1
0
1
0
1
0
1
0
0.55000
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
1
0
0.77500
1
0
1
0
1
1
1
0
0.52500
1
0
0
0
0
1
1
1
0.76875
1
0
1
0
1
1
1
1
0.51875
1
0
0
0
1
0
0
0
0.76250
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
1
0
0.75000
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
0
1
1
0.74375
1
1
1
1
1
1
1
0
OFF
1
0
0
0
1
1
0
0
0.73750
1
1
1
1
1
1
1
1
OFF
1
0
0
0
1
1
0
1
0.73125
MP2932 Rev.1.02
4/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
ID0 VOLTAGE
22
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
PACKAGE INFORMATION
QFN48 (6 x 6mm)
5.90
6.10
4.50
4.70
37
PIN 1 ID
MARKING
PIN 1 ID
SEE DETAIL A
48
36
1
0.40
BSC
5.90
6.10
PIN 1 ID
INDEX AREA
4.50
4.70
0.15
0.25
12
25
TOP VIEW
13
24
0.35
0.45
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.25 TYP.
0.80
1.00
0.20 REF
0.00
0.05
DETAIL A
SIDE VIEW
5.90
NOTE:
4.60
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-220, VARIATION VJJE-1.
5) DRAWING IS NOT TO SCALE.
0.70
0.20
0.40
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2932 Rev. 1.02
4/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
23
工商网监
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