Preliminary Specification Number : SP-ABZ-093-E
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LoRaWAN Modem Module Data Sheet
MP Part Number: CMWX1ZZABZ-093
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Revision History
Revision
Code
A
Date
Description
Dec 20, 2016
B
Feb 23, 2017
C
D
E
July 3, 2017
Sep 29, 2017
Nov 23, 2017
Initial Draft
Updated pin description according to MuRata LoRa
modem command specification v0.5
Added reference circuit
Updated reference circuit
Updated Electrical Characteristics and reference circuit
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Comments
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TABLE OF CONTENTS
1. Features ······················································································································· 4
2. Part Number ················································································································· 4
3. Block Diagram ··············································································································· 4
4. Dimensions, Marking and Terminal Configurations ···························································· 5
5. Label Information ·········································································································· 8
6. Absolute Maximum Ratings ····························································································· 9
7. Operating Condition ······································································································· 9
8. Electrical Characteristics ································································································ 9
9. Power Sequences ··········································································································· 11
10. Recommend Land Pattern····························································································· 12
11. Reference circuit ·········································································································· 13
12. Tape and Reel packing·································································································· 14
13. Notice ························································································································ 17
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1. Features
Interfaces
Main ICs
Reference Clocks
Supported Frequencies
Module Size
Weight
Package
RoHS
: UART
: STM32L, SX1276
: Integrated 32MHz clock (TCXO with frequency error=±2 ppm)
and 32.768KHz clock (frequency error=±20 ppm)
: 868 MHz, 915 MHz
: 12.5 mm x 11.6 mm x 1.76 mm (Max.)
: 0.48g (Typ.)
: Metal Shield can
: This module is compliant with the RoHS directive
2. Part Number
Ordering Part Number
B-L072Z-LRWAN1
CMWX1ZZABZ-093
Description
Evaluation board (owned by ST)
MP P/N
3. Block Diagram
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4. Dimensions, Marking and Terminal Configurations
Full datasheet with Terminal dimensions is available in my Murata. Check https://my.murata.com
under the “LoRa/Sigfox Module, Type ABZ LoRa Support Site”.
Top View
Bottom View
Side View
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Terminal Configurations
< Top View >
Table 2 Terminal Configurations
Pin NO.
Terminal Name
Type
Connection to
IC terminal
Description
1
PA12/USB_DP
O
STM32L072_PA12
Only power supply for TCXO
2
PA11/USB_DM
I/O
STM32L072_PA11
Unused
3
GND
Ground
-
Ground
4
VDD_USB
Power
-
Power supply for PA12/PA11
5
VDD_MCU
Power
-
Power supply for MCU
6
VDD_RF
Power
-
Power supply for RF IC
7
GND
Ground
-
Ground
8
DBG_SX1276_DIO2
I/O
SX1276_DIO2
Debug pin for SX1276, customer cannot use it
9
DBG_SX1276_DIO3
I/O
SX1276_DIO3
Debug pin for SX1276, customer cannot use it
10
DBG_SX1276_DIO4
I/O
SX1276_DIO4
SX1276 DIO4, customer cannot use it
11
DBG_SX1276_DIO5
I/O
SX1276_DIO5
Debug pin for SX1276, customer cannot use it
12
DBG_SX1276_DIO1
I/O
SX1276_DIO1
Debug pin for SX1276, customer cannot use it
13
DBG_SX1276_DIO0
I/O
SX1276_DIO0
Debug pin for SX1276, customer cannot use it
14
PB15/SPI2_MOSI
I
STM32L072_PB15
Input for factory new. In normal work mode,
this pin should be pulled up. If this pin is pulled
down continuously more than 5 seconds and
then pulled up, the module will be restored to
factory new.
15
PB14/SPI2_MISO
I/O
STM32L072_PB14
Unused
16
PB13/SPI2_SCK
I/O
STM32L072_PB13
Unused
17
PB12/SPI2_NSS
I/O
STM32L072_PB12
Unused
18
PA10/USART1_RX
I/O
STM32L072_PA10
Debug interface.
19
PA9/USART1_TX
I/O
STM32L072_PA9
Debug interface.
20
PA8/MCO
I/O
STM32L072_PA8
Unused
21
PA5/ADC5/DAC2
I/O
STM32L072_PA5
Unused
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22
PA4/ADC4/DAC1
I/O
STM32L072_PA4
Unused
23
PA3/ADC3
I/O
STM32L072_PA3
UART_RX for AT command interface
24
PA2/ADC2
I/O
STM32L072_PA2
UART_TX for AT command interface
25
GND
Ground
-
Ground
26
ANT
A,I/O
-
Transmit / Receive antenna
27
GND
Ground
-
Ground
28
DBG_CRF1
I/O
STM32L072_PA1
Unused
29
DBG_CRF3
I/O
STM32L072_PC1
Unused
30
DBG_CRF2
I/O
STM32L072_PC2
Unused
31
STSAFE_nRST
I
-
Unused
32
VREF+
Power
-
Reference Voltage for ADC and DAC
33
PA0/WKUP1
I/O
STM32L072_PA0
Input for bootloader mode. In normal work
mode, this pin should be pulled up. If this pin is
pulled down during power on, the module will
enter bootloader mode.
34
MCU_nRST
I
STM32L072_ nRST
nRST
35
PB8/I2C1_SCL
I/O
STM32L072_ PB8
Unused
36
PB9/I2C1_SDA
I/O
STM32L072_ PB9
Unused
37
PB2/LPTIM1_OUT
I/O
STM32L072_PB2
Unused
38
PB7/LPTIM1_IN2
I/O
STM32L072_PB7
Unused
39
PB6/LPTIM1_ETR
I/O
STM32L072_ PB6
Unused
40
PB5/LPTIM1_IN1
I/O
STM32L072_ PB5
Unused
41
PA13/SWDIO
I/O
STM32L072_PA13
Unused
42
PA14/SWCLK
I/O
STM32L072_PA14
Unused
43
BOOT0
I
STM32L072_BOOT0
Boot Option
44
GND
Ground
-
Ground
45
PH1-OSC_OUT
I/O
STM32L072_PH1
Unused
46
PH0-OSC_IN
I/O
STM32L072_PH0
Unused
47
TCXO_OUT
O
-
Internal TCXO output
48
VDD _TCXO
Power
-
Power supply for the TCXO
49~57
GND
Ground
-
Ground
Notes: GPIO pins are to be left OPEN if not used.
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5. Label Information
1 pin mark
Product name
FCC ID number
IC ID number
Inspection number
Murata Logo
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6. Absolute Maximum Ratings
Table 3 Maximum ratings
Parameters
Storage Temperature
Input RF Level
VDD_USB
VDD_MCU, VDD_RF, VDD_TCXO
Supply Voltage
VREF+
Min
-40
-0.3
-0.3
-0.3
Typ
25
-
Max
+90
10
3.9
3.9
Unit
degC
dBm
V
V
V
VDD_MCU+0.4
Min
-40
3.0
Typ
25
-
Max
+85
3.6
VDD_MCU_min
VDD_MCU
-
VDD_MCU_max
Unit
degC
V
V
3.6
VDD_MCU
V
V
7. Operating Condition
Table 4 Operating specification
Parameters
Operating Temperature
VDD_USB (USB peripheral used) (1)
VDD_USB(USB peripheral not used) (1)
Supply Voltage
VDD_MCU,VDD_RF,VDD_TCXO
VREF+(2)
2.2(3)
1.8
(1) VDD_USB must respect the following conditions:
- When VDD_MCU is powered on (VDD_MCU < VDD_MCU_min), VDD_USB should be always lower than VDD_MCU.
- When VDD_MCU is powered down (VDD_MCU < VDD_MCU_min), VDD_USB should be always lower than
VDD_MCU.
- In operating mode, VDD_USB could be lower or higher than VDD_MCU.
- If the USB is not used, VDD_USB must be tied to VDD_MCU to be able to use PA11 and PA12 as standard I/Os.
(2) VREF+ is used to ensure a better accuracy on low-voltage inputs and outputs of ADC and DAC. Detailed information is
on the STM32L072*** datasheet and user guider.
(3) When module is on +20dBm operation, the supply of the voltage should be set from 2.4V to 3.6V.
8. Electrical Characteristics
8.1 FSK/OOK Transceiver Specification
Conditions:
Supply voltage VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF =868/915 MHz , 2-level FSK modulation
without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, shared Rx
and TX path matching, unless otherwise specified.
FSK/OOK Receiver Specification
Symbol
RFS_F_HF
Description
LnaBoost is turned on
FSK/OOK Transmitter Specification
Symbol
RF_OP
RF_OPH
ΔRF_
OPH_V
ΔRF_T
IDDT
Description
RF output power in 50 ohms
on RFO pin ( High efficiency
PA)
RF output power in 50 ohms
on PA_BOOST pin( Regulated
PA)
RF output power stability on
PA_BOOST pin versus voltage
supply.
RF output power stability
versus temperature on
PA_BOOST pin.
Supply current in Transmit
mode with impedance
matching
Conditions
FDA = 5 kHz, BR = 4.8 kb/s
Min
Typ
-117.5
Max
Unit
dBm
Conditions
Min
Typ
14
Max
Unit
dBm
Programmable with
steps
Max
Min
-5
dBm
Max
18.5
dBm
Min
2
dBm
VDD = 2.2 V to 3.6 V
+/-1
dB
From T = -40 °C to +85 °C
+/-1.5
dB
Programmable with
1dB steps
RFOP setting = 20 dBm, on
PA_BOOST
RFOP setting = 17 dBm, on
PA_BOOST
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101
mA
mA
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RFOP setting = 14 dBm, on
RFO_HF pin
RFOP setting = 7 dBm, on
RFO_HF pin
46
mA
34
mA
8.2 LoRa Transceiver Specification
Conditions:
The table below gives the electrical specifications for the transceiver operating with LoRaTM modulation. Following
conditions apply unless otherwise specified: Supply voltage = 3.3 V, Temperature = 25° C, FXOSC = 32 MHz, Error
Correction Code (EC) = 4/5, Packet Error Rate (PER)= 1%, CRC on payload enabled, Payload length = 10 bytes.
With matched impedances
LoRa Receiver Specification
Symbol
IDDR_L
RFS_L125_HF
RFS_L250_HF
Description
Current in receiver
RF sensitivity, Long-Range
Mode, LnaBoost for Band1,
using split Rx/Tx path
125 kHz bandwidth
RF sensitivity, Long-Range
Mode, LnaBoost for Band1,
using split Rx/Tx path
250 kHz bandwidth
LoRa Transmitter Specification
Symbol
IDDT_L
IDDT_H_L
Description
Supply current in transmitter
mode
Supply current in transmitter
mode
Conditions
868 band
915 band
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
Min
Conditions
RFOP setting = 14 dBm
RFOP setting = 10 dBm
Using PA_BOOST pin
RFOP setting = 20 dBm
Min
Typ
Max
12.5
14.5
-122.5
-125.5
-128.5
-131.0
-133.5
-135.5
-119.0
-122.0
-125.0
-127.5
-130.0
-133.0
Typ
36
27.5
Max
118
Unit
mA
mA
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Unit
mA
mA
mA
8.3 Low power mode current
Conditions:
Power supply: 3.3V, Temp: Room,
Description
STM32L0 in stop mode with RTC (Real Time Clock)
SX1276 in sleep mode
Min
Typ
1.65
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Max
Unit
uA
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9. Power Sequences
9.1 Power Up Sequence
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10. Recommend Land Pattern
Full datasheet with recommended land pattern is available in my Murata.
https://my.murata.com under the “LoRa/Sigfox Module, Type ABZ LoRa Support Site”.
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11. Reference circuit
C4
1uF
C5
0.1uF
The VDD_USB is must.Because it is
the power supply for PA11 and PA12.
VDD
C3
10uF
1
2
3
4
5
6
7
8
9
10
11
12
54
55
56
57
VDD_TCXO
U1
CMWX1ZZABZ-093
GND
GND
GND
GND
PA12/USB_DP
PA11/USB_DM
GND
VDD_USB
VDD_MCU
VDD_RF
GND
DBG_SX1276_DIO2
DBG_SX1276_DIO3
SX1276_DIO4
DBG_SX1276_DIO5
DBG_SX1276_DIO1
Pin14 is as an input of factory new.
For the detail information, please refer
to the Murata LoRa modem command
specification.
R1
10K
13
14
15
16
17
18
19
20
21
22
23
24
f actory new
VDD
1
2
3
4
5
6
J1
1
2
3
4
5
6
SWD connector
C6
1uF
L1
VDD
C9
2
VDD
R3
10K
VDD
C2 0.1uF
Button2
1
VREF+
2
3
J2
1
4
SMA connector
5
bootload mode selection
C1 0.1uF
Button1
1
Module reset do not need
external pull up resistor.
Because there is an about
45K permanent pull up
resistor inside of module.
C8
module reset
10K
2
Pin 33 is as an input of bootload mode
selection.For the detail information,
please refer to the Murata LoRa modem
command specification.
Notes for VREF+:
1. VREF+ should be connected to GND
or floating if module is powered by
external power supply.
2. VREF+ should be connected to VDD
if module is battery powered and
reports battery level.
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SWCLK
SWDIO
36
35
34
33
32
31
30
29
28
27
26
25
Debug USART_TX
Debug USART_RX
Button3
R2
Host Interf ace USART_TX
Host Interf ace USART_RX
PB9/I2C1_SDA
PB8/I2C1_SCL
MCU_nRST
PA0/WKUP1
VREF+
STSAFE_nRST
DBG_CRF2
DBG_CRF3
DBG_CRF1
GND
ANT
GND
C7
0.1uF
1
2
48
47
46
45
44
43
42
41
40
39
38
37
DBG_SX1276_DIO0
PB15/SPI2_MOSI
VDD_TCXO
PB14/SPI2_MISO
TCXO_OUT
PB13/SPI2_SCK
PH0-OSC_IN
PB12/SPI2_NSS
PH1-OSC_OUT
PA10/USART1_RX
GND
PA9/USART1_TX
BOOT0
PA8/MCO
PA14/SWCLK/LPUART1_TX
PA5/ADC5/DAC2
PA13/SWDIO/LPUART1_RX
PA4/ADC4/DAC1
PB5/LPTIM1_IN1
PA3/ADC3/USART2_RX/LPUART1_RX
PB6/LPTIM1_ETR
PA2/ADC2/USART2_TX/LPUART1_TX
PB7/LPTIM1_IN2
PB2/LPTIM1_OUT
53
52
51
50
49
GND
GND
GND
GND
GND
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12. Tape and Reel packing
2.0±0.1
4.0±0.1 *1
φ1.5+0.1/-0.0
0.30±0.05
11.5±0.1
13±0.1
24.0±0.3
1.75±0.10
12.1 Dimension of Tape (Plastic tape)
φ1.5+0.1/-0
12.1±0.1
24.0±0.1
2±0.15
feeding direction
(unit : mm)
12.2 Dimensions of Reel
Label
120
φ13±0.2
R5
22
φ 80±1
R135
φ
φ330±2
R80
W1
W2
Reel inside width W1: 25.5±1.0
Reel outside width W2: 29.5±1.0
Unit: mm
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12.3 Taping Diagrams
[1] Feeding Hole : As specified in (1)
[2] Hole for chip : As specified in (1)
[3] Cover tape
: 62μMin thickness
[4] Base tape
: As specified in (1)
[3]
[1]
[2]
[3]
[4]
Feeding Hole
Feeding Direction
Chip
12.4 Leader and Tail tape
Tail tape
(No components) Component
s
40 to 200mm
No components
Leader tape
(Cover tape alone)
150mm min.
250mm min.
Feeding direction
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-
-
The tape for chips are wound clockwise, the feeding holes to the right side as the tape is pulled
toward the user.
The cover tape and base tape are not adhered at no components area for 250mm Min.
Tear off strength against pulling of cover tape : 5N Min.
Packaging unit : 1000 pcs/ reel
Material
Base tape : Plastic
Reel
: Plastic
Cover tape, cavity tape and reel are made the anti-static processing.
Peeling of force: 1.3N max. in the direction of peeling as shown below.
1.3 N max.
0.7 N max.
165 to 180 °
Cover tape
Base tape
-
Packaging (HumidiTyproof Packing)
Label
表示ラべル
Desiccant
乾燥剤
Humidity
湿度
Indicator
インジケ－タ
表示ラベル
Label
防湿梱包袋
Anti-humidity
Plastic Bag
Tape and reel must be sealed with the anti-humidiTyplastic bag. The bag contains the desiccant
and the humidity indicator.
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13. Notice
13.1 Storage Conditions
Please use this product within 6month after receipt.
- The product shall be stored without opening the packing under the ambient temperature from 5 to
35 °C and humidity from 20 ~ 70 %RH.
(Packing materials, in particular, may be deformed at the temperature over 40 °C)
- The product left more than 6months after reception, it needs to be confirmed the solderbility before
used.
- The product shall be stored in non corrosive gas (Cl2, NH3, SO2, Nox, etc.).
- Any excess mechanical shock including, but not limited to, sticking the packing materials by sharp
object and dropping the product, shall not be applied in order not to damage the packing materials.
This product is applicable to MSL3 (Based on IPC/JEDEC J-STD-020)
- After the packing opened, the product shall be stored at
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on the content of specification sheet or approval sheet.
Customer acknowledges that engineering samples may deviate from specifications and may contain
defects due to their development status.
We reject any liability or product warranty for engineering samples.
In particular we disclaim liability for damages caused by
・the use of the engineering sample other than for evaluation purposes, particularly the installation or
integration in the product to be sold by you,
・deviation or lapse in function of engineering sample,
・improper use of engineering samples.
We disclaims any liability for consequential and incidental damages.
If you can’t agree the above contents, you should inquire our sales.
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