NCV8406A, NCV8406B
Self-Protected Low Side
Driver with Temperature
and Current Limit
65 V, 7.0 A, Single N−Channel
NCV8406A/B is a three terminal protected Low-Side Smart Discrete
device. The protection features include overcurrent, overtemperature,
ESD and integrated Drain-to-Gate clamping for overvoltage protection.
This device offers protection and is suitable for harsh automotive
environments.
www.onsemi.com
VDSS
(Clamped)
RDS(on) TYP
ID TYP
(Limited)
65 V
210 mW
7.0 A
Features
•
•
•
•
•
•
•
•
•
•
Drain
Short Circuit Protection
Thermal Shutdown with Automatic Restart
Over Voltage Protection
Integrated Clamp for Inductive Switching
ESD Protection
dV/dt Robustness
Analog Drive Capability (Logic Level Input)
These Devices are Faster than the Rest of the NCV Devices
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Overvoltage
Protection
Gate
Input
ESD Protection
Temperature
Limit
Current
Sense
Source
4
Typical Applications
• Switch a Variety of Resistive, Inductive and Capacitive Loads
• Can Replace Electromechanical Relays and Discrete Circuits
• Automotive / Industrial
Current
Limit
1
2
DRAIN
4
3
SOT−223
CASE 318E
STYLE 3
4
1 2
MARKING
DIAGRAM
3
DPAK
CASE 369C
AYW
xxxxxG
G
1
2
3
SOURCE
GATE
DRAIN
YWW
xxxxxG
A
= Assembly Location
Y
= Year
W, WW = Work Week
xxxxx = 8406A or 8406B
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
October, 2018 − Rev. 7
1
Publication Order Number:
NCV8406/D
NCV8406A, NCV8406B
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage Internally Clamped
VDSS
60
Vdc
Gate−to−Source Voltage
VGS
"14
Vdc
Drain Current
Continuous
ID
Total Power Dissipation − SOT−223 Version
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
PD
Total Power Dissipation − DPAK Version
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
PD
Internally Limited
1.25
1.81
1.31
2.31
W
W
Thermal Resistance − SOT−223 Version
Junction−to−Soldering Point
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
RqJS
RqJA
RqJA
7.0
100
69
Thermal Resistance − DPAK Version
Junction−to−Soldering Point
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
RqJS
RqJA
RqJA
1.0
95
54
Single Pulse Inductive Load Switching Energy
(Starting TJ = 25°C, VDD = 50 Vdc, VGS = 5.0 Vdc,
IL = 2.1 Apk, L = 50 mH, RG = 25 W)
EAS
110
mJ
Load Dump Voltage (VGS = 0 and 10 V, RI = 2 W, RL = 7 W, td = 400 ms)
VLD
75
V
Operating Junction Temperature Range
TJ
−40 to 150
°C
Storage Temperature Range
Tstg
−55 to 150
°C
°C/W
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Surface mounted onto minimum pad size (100 sq/mm) FR4 PCB, 1 oz cu.
2. Mounted onto 1″ square pad size (700 sq/mm) FR4 PCB, 1 oz cu.
+
ID
DRAIN
IG
+
VDS
GATE
SOURCE
VGS
−
−
Figure 1. Voltage and Current Convention
www.onsemi.com
2
NCV8406A, NCV8406B
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
65
70
V
−
22
100
−
30
100
1.2
−
1.66
4.0
2.0
−
−
185
210
−
−
210
445
240
520
−
0.9
1.1
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Clamped Breakdown Voltage
(VGS = 0 V, ID = 2 mA)
Zero Gate Voltage Drain Current
(VDS = 52 V, VGS = 0 V)
IDSS
Gate Input Current
(VGS = 5.0 V, VDS = 0 V)
IGSS
mA
mA
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 150 mA)
Threshold Temperature Coefficient
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 V, ID = 2.0 A, TJ @ 25°C)
RDS(on)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 5.0 V, ID = 2.0 A, TJ @ 25°C)
(VGS = 5.0 V, ID = 2.0 A, TJ @ 150°C)
RDS(on)
Source−Drain Forward On Voltage
(IS = 7.0 A, VGS = 0 V)
VSD
V
−mV/°C
mW
mW
V
SWITCHING CHARACTERISTICS (Note 6)
Turn−on Delay Time
RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 10% Vin to 10% ID
td(on)
−
127
−
ns
Turn−on Rise Time
RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 10% ID to 90% ID
trise
−
486
−
ns
Turn−off Delay Time
RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 90% Vin to 90% ID
td(off)
−
1600
−
ns
Turn−off Fall Time
RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 90% ID to 10% ID
tfall
−
692
−
ns
Slew Rate ON
RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 70% to 50% VDD
dVDS/dTon
−
79
−
V/ms
Slew Rate OFF
RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 50% to 70% VDD
dVDS/dToff
−
27
−
V/ms
VDS = 10 V, VGS = 5.0 V, TJ = 25°C (Note 5)
VDS = 10 V, VGS = 5.0 V, TJ = 150°C (Notes 5, 6)
VDS = 10 V, VGS = 10 V, TJ = 25°C (Notes 5)
ILIM
5.0
3.5
6.5
7.0
4.5
8.5
9.5
6.0
10.5
A
VGS = 5.0 V (Note 6)
TLIM(off)
150
180
200
°C
SELF PROTECTION CHARACTERISTICS (Note 4)
Current Limit
Temperature Limit (Turn−off)
Thermal Hysteresis
VGS = 5.0 V
DTLIM(on)
−
10
−
°C
VGS = 10 V (Note 6)
TLIM(off)
150
180
200
°C
Thermal Hysteresis
VGS = 10 V
DTLIM(on)
−
20
−
°C
Input Current during
Thermal Fault
VDS = 0 V, VGS = 5.0 V, TJ = TJ > T(fault) (Note 6)
VDS = 0 V, VGS = 10 V, TJ = TJ > T(fault) (Note 6)
Ig(fault)
−
−
5.9
12.3
−
mA
6000
500
−
−
−
−
Temperature Limit (Turn−off)
ESD ELECTRICAL CHARACTERISTICS
ESD
Electro−Static Discharge Capability
Human Body Model (HBM)
Machine Model (MM)
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Fault conditions are viewed as beyond the normal operating range of the part.
5. Current limit measured at 380 ms after gate pulse.
6. Not subject to production test.
www.onsemi.com
3
NCV8406A, NCV8406B
TYPICAL PERFORMANCE CURVES
1000
TJstart = 25°C
Emax (mJ)
ILmax (A)
10
TJstart = 25°C
100
TJstart = 150°C
TJstart = 150°C
1
10
10
100
L (mH)
Figure 2. Single Pulse Maximum Switch−off
Current vs. Load Inductance
Figure 3. Single−Pulse Maximum Switching
Energy vs. Load Inductance
Emax (mJ)
ILmax (A)
1000
TJstart = 25°C
1
TJstart = 150°C
1
TJstart = 25°C
100
TJstart = 150°C
10
10
1
10
TIME IN CLAMP (ms)
TIME IN CLAMP (ms)
Figure 4. Single Pulse Maximum Inductive
Switch−off Current vs. Time in Clamp
Figure 5. Single−Pulse Maximum Inductive
Switching Energy vs. Time in Clamp
6V
12
7V
8V
9V
12
10 V
−40°C
VDS = 10 V
10
25°C
9
100°C
ID (A)
5V
8
ID (A)
100
L (mH)
10
0.1
10
4V
Ta = 25°C
6
6
150°C
3.3 V
4
3V
2
0
3
VGS = 2.5 V
0
5
10
0
15
0
1
2
3
4
VDS (V)
VGS (V)
Figure 6. On−state Output Characteristics
Figure 7. Transfer Characteristics
www.onsemi.com
4
5
NCV8406A, NCV8406B
TYPICAL PERFORMANCE CURVES
500
600
ID = 2 A
ID = 0.5 A
550
450
150°C
400
350
100°C
300
250
200
150
100
3
4
5
300
100
8
9
50
10
25°C, VGS = 5 V
200
−40°C
7
100°C, VGS = 10 V
250
150
6
100°C, VGS = 5 V
350
25°C
25°C, VGS = 10 V
−40°C, VGS = 5 V
−40°C, VGS = 10 V
0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
VGS (V)
ID (A)
Figure 8. RDS(on) vs. Gate−Source Voltage
Figure 9. RDS(on) vs. Drain Current
3
15
2.5
ID = 2 A
VGS = 10 V
2.0
VGS = 5 V
1.5
ILIM (A)
NORMALIZED RDS(on)
150°C, VGS = 10 V
400
RDS(on) (mW)
RDS(on) (mW)
500
150°C, VGS = 5 V
450
13
−40°C
11
25°C
9
100°C
7
1.0
150°C
5
0.5
−40 −20
0
20
40
60
80
100
120
3
140
VDS = 10 V
4
5
6
7
8
9
T (°C)
VGS (V)
Figure 10. Normalized RDS(on) vs. Temperature
Figure 11. Current Limit vs. Gate−Source
Voltage
15
10
1000
VGS = 10 V
VDS = 10 V
100
13
11
VGS = 5 V
IDSS (mA)
ILIM (A)
10
9
150°C
1
100°C
0.1
0.01 25°C
7
VGS = 0 V
0.001
5
−40 −20
0
20
40
60
80
100
0.0001
120 140
−40°C
10
20
30
40
50
60
TJ (°C)
VDS (V)
Figure 12. Current Limit vs. Junction
Temperature
Figure 13. Drain−to−Source Leakage Current
www.onsemi.com
5
70
NCV8406A, NCV8406B
TYPICAL PERFORMANCE CURVES
1100
ID = 150 mA
VDS = VGS
1.1
VSD (mV)
0.9
25°C
800
0.8
700
0.7
600
0.6
−40 −20
500
100°C
150°C
0
20
40
80
60
100
120 140
VGS = 0 V
1
2
3
4
5
6
8
9
IS (A)
Figure 14. Normalized Threshold Voltage vs.
Temperature
Figure 15. Source−Drain Diode Forward
Characteristics
3400
VDD = 13.8 V
ID = 2 A
RG = 0 W
1200
td(off)
2600
2200
tf
600
tr
TIME (ns)
800
td(off), VGS = 5 V
1800
tf, VGS = 5 V
tr, VGS = 10 V
1000
600
td(on)
200
5
6
7
8
9
td(on), VGS = 5 V
200
−200
10
tr, VGS = 5 V
tf, VGS = 10 V
1400
400
4
10
td(off), VGS = 10 V
3000
1000
3
7
T (°C)
1400
0
−40°C
900
1600
TIME (ns)
1000
1.0
td(on), VGS = 10 V
0
500
1000
1500
2000
VGS (V)
RG (W)
Figure 16. Resistive Load Switching Time vs.
Gate−Source Voltage
Figure 17. Resistive Load Switching Time vs.
Gate Resistance
DRAIN−SOURCE VOLTAGE SLOPE (V/ms)
NORMALIZED VGS(th) (V)
1.2
35
30
25
dVDS/dt(off), VGS = 5 V
20
dVDS/dt(off), VGS = 10 V
15
10
5
0
500
1000
1500
2000
RG (W)
Figure 18. Drain−Source Voltage Slope during
Turn On and Turn Off vs. Gate Resistance
www.onsemi.com
6
NCV8406A, NCV8406B
TYPICAL PERFORMANCE CURVES
110
110
100
100
90
PCB Cu thickness, 1.0 oz
RqJA (°C/W)
RqJA (°C/W)
90
80
70
PCB Cu thickness, 2.0 oz
60
80
70
PCB Cu thickness, 1.0 oz
60
50
50
40
40
100
200
300
400
500
600
PCB Cu thickness, 2.0 oz
100
200
300
400
500
COPPER HEAT SPREADER AREA (mm2)
COPPER HEAT SPREADER AREA (mm2)
Figure 19. RqJA vs. Copper Area − SOT−223
Figure 20. RqJA vs. Copper Area − DPAK
600
1000
R(t) (°C/W)
100 50% Duty Cycle
20%
10%
10
5%
2%
1
0.1
1%
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10
100
1000
PULSE TIME (sec)
Figure 21. Transient Thermal Resistance − SOT−223 Version
100
50% Duty Cycle
R(t) (°C/W)
10
20%
10%
5%
2%
1 1%
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 22. Transient Thermal Resistance − DPAK Version
www.onsemi.com
7
NCV8406A, NCV8406B
TEST CIRCUITS AND WAVEFORMS
RL
VIN
+
D
RG
VDD
G DUT
−
S
IDS
Figure 23. Resistive Load Switching Test Circuit
90%
VIN
10%
td(ON)
tr
td(OFF)
tf
90%
10%
IDS
Figure 24. Resistive Load Switching Waveforms
www.onsemi.com
8
NCV8406A, NCV8406B
TEST CIRCUITS AND WAVEFORMS
L
VDS
VIN
D
RG
+
VDD
G DUT
−
S
tp
IDS
Figure 25. Inductive Load Switching Test Circuit
5V
VIN
0V
Tav
Tp
V(BR)DSS
Ipk
VDD
VDS
VDS(on)
IDS
0
Figure 26. Inductive Load Switching Waveforms
www.onsemi.com
9
NCV8406A, NCV8406B
ORDERING INFORMATION
Package
Shipping†
NCV8406ASTT1G
SOT−223
(Pb−Free)
1000 / Tape & Reel
NCV8406ASTT3G
SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV8406ADTRKG
DPAK
(Pb−Free)
2500 / Tape & Reel
NCV8406BDTRKG
DPAK
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
C
A
b3
B
c2
4
L3
Z
D
1
2
H
DETAIL A
3
L4
NOTE 7
c
SIDE VIEW
b2
e
b
0.005 (0.13)
TOP VIEW
BOTTOM VIEW
C
M
Z
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
BOTTOM VIEW
A1
L1
DETAIL A
Z
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
2.58
0.102
1.60
0.063
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
6.17
0.243
SCALE 3:1
AYWW
XXX
XXXXXG
XXXXXX
A
L
Y
WW
G
3.00
0.118
5.80
0.228
XXXXXXG
ALYWW
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
http://onsemi.com
DPAK SINGLE GAUGE SURFACE
1 MOUNT
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
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Case Outline Number:
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DOCUMENT NUMBER:
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REVISION
DATE
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RELEASED FOR PRODUCTION. REQ. BY L. GAN
24 SEP 2001
A
ADDED STYLE 8. REQ. BY S. ALLEN.
06 AUG 2008
B
ADDED STYLE 9. REQ. BY D. WARNER.
16 JAN 2009
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ADDED STYLE 10. REQ. BY S. ALLEN.
09 JUN 2009
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RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE.
29 JUN 2010
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ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAMBALIZA.
06 FEB 2014
F
ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA.
21 JUL 2015
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