NTD3055L170T4G

NTD3055L170, NVD3055L170 Power MOSFET 9.0 A, 60 V, Logic Level, N−Channel DPAK/IPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features • NVD Prefix for Automotive and Other Applications Requiring • 9.0 AMPERES, 60 VOLTS RDS(on) = 170 mW D Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These are Pb−Free Devices N−Channel G Typical Applications • • • • www.onsemi.com Power Supplies Converters Power Motor Controls Bridge Circuits S 4 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating 1 1 2 Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc VGS VGS ±15 ±20 ID ID 9.0 3.0 27 Apk 1 − Gate 28.5 0.19 2.1 1.5 W W/°C W W 2 − Drain −55 to 175 °C 30 mJ Gate−to−Source Voltage − Continuous − Non−repetitive (tpv10 ms) Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH, IL(pk) = 7.75 A, VDS = 60 Vdc) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Vdc Adc IDM PD TJ, Tstg EAS 5.2 71.4 100 TL 260 DPAK CASE 369C (Surface Mounted) STYLE 2 °C 2 3 IPAK CASE 369D (Straight Lead) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 3 − Source 1 − Gate 2 − Drain °C/W RqJC RqJA RqJA 3 3 − Source A Y WW 3170L G AYWW 31 70LG AYWW 31 70LG 4 Drain 4 Drain = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION 1. When surface mounted to an FR4 board using 0.5 sq in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2014 May, 2017 − Rev. 7 1 Publication Order Number: NTD3055L170/D NTD3055L170, NVD3055L170 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Min Typ Max Unit 60 − − 53.6 − − − − − − 1.0 10 − − ±100 1.0 − 1.7 4.2 2.0 − − 153 170 − − 1.8 1.3 2.1 − gFS − 7.3 − mhos pF OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 5.0 Vdc, ID = 4.5 Adc) RDS(on) Static Drain−to−Source On−Voltage (Note 3) (VGS = 5.0 Vdc, ID = 9.0 Adc) (VGS = 5.0 Vdc, ID = 4.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 6.0 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance Ciss − 195 275 Coss − 70 100 Crss − 29 42 td(on) − 9.7 20 tr − 69 150 td(off) − 10 20 tf − 38 80 QT − 4.7 10 Q1 − 1.4 − Q2 − 2.9 − VSD − − 0.98 0.85 1.25 − Vdc trr − 29.8 − ns ta − 17.6 − tb − 12.2 − QRR − 0.031 − SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 9.0 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 3) Fall Time Gate Charge (VDS = 48 Vdc, ID = 9.0 Adc, VGS = 5.0 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 9.0 Adc, VGS = 0 Vdc) (Note 3) (IS = 9.0 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 9.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NTD3055L170, NVD3055L170 16 20 VDS ≥ 10 V 16 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V 5V 8V 6V 12 4V 8 3.5 V 4 3V 12 8 4 TJ = 25°C TJ = −55°C TJ = 100°C 1 3 2 4 5 6 7 8 TJ = 100°C 0.2 TJ = 25°C 0.15 TJ = −55°C 0.1 0.05 2 4 4.5 5 5.5 Figure 2. Transfer Characteristics 0.25 2.2 3.5 3 Figure 1. On−Region Characteristics 0.3 4 2.5 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 0 1.5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 0 1 0.35 6 8 10 12 14 16 18 6 0.35 VGS = 15 V 0.3 0.25 TJ = 100°C 0.2 TJ = 25°C 0.15 0.1 TJ = −55°C 0.05 0 4 12 8 16 20 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 24 1000 VGS = 0 V ID = 4.5 A VGS = 5 V 1.8 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 1.6 1.4 1.2 1 TJ = 150°C 100 TJ = 125°C 10 TJ = 100°C 0.8 0.6 −50 −25 1 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage www.onsemi.com 3 60 NTD3055L170, NVD3055L170 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 700 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 600 500 Ciss 400 300 Crss Ciss 200 Coss 100 Crss 0 10 5 5 0 VGS 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation www.onsemi.com 4 1000 6 QT 5 Q2 Q1 4 t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTD3055L170, NVD3055L170 3 VGS 2 100 tr tf td(off) 10 td(on) 1 VDS = 30 V ID = 9 A VGS = 5 V ID = 9 A TJ = 25°C 0 1 0 1 2 3 4 QG, TOTAL GATE CHARGE (nC) 5 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 10 8 VGS = 0 V TJ = 25°C 6 4 2 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.96 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For www.onsemi.com 5 NTD3055L170, NVD3055L170 I D, DRAIN CURRENT (AMPS) 100 VGS = 15 V SINGLE PULSE TC = 25°C 10 10 ms 100 ms 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 ms dc 0.1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 32 ID = 7.75 A 24 16 8 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 10 D = 0.5 0.2 1 0.1 P(pk) 0.05 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 001 0.00001 0.0001 0.001 0.01 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform www.onsemi.com 6 1 10 NTD3055L170, NVD3055L170 ORDERING INFORMATION Package Shipping† NTD3055L170G DPAK (Pb−Free) 75 Units / Rail NTD3055L170−1G IPAK (Pb−Free) 75 Units / Rail NTD3055L170T4G DPAK (Pb−Free) 2500 / Tape & Reel NVD3055L170T4G* DPAK (Pb−Free) 2500 / Tape & Reel NVD3055L170T4G−VF01* DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable www.onsemi.com 7 NTD3055L170, NVD3055L170 PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. A E C A b3 B c2 4 L3 Z D 1 2 H DETAIL A 3 L4 NOTE 7 c SIDE VIEW b2 e b TOP VIEW 0.005 (0.13) M C Z H L2 GAUGE PLANE C L L1 DETAIL A DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z BOTTOM VIEW Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ROTATED 905 CW SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 8 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD3055L170, NVD3055L170 PACKAGE DIMENSIONS IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− 3 PL 0.13 (0.005) M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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