SCA61T-FA1H1G-6

SCA61T Series Data Sheet THE SCA61T INCLINOMETER SERIES The SCA61T Series is a 3D-MEMS-based single axis inclinometer family that provides instrumentation grade performance for leveling applications. Low temperature dependency, high resolution and low noise together with robust sensing element design make the SCA61T ideal choice for leveling instruments. The Murata inclinometers are insensitive to vibration, due to their over damped sensing elements and can withstand mechanical shocks of 20000 g. Features          Measuring ranges ±30° SCA61T-FAHH1G and ± 90° SCA61T-FA1H1G 0.0025° resolution (10 Hz BW, analog output) Sensing element controlled over damped frequency response (-3dB 18Hz) Robust design, high shock durability (20000g) Excellent stability over temperature and time Single +5 V supply Ratiometric analog voltage outputs Digital SPI inclination and temperature output Comprehensive failure detection features o True self test by deflecting the sensing elements’ proof mass by electrostatic force. o Continuous sensing element interconnection failure check. o Continuous memory parity check.  RoHS compliant  Compatible with Pb-free reflow solder process Applications    Platform leveling and stabilization Leveling instruments Acceleration and motion measurement 8 VDD Sensing element Signal conditioning and filtering 7 OUT A/D conversion 6 ST Self test 1 EEPROM calibration memory Temperature Sensor 1 SCK SPI interface 2 MISO 3 MOSI 5 CSB 4 GND Figure 1. Murata Electronics Oy www.muratamems.fi Functional block diagram Subject to changes Doc. nr. 8261900 1/17 Rev.A2 SCA61T Series TABLE OF CONTENTS The SCA61T Inclinometer Series .............................................................................................1 Features............................................................................................................................................. 1 Applications ...................................................................................................................................... 1 Table of Contents......................................................................................................................2 1 Electrical Specifications .....................................................................................................3 1.1 Absolute Maximum Ratings ................................................................................................... 3 1.2 Performance Characteristics.................................................................................................. 3 1.3 Electrical Characteristics ....................................................................................................... 4 1.4 SPI Interface DC Characteristics............................................................................................ 4 1.5 SPI Interface AC Characteristics............................................................................................ 4 1.6 SPI Interface Timing Specifications ....................................................................................... 5 1.7 Electrical Connection.............................................................................................................. 6 1.8 Typical Performance Characteristics .................................................................................... 6 1.9 Additional External Compensation ........................................................................................ 7 2 Functional Description .......................................................................................................9 2.1 Measuring Directions .............................................................................................................. 9 2.2 Voltage to Angle Conversion ................................................................................................. 9 2.3 Ratiometric Output................................................................................................................ 10 2.4 SPI Serial Interface................................................................................................................ 10 2.5 Digital Output to Angle Conversion ..................................................................................... 12 2.6 Self Test and Failure Detection Modes ................................................................................ 13 2.7 Temperature Measurement .................................................................................................. 14 3 Application Information ....................................................................................................15 3.1 Recommended Circuit Diagrams and Printed Circuit Board Layouts ............................... 15 3.2 Recommended Printed Circuit Board Footprint ................................................................. 16 4 Mechanical Specifications and Reflow Soldering ..........................................................16 4.1 Mechanical Specifications (Reference only) ....................................................................... 16 4.2 Reflow Soldering ................................................................................................................... 17 Murata Electronics Oy www.muratamems.fi Subject to changes Doc. nr. 8261900 2/17 Rev.A2 SCA61T Series 1 Electrical Specifications The SCA61T product family comprises two versions, the SCA61T-FAHH1G and the SCA61TFA1H1G, that differ in measurement range. The product version specific performance specifications are listed in the following table below. All other specifications are common to both versions. Vdd=5.00V and ambient temperature unless otherwise specified. 1.1 Absolute Maximum Ratings Supply voltage (VDD) Voltage at input / output pins Storage temperature Operating temperature Mechanical shock 1.2 -0.3 V to +5.5V -0.3V to (VDD + 0.3V) -55°C to +125°C -40°C to +125°C Drop from 1 meter on a concrete surface (20000g). Powered or non-powered Performance Characteristics Parameter Condition Measuring range Nominal Frequency response Offset (Output at 0g) Offset calibration error Offset Digital Output Sensitivity –3dB LP Ratiometric output (1 between 0…1° Sensitivity calibration error Sensitivity Digital Output Offset temperature dependency Sensitivity temperature dependency Typical non-linearity Digital output resolution (2 -25…85°C (typical) -40…125°C (max) -25...85°C (typical) -40…125°C (max) Measuring range (2 Output noise density between 0…1° From DC...100Hz Analog output resolution Ratiometric error Cross-axis sensitivity Bandwidth 10 Hz Vdd = 4.75...5.25V Max. Note 1. Note 2. Note 3. Murata Electronics Oy www.muratamems.fi (3 SCA61TFAHH1G ±30 ±0.5 8-28 Vdd/2 ±0.11 1024 4 70 ±0.5 SCA61TFA1H1G ±90 ±1.0 8-28 Vdd/2 ±0.23 1024 2 35 ±0.5 Units 1638 ±0.008 ±0.86 ±0.014 -2.5...+1 ±0.11 11 0.035 0.0008 819 ±0.008 ±0.86 ±0.014 -2.5...+1 ±0.57 11 0.07 0.0008 LSB / g °/°C ° %/°C % ° Bits ° / LSB  / Hz 0.0025 ±1 4 0.0025 ±1 4 ° % % ° g Hz V ° LSB V/g mV/° % The frequency response is determined by the sensing element’s internal gas damping. The angle output has SIN curve relationship to voltage output refer to paragraph 2.2 Resolution = Noise density * √(bandwidth) Subject to changes Doc. nr. 8261900 3/17 Rev.A2 SCA61T Series 1.3 Electrical Characteristics Parameter Supply voltage Vdd Current consumption Operating temperature Analog resistive output load Analog capacitive output load Start-up delay 1.4 Min. Typ Max. Units 4.75 5.0 2.5 5.25 4 V mA +125 °C Vdd = 5 V; No load -40 Vout to Vdd or GND 10 kOhm Vout to Vdd or GND 20 nF Reset and parity check 10 ms SPI Interface DC Characteristics Parameter 1.5 Condition Conditions Symbol Min Typ Max 1.4.1.1.1 Input terminal CSB Pull up current VIN = 0 V Input high voltage Input low voltage Hysteresis Input capacitance IPU VIH VIL VHYST CIN 13 4 -0.3 22 35 Vdd+0.3 1 A V V V pF 1.4.1.1.2 Input terminal MOSI, SCK Pull down current VIN = 5 V Input high voltage Input low voltage Hysteresis IPD VIH VIL VHYST 9 4 -0.3 29 Vdd+0.3 1 0.23*Vdd A V V V Input capacitance CIN 2 pF 1.4.1.1.3 Output terminal MISO Output high voltage I > -1mA VOH Output low voltage Tristate leakage VOL ILEAK I < 1 mA 0 < VMISO < Vdd 0.23*Vdd 2 17 Vdd0.5 Unit V 5 0.5 100 V pA SPI Interface AC Characteristics Parameter Condition Output load SPI clock frequency Internal A/D conversion time Data transfer time @500kHz Murata Electronics Oy www.muratamems.fi @500kHz Subject to changes Doc. nr. 8261900 Min. Typ. 150 38 Max. Units 1 500 nF kHz s s 4/17 Rev.A2 SCA61T Series 1.6 SPI Interface Timing Specifications Parameter Terminal CSB, SCK Time from CSB (10%) to SCK (90%) Time from SCK (10%) to CSB (90%) Terminal SCK SCK low time Conditions Symbol Min. TLS1 120 ns TLS2 120 ns TCL 1 s TCH 1 s TSET 30 ns THOL 30 ns Load capacitance at MISO < 15 pF Load capacitance at MISO < 15 pF TVAL1 10 100 ns TLZ 10 100 ns Load capacitance at MISO < 15 pF TVAL2 100 ns Load capacitance at MISO < 2 nF Load capacitance at MISO < 2 nF SCK high time Terminal MOSI, SCK Time from changing MOSI (10%, 90%) to SCK (90%). Data setup time Time from SCK (90%) to changing MOSI (10%,90%). Data hold time Terminal MISO, CSB Time from CSB (10%) to stable MISO (10%, 90%). Time from CSB (90%) to high impedance state of MISO. Terminal MISO, SCK Time from SCK (10%) to stable MISO (10%, 90%). Typ. Max. Unit Terminal CSB Time between SPI cycles, CSB at high level (90%) When using SPI commands RDAX, RDAY, RWTR: Time between SPI cycles, CSB at high level (90%) TLS1 TCH TLH 15 s TLH 150 s TCL TLS2 TLH CSB SCK THOL MOSI MSB in TVAL1 MISO Figure 2. Murata Electronics Oy www.muratamems.fi TSET DATA in LSB in TVAL2 MSB out TLZ DATA out LSB out Timing diagram for SPI communication Subject to changes Doc. nr. 8261900 5/17 Rev.A2 SCA61T Series 1.7 Electrical Connection If the SPI interface is not used SCK (pin1), MISO (pin3), MOSI (pin4) and CSB (pin7) must be left floating. Self-test can be activated applying logic “1” (positive supply voltage level) to ST pin (pin 6). If ST feature is not used pin 6 must be left floating or connected to GND. Inclination signal is provided from pin OUT. 1 SCK 8 VDD 2 MISO 7 OUT 3 MOSI 6 ST 4 GND Figure 3. No. 1 2 3 4 5 6 7 8 1.8 5 CSB SCA61T electrical connection Node SCK MISO MOSI GND CSB ST Out VDD I/O Input Output Input Supply Input Input Output Supply Description Serial clock Master in slave out; data output Master out slave in; data input Ground Chip select (active low) Self test input Output Positive supply voltage (+5V DC) Typical Performance Characteristics Typical offset and sensitivity temperature dependencies of SCA61T are presented in following diagrams. These results represent the typical performance of SCA61T components. The mean value and 3 sigma limits (mean ± 3 standard deviation) and specification limits are presented in following diagrams. The 3 sigma limits represents 99.73% of the SCA61T population. Temperature dependency of SCA61T offset 1.0 specification limit 0.8 Offset error [degrees] 0.6 0.4 0.2 average 0.0 +3 sigma -0.2 -3 sigma -0.4 -0.6 -0.8 -1.0 -40 specification limit -20 0 20 40 60 80 100 120 Temp [°C] Figure 4. Murata Electronics Oy www.muratamems.fi Typical temperature dependency of the SCA61T offset Subject to changes Doc. nr. 8261900 6/17 Rev.A2 SCA61T Series Temperature dependency of SCA61T sensitivity specification limit 1.0 sensitivity error [%] 0.5 0.0 -0.5 average +3 sigma -1.0 -3 sigma -1.5 -2.0 -2.5 -40 -20 0 20 40 60 80 100 120 specification limit Temp [°C] Figure 5. 1.9 Typical temperature dependency of SCA61T sensitivity Additional External Compensation To achieve the best possible accuracy, the temperature measurement information and typical temperature dependency curves can be used for SCA61T offset and sensitivity temperature rd dependency compensation. The equation for the fitted 3 order polynome curve for offset compensation is: Offcorr  0.0000005 * T 3  0.0000857 * T 2  0.0032 * T  0.0514 Where: Offcorr: T rd 3 order polynome fitted to average offset temperature dependency curve temperature in °C (Refer to paragraph 2.7 Temperature Measurement) The calculated compensation curve can be used to compensate for the temperature dependency of the SCA61T offset by using the following equation: OFFSETcomp  Offset  Offcorr Where: OFFSETcomp temperature compensated offset in degrees Offset Nominal offset in degrees nd The equation for the fitted 2 order polynome curve for sensitivity compensation is: Scorr  0.00011*T 2  0.0019 *T  0.0362 Where: Scorr: T nd 2 order polynome fitted to average sensitivity temperature dependency curve temperature in °C The calculated compensation curve can be used to compensate the temperature dependency of the SCA61T sensitivity by using the following equation: SENScomp  SENS * (1  Scorr / 100) Where: SENScomp Murata Electronics Oy www.muratamems.fi temperature compensated sensitivity Subject to changes Doc. nr. 8261900 7/17 Rev.A2 SCA61T Series SENS Nominal sensitivity (4V/g SCA61T-FAHH1G, 2V/g SCA61T-FA1H1G) The typical offset and sensitivity temperature dependency after external compensation is shown in the following diagrams. Temperature dependency of externally compensated SCA61T offset 1.0 0.8 Offset error [degrees] 0.6 0.4 0.2 average 0.0 +3 sigma -0.2 -3 sigma -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 80 100 120 Temp [°C] Figure 6. The temperature dependency of externally compensated SCA61T offset Temperature dependency of externally compensated SCA61T sensitivity 1.0 0.8 sensitivity error [%] 0.6 0.4 0.2 0.0 average +3 sigma -0.2 -3 sigma -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 80 100 120 Temp [°C] Figure 7. Murata Electronics Oy www.muratamems.fi The temperature dependency of externally compensated SCA61T sensitivity Subject to changes Doc. nr. 8261900 8/17 Rev.A2 SCA61T Series 2 2.1 Functional Description Measuring Directions X-axis VOUT > Figure 8. 2.2 VOUT =2.5V > VOUT The measuring direction of the SCA61T Voltage to Angle Conversion Analog output can be transferred to angle using the following equation for conversion:  Vout  Offset    Sensitivit y    arcsin  where: Offset = output of the device at 0° inclination position, Sensitivity is the sensitivity of the device and VDout is the output of SCA61T. The nominal offset is 2.5 V and the sensitivity is 4 V/g with SCA61T-FAHH1G and 2 V/g with SCA61T-FA1H1G. Angles close to 0° inclination can be estimated quite accurately with straight line conversion but for best possible accuracy arcsine conversion is recommended to be used. The following table shows the angle measurement error if straight line conversion is used. Straight line conversion equation:  Vout  Offset Sensitivit y Where: Sensitivity = 70mV/° with SCA61T-FAHH1G or Sensitivity= 35mV/° with SCA61T-FA1H1G Tilt angle [°] 0 1 2 3 4 5 10 15 30 Murata Electronics Oy www.muratamems.fi Straight line conversion error [°] 0 0.0027 0.0058 0.0094 0.0140 0.0198 0.0787 0.2185 1.668 Subject to changes Doc. nr. 8261900 9/17 Rev.A2 SCA61T Series 2.3 Ratiometric Output Ratiometric output means that zero offset point and sensitivity of the sensor are proportional to the supply voltage. If the SCA61T supply voltage is fluctuating, the SCA61T output will also vary. When the same reference voltage for both the SCA61T sensor and the measuring part (A/D-converter) is used, the error caused by reference voltage variation is automatically compensated for. 2.4 SPI Serial Interface A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave devices. The master is defined as a micro controller providing the SPI clock and the slave as any integrated circuit receiving the SPI clock from the master. The ASIC in Murata Technologies’ products always operates as a slave device in master-slave operation mode. The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a low active Slave Select or Chip Select wire (CSB). Data is transmitted with a 3-wire interface consisting of wires for serial data input (MOSI), serial data output (MISO) and serial clock (SCK). MASTER MICROCONTROLLER SLAVE DATA OUT (MOSI) SI DATA IN (MISO) SO SERIAL CLOCK (SCK) SCK SS0 CS SS1 SI SS2 SO SS3 SCK CS SI SO SCK CS SI SO SCK CS Figure 9. Typical SPI connection The SPI interface in Murata products is designed to support any micro controller that uses an SPI bus. Communication can be carried out by a software or hardware based SPI. Please note that in the case of a hardware based SPI, the received acceleration data is 11 bits. The data transfer uses the following 4-wire interface: MOSI Murata Electronics Oy www.muratamems.fi master out slave in Subject to changes Doc. nr. 8261900 µP → SCA61T 10/17 Rev.A2 SCA61T Series MISO SCK CSB SCA61T → µP µP → SCA61T µP → SCA61T master in slave out serial clock chip select (low active) Each transmission starts with a falling edge of CSB and ends with the rising edge. During transmission, commands and data are controlled by SCK and CSB according to the following rules:           commands and data are shifted; MSB first, LSB last each output data/status bits are shifted out on the falling edge of SCK (MISO line) each bit is sampled on the rising edge of SCK (MOSI line) after the device is selected with the falling edge of CSB, an 8-bit command is received. The command defines the operations to be performed the rising edge of CSB ends all data transfer and resets internal counter and command register if an invalid command is received, no data is shifted into the chip and the MISO remains in high impedance state until the falling edge of CSB. This reinitializes the serial communication. data transfer to MOSI continues immediately after receiving the command in all cases where data is to be written to SCA61T’s internal registers data transfer out from MISO starts with the falling edge of SCK immediately after the last bit of the SPI command is sampled in on the rising edge of SCK maximum SPI clock frequency is 500kHz maximum data transfer speed for RDAX is 5300 samples per sec / channel The SPI command can be either an individual command or a combination of command and data. In the case of combined command and data, the input data follows uninterruptedly the SPI command and the output data is shifted out parallel with the input data. The SPI interface uses an 8-bit instruction (or command) register. The list of commands is given in Table below. Command name MEAS RWTR STX STY RDAX RDAY Command format 00000000 00001000 00001110 00001111 00010000 00010001 Description: Measure mode (normal operation mode after power on) Read temperature data register Activate Self test for X-channel Activate Self test for Y-channel Read X-channel acceleration Read Y-channel acceleration Measure mode (MEAS) is standard operation mode after power-up. During normal operation, the MEAS command is the exit command from Self test. Read temperature data register (RWTR) reads temperature data register during normal operation without effecting the operation. Temperature data register is updated every 150 µs. The load operation is disabled whenever the CSB signal is low, hence CSB must stay high at least 150 µs prior the RWTR command in order to guarantee correct data. The data transfer is presented in Figure below. The data is transferred MSB first. In normal operation, it does not matter what data is written into temperature data register during the RWTR command and hence writing all zeros is recommended. Murata Electronics Oy www.muratamems.fi Subject to changes Doc. nr. 8261900 11/17 Rev.A2 SCA61T Series Figure 10. Command and 8 bit temperature data transmission over the SPI Self test for X-channel (STX) activates the self test function for the X-channel (Channel 1). The Internal charge pump is activated and a high voltage is applied to the X-channel acceleration sensor element electrode. This causes the electrostatic force that deflects the beam of the sensing element and simulates the acceleration to the positive direction. The self-test is de-activated by giving the MEAS command. Read X-channel acceleration (RDAX) accesses the AD converted X-channel acceleration signal stored in acceleration data register X. During normal operation, acceleration data registers are reloaded every 150 µs. The load operation is disabled whenever the CSB signal is low, hence CSB must stay high at least 150 µs prior the RDAX command in order to guarantee correct data. Data output is an 11-bit digital word that is fed out MSB first and LSB last. Figure 11. 2.5 Command and 11 bit acceleration data transmission over the SPI Digital Output to Angle Conversion The acceleration measurement results in RDAX data register are in 11 bit digital word format. The data range is from 0 to 2048. The nominal content of RDAX data register in zero angle position is: Binary: 100 0000 0000 Decimal: 1024 The transfer function from differential digital output to angle can be presented as Murata Electronics Oy www.muratamems.fi Subject to changes Doc. nr. 8261900 12/17 Rev.A2 SCA61T Series  Dout LSB   Dout@ 0 LSB      Sens LSB/g     arcsin  where; Dout Dout@0°  Sens digital output (RDAX) digital offset value, nominal value = 1024 angle sensitivity of the device. (SCA61T-FAHH1G: 1638, SCA61T-FA1H1G: 819) As an example following table contains data register values and calculated differential digital output values with -5, -1 0, 1 and 5 degree tilt angles. 2.6 Angle [°] -5 Acceleration [mg] -87.16 -1 -17.45 0 0 1 17.45 5 87.16 RDAX (SCA61TFAHH1G) dec: 881 bin: 011 0111 0001 dec: 995 bin: 011 1110 0011 dec: 1024 bin: 100 0000 0000 dec: 1053 bin: 100 0001 1101 dec: 1167 bin: 100 1000 1111 RDAX (SCA61TFA1H1G) dec: 953 bin: 011 1011 1001 dec: 1010 bin: 011 1111 0010 dec: 1024 bin: 100 0000 0000 dec: 1038 bin: 100 0000 1110 dec: 1095 bin: 100 0100 0111 Self Test and Failure Detection Modes To ensure reliable measurement results the SCA61T has continuous interconnection failure and calibration memory validity detection. A detected failure forces the output signal close to power supply ground or VDD level, outside the normal output range. The normal output ranges are: analog 0.25-4.75 V (@Vdd=5V) and SPI 102...1945 counts. The calibration memory validity is verified by continuously running parity check for the control register memory content. In the case where a parity error is detected the control register is automatically re-loaded from the EEPROM. If a new parity error is detected after re-loading data both analog output voltage is forced to go close to ground level (