UPD98402AGM-KED

DATA SHEET MOS INTEGRATED CIRCUIT µPD98402A LOCAL ATM SONET FRAMER The µPD98402A is one of the ATM-LAN LSIs and incorporates the TC sublayer function in the SONET/SDHbased physical layer of the ATM protocol. The main functions of the µPD98402A include a transmit function for mapping ATM cells received from the ATM layer onto the payload block of the SONET STS-3c/SDH STM-1 frame and sending them to PMD (Physical Media Dependent) in the physical layer, and a receive function for separating the overhead block and ATM cells from the data string received from the PMD sublayer and sending the ATM cells to the ATM layer. Futhermore, the µPD98402A is compliant with the ATM Forum UNI Recommendations. FEATURES • Provision of TC sublayer function of ATM protocol physical layer • Support of SONET STS-3c frame/SDH STM-1 frame format • Provision of stop mode for cell scramble/descramble and frame scramble/descramble • Disposal/transitory selection of unassigned cells is possible. • Compliant with UTOPIA interface • Incorporation of internal loopback function at PMD and ATM layer turns • PMD interface 155.52 Mbps serial interface 19.44 MHz parallel interface • Provided with registers for writing/reading overhead information SOH (section overhead): C1 (1st to 3rd) bytes, F1 byte LOH (line overhead): K2 byte POH (pass overhead): F2 byte, C2 byte • CMOS process • +5 V single power supply The information in this document is subject to change without notice. Document No. S10835EJ1V0DS00 (1st edition) Date Published December 1995 P Printed in Japan © 1995 µPD98402A • Incorporation of OAM (Operation And Maintenance) function Transmitting side Transmission of various alarms • Transmission by generation of sources Line RDI (FERF), Path RDI (FERF) Line FEBE, Path FEBE • Transmission by command instruction Line AIS, Path AIS Line FEBE, Path FEBE Receiving side • Detection of alarms and error signals LOS (Loss Of Signal) OOF (Out Of Frame) LOF (Loss Of Frame) LOP (Loss Of Pointer) LOC (Loss Of Cell delineation) Line RDI (FERF), Path RDI (FERF) Line AIS, Path AIS • Detection and display of quality deterioration sources B1 error, B2 error, B3 error, Line FEBE, Path FEBE • Incorporation of counter for counting number of performance monitoring errors B1 byte error counter B2 byte error counter B3 byte error counter Line FEBE error counter Path FEBE error counter 2 µPD98402A ORDERING INFORMATION Part Number Package µPD98402AGM-KED160-pin plastic QFP (FINE PITCH) (24 × 24 mm) APPLICATION EXAMPLES The followings are examples of the terminal equipment and the ATM Hub application using the µPD98402A. NIC APPLICATION DATA I/F (UTOPIA) CLOCK RECOVERY CHIP Rx PMD TO HUB Tx PMD CONTROL MEMORY PD98401A m SAR CHIP PD98402A m PHY CHIP CNT I/F 155.52MHz HOST BUS I/F SYNTHESIZER HOST BUS HUB APPLICATION (NIC SIDE) DATA I/F SWITCH SYSTEM (UTOPIA) CNT I/F PD98402A m PHY CHIP CLOCK RECOVERY CHIP Rx PMD TO NIC Tx PMD 155.52MHz SYNTHESIZER CONTROLLER CONTROLLER BUS 3 BLOCK DIAGRAM 4 RxFP OOF RCL PSEL TDOC, TDOT TCOC, TCOT TFKC, TFKT Serialfi Parallel Cell Descrambler Descrambler Idle Cell Drop Rx Timing Generator Cell Delineation HEC Verification HEC Correction Loop Back Rx FIFO 4 Cell RDIC, RDIT SONET Framing A1, A2 RCIC, RCIT RDO0—RDO7 RENBL EMPTY RSOC RCLK TDI0—TDI7 TENBL FULL TSOC TCLK Loop Back TPD0-TPD7 PMD Interface TPC ATM Layer Interface RPD0-RPD7 Parallel fiSerial + Scrambler + RPC Cell Scrambler HEC Generator Tx FIFO 4 Cell Idle Cell Insert TFC Tx Overhead Registers C1(#1~#3) Tx Overhead Controller Rx Overhead Controller F1 K2 C2 F2 D0—D7 A0—A5 R/W ACK BIP Generator (Tx) BIP Generator (Rx) Tx Timing Generator OAM Sequencer Rx Overhead Registers C1(#1~#3) F1 K2 Mode Register Performance Registers INT Cause Registers C2 F2 CE PHINT OE Management Interface TDO TJI TCK TMS TRST Test Block RESET VDD GND TCL TAL RAL LOS µPD98402A TxFP TFSS µPD98402A FUNCTIONAL PIN GROUPS Control RESET TFSS RxFP TxFP RCL RDIC RDIT RCIC RCIT TDOC TDOT PMD Interface TCOC TCOT TFKC TFKT 8 GND TCL VDD RDO0-RDO7 RCLK RSOC RENBL EMPTY TDI0-TDI7 TCLK TSOC TENBL FULL 8 8 ATM Layer Interface TPD0-TPD7 TPC TFC D0-D7 A0-A5 R/W CE ACK 8 6 Management Interface 8 RPD0-RPD7 RPC PSEL RAL PHINT OE OAM Interface TAL LOS JTAG boundary scanNote pin Note This function can be supported at the customer’s request. TRST TDO TMS TCK OOF TJI 5 µPD98402A PIN CONFIGURATION 160-pin plastic QFP (FINE PITCH) (24 × 24 mm) (Top View) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VDD TCK TDO TJI TMS TRST RAL TAL LOS OOF IC IC IC IC IC IC IC IC IC VDD GND IC IC IC IC IC IC IC TFSS RxFP TxFP TCL VDD GND TPD0 TPD1 TPD2 TPD3 TPD4 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD A5 A4 A3 A2 A1 A0 GND D7 D6 D5 D4 D3 GND D2 D1 D0 RESET CG GND VDD IC IC IC IC IC GND IC IC IC IC IC IC IC IC RCL IC IC IC VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Remarks 1. IC : Internally Connected. Leave open. 2. CG : Connect to GND. 6 GND GND TPD5 TPD6 TPD7 TPC GND TFC TFKT TFKC GND VDD TCOT TCOC VDD GND VDD TDOT TDOC VDD GND RCIT RCIC GND RDIT RDIC RPC GND RPD7 RPD6 RPD5 GND RPD4 RPD3 RPD2 RPD1 RPD0 PSEL GND GND GND GND RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 VDD GND RCLK GND RENBL RSOC EMPTY FULL TSOC TEMBL GND TCLK GND VDD TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0 GND PHINT CE OE ACK R/W GND GND µ PD98402AGM-KED µPD98402A A0-A5 ACK CE D0–D7 EMPTY FULL GND LOS OE OOF PHINT PSEL RAL RCIC RCIT RCL RCLK RDIC RDIT : Address Bus : Read/write Cycle Receive Acknowledge : Chip Enable : Data Bus : Output Buffer Empty : Buffer Full : Ground : Loss of Signal : Output Enable : Out of Frame : Physical Interrupt : PMD I/F Select : Receive Alarm : Receive Clock Input Complement : Receive Clock Input True : Internal Receive System Clock : Receive Data Transferring Clock from the ATM Layer Device : Receive Data Input Complement : Receive Data Input True RDO0-RDO7 : Receive Data Output RENBL : Receive Data Enable RESET RPC : System Reset : Receive Parallel Data Clock RPD0-RPD7 : Receive Parallel Data RSOC : Receive Start Address of ATM Cell R/W RxFP TAL TCK TCL TCLK TCOC TCOT TDI0-TDI7 TDO TDOC TDOT TENBL TFC TFKC TFKT TFSS TJI : Read/write Control : Receive Frame Pulse : Transmit Alarm : Test Clock : Internal Transmit System Clock : Transmit Data Transferring Clock from the ATM Layer Device : Transmit Clock Output Complement : Transmit Clock Output True : Transmit Data Input from the ATM Layer : Test Data Output : Transmit Data Output Complement : Transmit Data Output True : Transmit Data Enable : Transmit Reference Clock : Transmit Reference Clock Complement : Transmit Reference Clock True : Transmit Frame Set Signal : Test JTAG Data Input TPC : Transmit Parallel Data Clock TPD0-TPD7 : Transmit Parallel Data TMS TRST TSOC TxFP VDD : Test Mode Select : Test Reset : Transmit Start Address of ATM Cell : Transmit Frame Pulse : Supply Voltage 7 µPD98402A 1. PIN FUNCTIONS • PMD Interface Symbol RDIC RDIT RCIC RCIT TDOC TDOT TCOC Pin No. 66 65 63 62 59 58 54 I/O I I I I O O O I/O Level Pseudo ECL Complement (–) Pseudo ECL True (+) Pseudo ECL Complement (–) Pseudo ECL True (+) Pseudo ECL Complement (–) Pseudo ECL True (+) Pseudo ECL Complement (–) Pseudo ECL True (+) Pseudo ECL Complement (–) Pseudo ECL True (+) TTL Function These pins are used to input receive serial data when serial interface mode is used (PSEL pin input = low level). Ground them when Parallel interface mode is used. These pins are used to input the receive system clock when serial interface mode is used (PSEL pin input = low level). Clocks are input in synchronization with receive data. Ground them when parallel interface mode is used. These pins are used to output transmit serial data when serial interface mode is used (PSEL pin input = low level). They are open-drain pins. Terminate them with VDD –2 V via a 50 Ω resistor. To be undefined after reset. These pins are used to output transmit clocks when serial interface mode is used (PSEL pin input = low level). Transmit clocks to be input to the TFKC/TFKT pins are output passing through internal gates. They are open-drain pins. Terminate them with VDD –2 via a 50 Ω resistor. To be undefined after reset. These pins are used to input transmit system clocks when serial interface mode is used (PSEL pin input = low level). Transmit data output from the TDOC/TDOT pins is output in synchronization with clocks that are input to these pins. Ground them when parallel interface mode is used. TCOT 53 O TFKC 50 I TFKT 49 I RPD0-RPD7 77-73, 71-69 I These pins are used to input receive parallel data when parallel interface mode is used (PSEL pin input = high level). Leave them open when serial interface mode is used. This pin is used to input the receive system clock when parallel interface mode is used (PSEL pin input = high level). Input clocks synchronous with the receive data. Leave it open when serial interface mode is used. These pins are used to output transmit parallel data when parallel interface mode is used (PSEL pin input = high level). Leave them open when serial interface mode is used. This pin is used to output transmit clocks when parallel interface mode is used (PSEL pin input = high level). Transmit clocks to be input to the TFC pin are output passing through internal gates. Leave it open when serial interface mode is used. This pins is used to input transmit system clocks when parallel interface mode is used (PSEL pin input = high level). Transmit data output from pins TPD0 to TPD7 are output in synchronization with the clocks input to this pin. Leave it open when serial interface mode is used. This pin is used to select the mode for PMD interface serial/ parallel interface. Low level: Serial interface mode High level: Parallel interface mode RPC 67 I TTL TPD0-TPD7 35-39, 43-45 O CMOS TPC 46 O CMOS TFC 48 I TTL PSEL 78 I CMOS 8 µPD98402A • Power supply Symbol VDD Pin No. 1, 20, 33, 40, 52, 55, 57, 60, 81, 100, 120, 137, 150 21, 34, 41, 42, 47, 51, 56, 61, 64, 68, 72, 79, 80, 94, 101, 107, 113, 121, 122, 128, 138, 140, 147, 149, 159, 160 I/O – Supply voltage, 5 V ± 5 % Function GND – Ground • ATM Layer Interface Symbol RDO0-RDO7 Pin No. 151-158 I/O O I/O Level CMOS Function Connected to 8-bit data bus to output the receive data to the ATM Layer device. Output is synchronized with the RCLK rising up. To be undefined after reset. Input pin of the receive data transferring clock from the ATM Layer device. Receive cell start address signal. To the ATM Layer device, this signal indicates the start address byte of the receive ATM cell. To be undefined after reset. Receive enable signal. Input pin of the signal indicating that the ATM layer device can receive data. Output buffer empty signal. This signal indicates that there is no data to be transferred to the receive FIFO of the µPD98402A. To be inactive after reset. 8-bit data bus to input the transmit data from the ATM Layer device. Reading a data on the bus is synchronized with the TCLK rising-up. Input pin of the transmit data transferring clock from the ATM layer device. Transmit cell start address signal. Input pin of the signal indicating the start byte of the transmit ATM cell input from the ATM Layer device to the µPD98402A. Transmit enable signal. This signal indicates that the ATM Layer device is transmitting the valid data to the TDI0-TDI7. Input buffer full signal. When 4 bytes remain as the acceptable bytes of transmit FIFO at last, this signal changes to active. To be inactive after reset. RCLK RSOC 148 145 I O TTL CMOS RENBL EMPTY 146 144 I O TTL CMOS TDI0-TDI7 129-136 I TTL TCLK TSOC 139 142 I I TTL TTL TENBL FULL 141 143 I O TTL CMOS 9 µPD98402A • Management Interface Symbol D0-D7 A0-A5 R/W Pin No. 104-106 108-112 114-119 123 I/O I/O I I I/O Level CMOS TTL TTL Function 8-bit data bus for data transfer between the control processor and the internal register of the µPD98402A. Address bus. Used for setting the internal register address of the µPD98402A. Read/write control signal. Low level: Write cycle High level: Read cycle Chip enable signal. At low level, internal register access is to be enable. Read/write cycle receive acknowledge or ready signal. After reset, this signal indicates inactive level. Signal which indicates the interrupt cause occurrence to the processor. After reset, this signal indicates inactive level. Output enable. When this signal is set to low level, the µPD98402A outputs data to the control bus. Even if the CE signal is inactive, when this signal is at low level, the µPD98402A drives the control bus. CE ACK PHINT 126 124 127 I O O TTL CMOS CMOS OE 125 I TTL • OAM Interface Symbol LOS Pin No. 9 I/O O I/O Level CMOS Function Loss of signal detection. Output high level when receive serial data input is "0" for 50 µs continuously or optical input stop signal (RAL) is input. When 2 consecutive frames of valid synchronous pattern is detected, or when input of the optical input stop signal is released, low level is output. To be inactive after reset. Out of frame detection. When 4 consecutive frames of wrong synchronous pattern are detected, high level is output. When 2 consecutive frames of normal synchronous pattern are detected, low level is output. To be inactive after reset. Receive alarm. Inputs receiver-side optical input stop signal by the optical module. Low level: Normal High level: Optical input stopped. Transmit alarm. Inputs transmit-side optical output stop signal output by the optical module. Low level: Normal High level: Optical output stopped. OOF 10 O CMOS RAL 7 I TTL TAL 8 I TTL 10 µPD98402A • Control Symbol TFSS Pin No. 29 I/O I I/O Level TTL Function This is the transmit frame setting signal input pin. It allows synchronization timing of transmit frame output to be set. The µPD98402A samples this input signal by the internal transmit system clock (TCL). Initial output of the transmit frame is restarted 9 clocks into TCL clock cycle after a high level is latched at TCL rise. This is the system reset signal input pin. It initializes the µPD98402A. It is necessary to input a reset signal with a pulse width of 2 cycles or more of the clock that has the longest cycle among the following clocks input to the µPD98402A. ATM layer : TCLK, RCLK clock cycles PMD layer : 1/8 cycle of TFKT/TFKC, RCIC/RCIT clocks, TFC, RPC clock cycles Immediately after a reset, no read/write is possible to registers during 5 clocks of the TCL clock (19.44 MHz). This pin is used to output an internal transmit system clock. The µPD98402A outputs as the internal transmit system clock, the TFKT/TFKC input clock (155.52 MHz) scaled by 8 in serial interface mode, and the TFC input clock (19.44 MHz) in parallel interface mode. This pin is used to output an internal receive system clock. The µPD98402A outputs as the internal receive system clock, the RCIC/RCIT input clock (155.52 MHz) scaled by 8 in serial interface mode, and the RFC input clock (19.44 MHz) in parallel interface mode. This is a frame pulse signal on the transmitting side. It outputs pulses synchronous with the transmit frame start. To be inactive after reset. This is a frame pulse signal on the receiving side. It outputs pulses synchronous with the receive frame start. To be inactive after reset. RESET 103 I TTL TCL 32 O CMOS RCL 85 O CMOS TxFP 31 O CMOS RxFP 30 O CMOS • JTAG boundary scan pins (This function can be supported at the customer’s request.) Symbol TJI TDO TCK TMS TRST Pin No. 4 3 2 5 6 I/O I O I I I I/O Level TTL CMOS TTL TTL TTL Function This is a pin for JTAG boundary scan. Pull it up or ground it in normal operation. This is a pin for JTAG boundary scan. Leave it open in normal operation. This is a pin for JTAG boundary scan. Pull it up or ground it in normal operation. This is a pin for JTAG boundary scan. Pull it up or ground it in normal operation. This is a pin for JTAG boundary scan. Ground it in normal operation. 11 µPD98402A • Recommended Connection for Unused Pins Pin TDOC, TDOT, TCOC, TCOT, ACK, LOS, OOF, TCL, TxFP, RxFP RAL, TAL, TFSS Recommended connection leave open connect to GND 12 µPD98402A 2. ELECTRICAL SPECIFICATION Absolute maximum ratings Parameters Supply voltage Input/output voltage Operating ambient temperature Storage temperature Symbol V DD VI/VO TA Tstg Conditions Ratings –0.5 to +6.5 –0.5 to VDD +0.5 0 to +70 –65 to +150 Unit V V °C °C Caution Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC characteristics. Capacitance Parameters Input capacitance Output capacitance Input/output capacitance Symbol CI CO CIO f = 1 MHz Conditions MIN. TYP. 10 10 10 MAX. 20 20 20 Unit pF pF pF Recommended operating conditions Parameters Supply voltage Operating ambient temperature Symbol V DD TA VIL1 Low level input voltage VIL2 VIL3 VIH1 High level input voltage VIH2 VIH3 Note1 Note2 Note3 Note1 Note2 Note3 Conditions MIN. 4.75 0 0 V DD–2 0 2.2 V DD–1.1 0.7 V DD TYP. MAX. 5.25 +70 +0.8 V DD–1.5 0.3 VDD VDD VDD VDD V V Unit V °C Notes 1. 2. 3. TTL input pin Pseudo ECL input pin CMOS input pin 13 µPD98402A DC Characteristics (VDD = 5 V ±0.25 V, TA = 0 to +70 °C) Parameters Off-state output current Input leak current ILI2 VOH1 High level output voltage VOH2 V OL1 Low level output voltage V OL2 Supply current I DD Note 5 Normal operation V DD–2.0 — V DD–1.7 300 mA Note 5 IOL = 6.0 mA Note4 V DD–0.9 — V DD–0.4 0.4 V Note 3 IOH = –0.5 mA Note4 — 0.7 VDD 10 — V Symbol I OZ ILI1 Conditions VI = V DD or GND Note1 VI = V DD or GND Note2 MIN. — — TYP. MAX. 10 10 Unit µA µA Notes 1. 2. 3. 4. 5. 3-state data bus TTL input pin Pseudo ECL input pin CMOS output pin Pseudo ECL output pin 14 µPD98402A AC Characteristics (1) Management Interface Internal Register Read/Write Parameters A0-A5 setup time (to CE↓) R/W setup time (to CE↓) A0-A5 hold time (to CE↓) R/W hold time (to CE↓) CE↓→ACK↓ delay time (read) Symbol tSCC1 tSCC2 tHCC1 tHCC2 tDCNAR Load capacitor 15 pF At parallel data input Load capacitor 15 pF At serial data input CE↓→ACK↓ delay time (write) tDCNAW Load capacitor 15 pF At parallel data input Load capacitor 15 pF At serial data input CE↑→ACK↑ delay time tDCPA Load capacitor 15 pF At parallel data input Load capacitor 15 pF At serial data input CE↓→ data output delay time tDCD Load capacitor 15 pF At parallel data input Load capacitor 15 pF At serial data input OE↓→ data output delay time OE↑→ data floating output delay time D0-D7 setup time (to CE↓) D0-D7 hold time (to CE↓) CE low-level width tDOD tFOD tSDC tHCD tCEBW At parallel data input At serial data input OE low-level width tOEBW At parallel data input At serial data input Load capacitor 15 pF Load capacitor 15 pF Conditions MIN. 5 5 3 3 3× tCYPPR 3× (tCYPSR × 8) 2× tCYPPR 2× (tCYPSR × 8) 1× tCYPPR 1× (tCYPSR × 8) 2× tCYPPR 2× (tCYPSR × 8) — — 5 3 3.5 × tCYPPR 3.5 × (tCYPSR × 8) 2.5 × tCYPPR 2.5 × (tCYPSR × 8) 4.5 × tCYPPR 4.5 × (tCYPSR × 8) 3.5 × tCYPPR 3.5 × (tCYPSR × 8) 2.5 × tCYPPR 2.5 × (tCYPSR × 8) 3.5 × tCYPPR 3.5 × (tCYPSR × 8) 9.4 10 — — — ns — — ns — ns TYP. MAX. Unit ns ns ns ns ns ns ns ns ns Remarks 1. 2. For tCYPPR, refer to (6) PMD parallel interface timing. For tCYPSR, refer to (7) PMD serial interface timing. 15 µPD98402A Management Interface Internal Register Read (a) Case 1 When the host uses ACK signal tSCC1 A0-A5 tHCC1 R/W tSCC2 tHCC2 tCEBW CE tOEBW OE tDCNAR ACK tDOD Valid tDCD tDCPA D0-D7 tFOD (b) Case 2 When the host does not use ACK signal tSCC1 A0-A5 tHCC1 R/W tSCC2 tHCC2 tCEBW CE tOEBW OE Valid tDOD tFOD D0-D7 16 µPD98402A Internal Register Write tSCC1 A0-A5 tHCC1 tHCC2 R/W CE tSCC2 ACK tDCNAW Valid tSDC OE tHCD “H” tDCPA D0-D7 (2) OAM Interface Parameters TCL↑→LOS delay time RCL↑→OOF delay time Symbol tDCLS tDCOF Conditions load capacitor = 15 pF load capacitor = 15 pF MIN. 5 –5 TYP. MAX. 30 +7 Unit ns ns OAM Interface TCL RCL tDCLS LOS OOF tDCOF 17 µPD98402A (3) Control Signal Interface Parameters TCL↑→TPC delay time TFSS setup time (to TCL↑) TFSS hold time (to TCL↑) TCL↑→TxFP delay time RCL↑→RxFP delay time Symbol tDTCP tSFSC tHCFS tDCFP tDCRP load capacitor = 15 pF load capacitor = 15 pF Conditions load capacitor = 15 pF MIN. 0 10 5 0 –5 TYP. MAX. +5 — — +20 +20 Unit ns ns ns ns ns Control Signal Interface TPC tDTCP TCL tDCFP TFSS TxFP tSFSC tHCFS tDCFP RCL RxFP tDCRP tDCRP 18 µPD98402A (4) SAR Interface (Transmitter Side) Parameters TCLK cycle time TCLK high level width TCLK low level width TCLK↑→FULL↓ delay time TDI0-TDI7 setup time (to TCLK↑) TSOC setup time (to TCLK↑) TENBL setup time (to TCLK↑) TDI0-TDI7 hold time (to TCLK↑) TSOC hold time (to TCLK↑) TENBL hold time (to TCLK↑) Symbol tCYST tSTH tSTL tFD tSTDK1 tSTDK2 tSTDK3 tHKTD1 tHKTD2 tHKTD2 load capacitor = 15 pF Conditions MIN. 30 12 12 5 5 12 5 3 3 3 TYP. MAX. 125 110 110 17 — — — — — — Unit ns ns ns ns ns ns ns ns ns ns SAR Interface (Transmitter Side) tCYST TCLK tSTH FULL tFD TENBL tHKTD2 TSOC tSTDK1 tHKTD1 tSTDK2 tHKTD3 tSTDK3 tSTL TDI0-TDI7 P48 H1 Invalid H2 H3 19 µPD98402A (5) SAR Interface (Receiver Side) Parameters RCLK cycle time RCLK high level width RCLK low level width RCLK↑→EMPTY↑↓delay time RENBL setup time (to RCLK↑) RENBL hold time (to RCLK↑) RCLK↑→RSOC↑↓ delay time RCLK↑→RDO0-RDO7 delay time Symbol tSYCR tSRH tSRL tED tSREK tHKRE tRSD tRDD load capacitor = 15 pF load capacitor = 15 pF load capacitor = 15 pF Conditions MIN. 30 12 12 5 12 3 0 0 TYP. MAX. 125 110 110 17 — — 17 17 Unit ns ns ns ns ns ns ns ns SAR Interface (Receiver Side) tSYCR RCLK tSRH EMPTY tSREK tED RENBL tRSD RSOC tRDD RDO0-RDO7 P48 H1 tRDD H2 H3 tRSD tED tHKRE tSRL 20 µPD98402A (6) PMD Parallel Interface Parameters RPC cycle time RPC high level width RPC low level width TFC cycle time TFC high level width TFC low level width RPD0-RPD7 setup time (to RPC↑) RPD0-RPD7 hold time (to RPC↑) TFC↑→TPC↑ delay time TFC↓→TPC↓ delay time TPC↑→TPD0-TPD7 delay time Symbol tCYPPR tPPRH tPPRL tCYPPT tPPTH tPPTL tSPDC tHPCD tDFPCP tDFPCN tDPCD load capacitor = 15 pF load capacitor = 15 pF load capacitor = 15 pF Conditions MIN. 50 20 20 50 20 20 5 3 3 3 –3.0 TYP. MAX. — — — — — — — — 25 25 +1.0 Unit ns ns ns ns ns ns ns ns ns ns ns PMD Parallel Interface Receive Side tCYPPR tPPRH RPC tPPRL RPD0-RPD7 tSPDC tHPCD Transmit Side tDFPCP TFC tDFPCN tCYPPT tPPTH tPPTL TPC TPD0-TPD7 tDPCD 21 µPD98402A (7) PMD Serial Interface Parameters RCIT (RCIC) cycle time TFKT (TFKC) cycle time Serial data setup time Serial data hold time Serial clock delay time (rising) Serial clock delay time (falling) Transmit serial data delay time Symbol tCYPSR tCYPST tSSDC tHSCD tDFSCP tDFSCN tDSCD Load capacitor 15 pF Load capacitor 15 pF Load capacitor 15 pF Conditions MIN. 6.4 6.4 1.0 1.0 — — — TYP. MAX. — — — — 8 8 3 Unit ns ns ns ns ns ns ns PMD Serial Interface Receive Side tCYPSR RCIC, RCIT RDIC, RDIT tSSDC tHSCD Transmit Side tDFSCP TFKC, TFKT tDFSCN tCYPST TCOC, TCOT TDOC, TDOT tDSCD 22 µPD98402A 3. PACKAGE DRAWING 160 PIN PLASTIC QFP (FINE PITCH) ( 24) A B 120 121 81 80 detail of lead end CD S Q R 160 1 41 40 F G H I M J K P N NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. M L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 26.0±0.2 24.0±0.2 24.0±0.2 26.0±0.2 2.25 2.25 0.22 +0.05 –0.04 0.10 0.5 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 –0.07 0.10 2.7 0.125±0.075 5°±5° 3.0 MAX. INCHES 1.024 +0.008 –0.009 0.945±0.008 0.945±0.008 1.024 +0.008 –0.009 0.089 0.089 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 –0.008 0.020 +0.008 –0.009 0.007 +0.001 –0.003 0.004 0.106 0.005±0.003 5°±5° 0.119 MAX. S160GM-50-3ED, JED, KED-2 23 µPD98402A 4. RECOMMENDED SOLDERING CONDITIONS For the µPD98402A, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document “Semiconductor Device Mounting Technology Manual” (IEI-1207). For other soldering methods, please consult with NEC sales personnel. • µPD98402AGM-KED: 160-pin plastic QFP (FINE PITCH) (24 × 24 mm) Soldering Method Soldering Conditions Package peak temperature: 235 °C, time: 30 sec. max. (over 210 ° C), count: twice or less, restriction days: 3Note (after that, 125 ° C pre-baking for 20 hours is necessary) Precautions: (1) Reflow a second time should be started when the device temperature has returned to its normal state after the first reflow. (2) Avoid flux cleaning with water after the first reflow. Pin temperature: 300 ° C max., time: 3 seconds max. (per side) Symbol Infrared reflow IR35-203-2 Pin partial heating — Note This means the number of days after unpacking the dry pack. Storage conditions are 25 ° C and 65 % RM max. 24 µPD98402A [MEMO] 25 µPD98402A [MEMO] The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 26