74F181

54F 74F181 4-Bit Arithmetic Logic Unit August 1995 54F 74F181 4-Bit Arithmetic Logic Unit General Description The ’F181 is a 4-bit Arithmetic logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations It is 40% faster than the Schottky ALU and only consumes 30% as much power Features Y Y Full lookahead for high-speed arithmetic operation on long words Guaranteed 4000V minimum ESD protection Commercial 74F181PC 74F181SPC Military Package Number N24A N24C Package Description 24-Lead (0 600 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead Ceramic Dual-In-Line 24-Lead (0 300 ) Ceramic Dual-In-Line 24-Lead (0 300 ) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F181DM (Note 2) 54F181SDM (Note 2) 74F181SC (Note 1) 54F181FM (Note 2) 54F181LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX J24A J24F M24B W24C E28A Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9491 – 2 TL F 9491 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9491 RRD-B30M105 Printed in U S A Logic Symbols Active-HIGH Operands Active-LOW Operands IEEE IEC TL F 9491–3 TL F 9491 – 4 Unit Loading Fan Out 54F 74F Pin Names Description UL Input IIH IIL HIGH LOW Output IOH IOL 10 30 10 30 10 40 10 10 10 50 50 33 3 OC 33 3 50 33 3 50 33 3 50 33 3 20 mA b1 8 mA 20 mA b1 8 mA 20 mA b2 4 mA 20 mA b0 6 mA 20 mA b3 0 mA b 1 mA 20 mA 20 mA b 1 mA 20 mA b 1 mA 20 mA b 1 mA 20 mA TL F 9491 – 10 A 0 – A3 B 0 – B3 S0 – S3 M Cn F0 – F3 AeB G P Cn a 4 A Operand Inputs (Active LOW) B Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output OC-Open Collector Functional Description The ’F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU) Controlled by the four Function Select inputs (S0 – S3) and the Mode Control input (M) it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands The Function Table lists these operations When the Mode Control input (M) is HIGH all internal carries are inhibited and the device performs logic operations on the individual bits as listed When the Mode Control input is LOW the carries are enabled and the device performs arithmetic operations on the two 4-bit words The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn a 4 output or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate) In the Add mode P indicates that F is 15 or more while G indicates that F is 16 or more In the Subtract mode P indicates that F is zero or less while G indicates that F is less than zero P and G are not affected by carry in When speed requirements are not stringent the ’F181 can be used in a simple Ripple Carry mode by connecting the Carry output (Cn a 4) signal to the Carry input (Cn) of the next unit For high speed operation the device is used in conjunction with a carry lookahead circuit One carry lookahead package is required for each group of four ’F181 devices Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths The A e B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode The A e B output is open collector and can be wired AND with other A e B outputs to give a comparison for more than four bits The A e B signal can also be used with the Cn a 4 signal to indicate AlB and AkB The Function Table lists the arithmetic operations that are performed without a carry in An incoming carry adds a one to each operation Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied Because subtraction is actually performed by complementary addition (1s complement) a carry out means borrow thus a carry is generated when there is no underflow and no carry is generated when there is underflow As indicated this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs For either case the table lists the operations that are performed to the operands labeled inside the logic symbol 2 ’F181 Operation Table S0 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H S1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H S2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H S3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H Logic (M e H) A AB AaB Logic ‘‘1’’ AaB B AZB AaB AB AZB B AaB Logic ‘‘0’’ AB AB A A AaB AB Logic ‘‘0’’ AB B AZB AB AaB AZB B AB Logic ‘‘1’’ AaB AaB A A AaB AB Logic ‘‘1’’ AB B AZB AaB AaB AZB B AaB Logic ‘‘0’’ AB AB A A AB AaB Logic ‘‘0’’ AaB B AZB AB AB AZB B AB Logic ‘‘1’’ AaB AaB A Arithmetic (M e L C0 e Inactive) A minus 1 A  B minus 1 A  B minus 1 minus 1 (2s comp ) A plus (A a B) A  B plus (A a B) A minus B minus 1 AaB A plus (A a B) A plus B A  B plus (A a B) AaB A plus A (2 c A) A plus A  B A plus A  B A A AaB AaB minus 1 (2s comp ) A plus (A  B) A  B plus (A a B) A minus B minus 1 A  B minus 1 A plus A  B A plus B A  B plus (A a B) A  B minus 1 A plus A (2 c A) A plus (A a B) A plus (A a B) A minus 1 A minus 1 A  B minus 1 A  B minus 1 minus 1 (2s comp ) A plus (A a B) A  B plus (A a B) A plus B AaB A plus (A a B) A minus B minus 1 A  B plus (A a B) AaB A plus A (2 c A) A plus A  B A plus A  B A A AaB AaB minus 1 (2s comp ) A plus A  B A  B plus (A a B) A plus B A  B minus 1 A plus A  B A minus B minus 1 A  B plus (A a B) A  B minus 1 A plus A (2 c A) A plus (A a B) A plus (A a B) A minus 1 Arithmetic (M e L C0 e Active) A AB AB Zero A plus (A a B) plus 1 A  B plus (A a B) plus 1 A minus B A a B plus 1 A plus (A a B plus 1 A plus B plus 1 A  B plus (A a B) plus 1 A a B plus 1 A plus A (2 c A) plus 1 A plus A  B plus 1 A plus A  B plus 1 A plus 1 A plus 1 A a B plus 1 A a B plus 1 Zero A plus A  B plus 1 A  B plus (A a B) plus 1 A minus B AB A plus A  B plus 1 A plus B plus 1 A  B plus (A a B) plus 1 AB A plus A (2 c A) plus 1 A plus (A a B) plus 1 A plus (A a B) plus 1 A A AB AB Zero A plus (A a B) plus 1 A  B plus (A a B) plus 1 A plus B plus 1 A a B plus 1 A plus (A a B) plus 1 A minus B A  B plus (A a B) plus 1 A a B plus 1 A plus A (2 c A) plus 1 A plus A  B plus 1 A plus A  B plus 1 A plus 1 A plus 1 A a B plus 1 A a B plus 1 Zero A plus A  B plus 1 A  B plus (A a B) plus 1 A plus B plus 1 AB A plus A  B plus 1 A minus B A  B plus (A a B) plus 1 AB A plus A (2 c A) plus 1 A plus (A a B) plus 1 A plus (A a B) plus 1 A a All Input Data Inverted b All Input Data True c A Input Data Inverted B Input Data True d A Input Data True B Input Date Inverted 3 Logic Diagram 4 TL F 9491 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V C C C C Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V b 0 5V to VCC b 0 5V to a 5 5V DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75 b0 6 b1 8 b2 4 b3 0 b 60 b 150 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC (Fn G P Cn a 4) IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN VIN VIN VIN e e e e 25 25 27 05 05 20 0 50 100 70 250 50 VOL IIH IBVI ICEX VID IOD IIL V mA mA mA V mA Min Max Max Max 00 00 mA Max 0 5V (M) 0 5V (A0 A1 A3 B0 B1 B3) 0 5V (Sn A2 B2) 0 5V (Cn) IOS IOHC ICCH ICCL Output Short-Circuit Current Open Collector Output OFF Leakage Test Power Supply Current Power Supply Current mA mA mA mA Max Min Max Max VOUT e 0V (Fn G P Cn a 4) VO e VCC (A e B) VO e HIGH VO e LOW 250 43 43 65 0 65 0 5 AC Electrical Characteristics 74F Symbol Path tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Cn to Cn a 4 Propagation Delay A or B to Cn a 4 Propagation Delay A or B to Cn a 4 Propagation Delay Cn to F Propagation Delay A or B or G Propagation Delay A or B to G Propagation Delay A or B to P Propagation Delay A or B to P Propagation Delay Ai or Bi to Fi Propagation Delay Ai or Bi to Fi Propagation Delay Any A or B to Any F Propagation Delay Any A or B to Any F Propagation Delay A or B to F Propagation Delay A or B to A e B Sum Dif Any Sum Dif Sum Dif Sum Dif Sum Dif Logic Dif Parameter Mode Min 30 30 50 40 50 50 30 30 30 30 30 30 30 30 30 40 30 30 30 30 40 40 45 35 40 40 11 0 60 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 64 61 10 0 94 10 8 10 0 67 65 57 58 65 73 50 55 58 65 70 72 82 50 80 78 94 94 60 60 18 5 98 Max 85 80 13 0 12 0 14 0 13 0 85 85 75 75 85 95 70 75 75 85 90 10 0 11 0 11 0 10 5 10 0 12 0 12 0 90 10 0 27 0 12 5 54F TA VCC e Mil CL e 50 pF Min 30 30 50 35 50 40 25 25 25 25 25 25 25 30 25 30 30 30 30 30 35 40 35 30 35 30 80 55 Max 10 0 95 15 5 16 5 17 0 15 0 16 0 12 0 90 95 11 5 11 0 85 95 11 0 11 0 14 5 14 5 17 5 14 5 16 5 13 5 17 5 14 0 14 5 15 5 35 0 21 0 74F TA VCC e Com CL e 50 pF Min 30 30 50 40 50 50 30 30 30 30 30 30 30 30 30 40 30 30 30 30 40 40 45 35 40 40 11 0 60 Max 95 90 14 0 13 0 15 0 14 0 95 95 85 85 95 10 5 80 85 85 95 10 0 10 0 12 0 12 0 11 5 11 0 13 0 13 0 10 0 11 0 29 0 13 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP SP e Slim Plastic DIP D e Ceramic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC 181 P C Special Variations QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 6 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24A 7 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0 300 Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 24-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M24B 8 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0 600 Wide) Molded Dual-In-Line Package (P) NS Package Number N24A 24-Lead (0 300 Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 54F 74F181 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED 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