ADC12451CMJ

ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A D Converter with Sample-and-Hold December 1994 ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A D Converter with Sample-and-Hold General Description The ADC12451 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic specifications (S N THD etc ) are tested and guaranteed On request the ADC12451 goes through a self-calibration cycle that adjusts linearity zero and full-scale errors The ADC12451 also has the ability to go through an Auto-Zero cycle that corrects the zero error during every conversion The analog input to the ADC12451 is tracked and held by the internal circuitry so an external sample-and-hold is not required The ADC12451 has a S H control input which directly controls the track-and-hold state of the A D A unipolar analog input voltage range (0V to a 5V) or a bipolar range (b5V to a 5V) can be accommodated with g 5V supplies The 13-bit data result is available on the eight outputs of the ADC12451 in two bytes high-byte first and sign extended The digital inputs and outputs are compatible with TTL or CMOS logic levels Y Y Y Telecommunications High Resolution Process Control Instrumentation Features Y Y Y Y Self-calibration provides excellent temperature stability Internal sample-and-hold 8-bit mP DSP interface Bipolar input range with a single a 5V reference Key Specifications Y Y Y Y Y Y Y Y Applications Y Y Y Y Digital Signal Processing Audio Resolution Conversion Time Sampling Rate Bipolar Signal Noise Total Harmonic Distortion Aperture Time Aperture Jitter Zero Error Positive Full-Scale Error Power Consumption g 5V 12 bits plus sign 7 7 ms (max) 83 kHz (max) 73 5 dB (min) b 78 0 dB (max) 100 ns 100 psrms g 2 LSB (max) g 1 5 LSB (max) 113 mW (max) Simplified Block Diagram Connection Diagram Dual-In-Line Package TL H 11025 – 2 Top View Ordering Information Industrial (b40 C s TA s 85 C) ADC12451CIJ TL H 11025 – 1 Package J24A Military Package (b55 C s TA s 125 C) ADC12451CMJ ADC12451CMJ 883 J24A TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL H 11025 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Ratings (Notes 1 Temperature Range ADC12451CIJ ADC12451CMJ ADC12451CMJ 883 DVCC and AVCC Voltage (Notes 6 7) Negative Supply Voltage (Vb) Reference Voltage (VREF Notes 6 7) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC e DVCC e AVCC) 6 5V b 6 5V Negative Supply Voltage (Vb) b 0 3V to (VCC a 0 3V) Voltage at Logic Control Inputs Voltage at Analog Inputs (VIN VREF) (Vb b0 3V) to (VCC a 0 3V) 0 3V AVCC-DVCC (Note 7) g 5 mA Input Current at any Pin (Note 3) g 20 mA Package Input Current (Note 3) 875 mW Power Dissipation at 25 C (Note 4) b 65 C to a 150 C Storage Temperature Range ESD Susceptability (Note 5) Soldering Information J Package (10 Seconds) 2000V 300 C 2) TMIN s TA s TMAX b 40 C s TA s a 85 C b 55 C s TA s a 125 C 4 5V to 5 5V b 4 5V to b 5 5V 3 5V to AVCC a 50 mV Converter Electrical Characteristics The following specifications apply for VCC e DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V using S H input for conversion control and fCLK e 3 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 7 and 8) Symbol Parameter Conditions Typical (Note 9) Limit (Note 10 19) Units (Limit) STATIC CHARACTERISTICS Positive Integral Linearity Error Negative Integral Linearity Error Positive or Negative Differential Linearity Zero Error (Notes 12 13) After Auto-Cal (Notes 11 After Auto-Cal (Notes 11 After Auto-Cal (Notes 11 12) 12) 12) g g LSB LSB Bits LSB g2 g3 0 12 g1 AZ e ‘‘0’’ fCLK e 1 75 MHz After Auto-Cal Only LSB(max) LSB Positive Full-Scale Error (Note 12) AZ e ‘‘0’’ fCLK e 1 75 MHz Auto-Cal Only g1 g1 5 g2 5 g1 g1 5 g3 0 LSB(max) LSB LSB(max) V(min) V(max) LSB LSB LSB pF pF Negative Full-Scale Error (Note 12) AZ e ‘‘0’’ fCLK e 1 75 MHz Auto-Cal Only VIN Analog Input Voltage Power Supply Sensitivity Zero Error (Note 14) AVCC e DVCC e 5V g 5% VREF e 4 75V Vb e b5V g 5% Full-Scale Error Linearity Error g g g Vb b 0 05 VCC a 0 05 CREF CIN VREF Input Capacitance Analog Input Capacitance 80 65 DYNAMIC CHARACTERISTICS Bipolar Effective Bits (Note 17) fIN e 1 kHz VIN e g 4 85V fIN e 20 67 kHz VIN e g 4 85V Unipolar Effective Bits (Note 17) fIN e 1 kHz VIN e 4 85 Vp-p fIN e 20 67 kHz VIN e 4 85 Vp-p SN Bipolar Signal to Noise Ratio (Note 17) fIN e 1 kHz VIN e g 4 85V fIN e 10 kHz VIN e g 4 85V fIN e 20 67 kHz VIN e g 4 85V 12 6 12 6 11 8 11 8 78 78 78 73 5 11 1 11 9 Bits Bits(min) Bits Bits(min) dB dB dB(min) 2 Converter Electrical Characteristics (Continued) The following specifications apply for VCC e DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V using S H input for conversion control and fCLK e 3 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 7 and 8) Symbol Parameter Conditions Typical Limit (Note 9) (Note 10 19) Units (Limit) DYNAMIC CHARACTERISTICS (Continued) SN Unipolar Signal to Noise Ratio (Note 17) fIN e 1 kHz VIN e 4 85 Vp-p fIN e 10 kHz VIN e 4 85 Vp-p fIN e 20 67 kHz VIN e 4 85 Vp-p THD Bipolar Total Harmonic Distortion (Note 17) fIN e 1 kHz VIN e g 4 85V fIN e 20 67 kHz VIN e g 4 85V THD Unipolar Total Harmonic Distortion (Note 17) fIN e 1 kHz VIN e 4 85 Vp-p fIN e 20 67 kHz VIN e 4 85 Vp-p Bipolar Peak Harmonic or Spurious Noise (Note 17) fIN e 1 kHz VIN e g 4 85V fIN e 10 kHz VIN e g 4 85V fIN e 20 kHz VIN e g 4 85V Unipolar Peak Harmonic or Spurious Noise (Note 17) fIN e 1 kHz VIN e 4 85 Vp-p fIN e 10 kHz VIN e 4 85 Vp-p fIN e 20 kHz VIN e 4 85 Vp-p Bipolar Two Tone Intermodulation Distortion (Note 17) Unipolar Two Tone Intermodulation Distortion (Note 17) b 3 dB Bipolar Full Power Bandwidth b 3 dB Unipolar Full Power Bandwidth 73 73 73 b 82 b 80 b 82 b 80 b 88 b 84 b 80 b 90 b 86 b 82 b 78 b 78 b 73 1 b 78 0 dB dB 68 7 dB(min) dB dB(max) dB dB(max) dB dB dB dB dB dB dB(max) dB(max) 20 67 20 67 kHz(min) kHz(min) ns psrms VIN e g 4 85V fIN1 e 19 375 kHz fIN2 e 20 kHz VIN e 4 85 Vp-p fIN1 e 19 375 kHz fIN2 e 20 kHz VIN e g 4 85V (Note 17) VIN e 4 85 Vp-p (Note 17) 25 32 100 100 Aperture Time Aperture Jitter 3 Digital and DC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V and fCLK e 3 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7) Symbol VIN(1) VIN(0) IIN(1) IIN(0) VT a VTb VH VOUT(1) Parameter Logical ‘‘1’’ Input Voltage for All Inputs except CLK IN Logical ‘‘0’’ Input Voltage for All Inputs except CLK IN Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current CLK IN Positive-Going Threshold Voltage CLK IN Negative-Going Threshold Voltage CLK IN Hysteresis VT a (min) b VTb(max) Logical ‘‘1’’ Output Voltage VCC e 4 75V IOUT e b360 mA IOUT e b10 mA VCC e 4 75V IOUT e 1 6 mA VOUT e 0V VOUT e 5V VOUT e 0V VOUT e 5V CS e ‘‘1’’ CS e ‘‘1’’ CS e ‘‘1’’ b 0 01 Condition VCC e 5 25V VCC e 4 75V VIN e 5V VIN e 0V Typical (Note 9) Limit (Note 10 19) 20 08 Units (Limit) V(min) V(max) mA(max) mA(max) V(min) V(max) V(min) 0 005 b 0 005 1 b1 28 21 07 27 23 04 24 45 04 b3 V(min) V(min) V(max) mA(max) mA(max) mA(min) mA(min) mA(max) mA(max) mA(max) VOUT(0) IOUT Logical ‘‘0’’ Output Voltage TRI-STATE Output Leakage Current Output Source Current Output Sink Current DVCC Supply Current AVCC Supply Current Vb Supply Current 0 01 b 20 3 b6 0 ISOURCE ISINK DICC AICC Ib 20 1 28 28 80 25 10 10 AC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5 0V Vb e b5 0V tr e tf e 20 ns unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7) Symbol fCLK Parameter Clock Frequency 05 60 Clock Duty Cycle 50 40 60 tC Conversion Time using WR to start a Conversion 27(1 fCLK) fCLK e 3 5 MHz AZ e ‘‘1’’ fCLK e 1 75 MHz AZ e ‘‘0’’ tC Conversion Time using S H to start a Conversion AZ e ‘‘1’’ fCLK e 3 5 MHz AZ e ‘‘1’’ 77 15 4 34(1 fCLK) 97 27(1 fCLK) a 250 ns 7 95 15 65 34(1 fCLK) a 250 ns 9 95 35 Conditions Typical (Note 9) Limit (Note 10 19) Units (Limit) MHz MHz(min) MHz(max) % %(min) %(max) (max) ms(max) ms(max) (max) ms(max) 4 AC Electrical Characteristics (Continued) The following specifications apply for DVCC e AVCC e a 5 0V Vb e b5 0V tr e tf e 20 ns unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7) Symbol tA tIA tZA Parameter Acquisition Time (Note 15) Internal Acquisition Time (when using WR Control Only) Auto Zero Time a Acquisition Time Delay from Hold Command to Falling Edge of EOC Calibration Time fCLK e 3 5 MHz tW(CAL)L tW(WR)L tACC Calibration Pulse Width minimum WR Pulse Width maximum Access Time (Delay from Falling Edge of RD to Output Data Valid) TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) maximum Delay from Falling Edge of RD or WR to Reset of INT Delay between Successive RD Pulses CL e 100 pF 50 RL e 1 kX CL e 100 pF 95 ns(max) (Note 16) Conditions RSOURCE e 50X Typical (Note 9) 35 7(1 fCLK) 33(1 fCLK) fCLK e 1 75 MHz Using WR Control Using S H Control 18 8 200 100 1399 (1 fCLK) 399 60 60 Limit (Note 10 19) 35 7(1 fCLK) 33(1 fCLK) a 250 ns 19 05 350 150 1399 (1 fCLK) 400 200 200 Units (Limit) ms(min) (max) (max) ms(max) ns(max) ns(max) (max) ms(max) ns(min) ns(min) tD(EOC)L tCAL t0H t1H 30 70 ns(max) tPD(INT) tRR 100 30 175 60 ns(max) ns(min) Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2 All voltages are measured with respect to AGND and DGND unless otherwise specified Note 3 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to 5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power supply voltages Note 4 The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation a 1 TTL Load on each digital output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMax (maximum junction temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature is PDMax e (TJMax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJMax e 150 C and the typical thermal resistance (iJA) of the ADC12451 with CMJ and CIJ suffixes when board mounted is 51 C W Note 5 Human body model 100 pF discharged through a 1 5 kX resistor Note 6 Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than b 50 mV This means that if AVCC and DVCC are minimum (4 75 VDC) and V is maximum ( b 4 75 VDC) the analog input full-scale voltage must be s g 4 8 VDC TL H 11025 – 4 5 Electrical Characteristics (Continued) Note 7 A diode exists between AVCC and DVCC as shown below TL H 11025 – 5 To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin Note 8 Accuracy is guaranteed at fCLK e 3 5 MHz At higher or lower clock frequencies accuracy may degrade see the typical performance characteristic curves Note 9 Typicals are at TJ e 25 C and represent most likely parametric norm Note 10 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 11 Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and zero For negative linearity error the straight line passes through negative full scale and zero (See Figures 1b and 1c ) Note 12 The ADC12451’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will result in a repeatability uncertainty of g 0 20 LSB Note 13 If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started see the typical performance characteristic curves Note 14 After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes Note 15 When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the end of the interval of tA therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the clock is synchronous to the rising edge of WR then tA will end exactly 6 5 clock periods after the rising edge of WR This does not occur when S H control is used Note 16 The CAL line must be high before a conversion is started Note 17 The specifications for these parameters are valid after an Auto-Cal cycle has been completed Note 18 The ADC12451 reference ladder is composed solely of capacitors Note 19 A military RETS electrical test specification is available on request At time of printing the ADC12451CMJ 883 RETS specification complies fully with the boldface limits in this column TL H 11025 – 6 FIGURE 1a Transfer Characteristic 6 Electrical Characteristics (Continued) TL H 11025 – 7 FIGURE 1b Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles TL H 11025 – 8 FIGURE 1c Simplified Error Curve vs Output Code after Auto-Cal Cycle Typical Performance Characteristics Zero Error Change vs Ambient Temperature Zero Error vs VREF Linearity Error vs VREF TL H 11025 – 9 7 Typical Performance Characteristics Linearity Error vs Clock Frequency (Continued) Bipolar Signal-toNoise a Distortion Ratio vs Input Source Impedance Full Scale Error Change vs Ambient Temperature Bipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Spectral Response with 1 kHz Sine Wave Input Bipolar Spectral Response with 10 kHz Sine Wave Input Bipolar Spectral Response with 20 kHz Sine Wave Input Bipolar Spectral Response with 40 kHz Sine Wave Input Unipolar Spectral Response with 1 kHz Sine Wave Input TL H 11025 – 10 8 Typical Performance Characteristics Unipolar Spectral Response with 10 kHz Sine Wave Input (Continued) Unipolar Spectral Response with 40 kHz Sine Wave Input Unipolar Spectral Response with 20 kHz Sine Wave Input TL H 11025 – 11 Test Circuits TL H 11025 – 13 TL H 11025 – 12 TL H 11025 – 15 TL H 11025 – 14 FIGURE 2 TRI-STATE Test Circuits and Waveforms 9 Timing Diagrams Auto-Cal Cycle TL H 11025 – 16 Using WR Control to Start a Conversion with Auto-Zero (CAL e 1 AZ e 0) TL H 11025 – 17 10 Timing Diagrams (Continued) Using WR Control to Start a Conversion without Auto-Zero (CAL 1 AZ e 1) TL H 11025 – 18 Using S H Control to Start a Conversion without Auto-Zero (AZ e 1 CAL e 1) TL H 11025 – 19 11 1 0 Pin Descriptions DVCC (24) AVCC (4) The digital and analog positive power supply pins The digital and analog power supply voltage range of the ADC12451 is a 4 5V to a 5 5V To guarantee accuracy it is required that the AVCC and DVCC be connected together to the same power supply with separate bypass capacitors (10 mF tantalum in parallel with a 0 1 mF ceramic) at each VCC pin The analog negative supply voltage pin Vb has a range of b4 5V to b5 5V and needs bypass capacitors of 10 mF tantalum in parallel with a 0 1 mF ceramic The digital and analog ground pins AGND and DGND must be connected together externally to guarantee accuracy The reference input voltage pin To maintain accuracy the voltage at this pin should not exceed the AVCC or DVCC by more than 50 mV or go below a 3 5 VDC The analog input voltage pin To guarantee accuracy the voltage at this pin should not exceed VCC by more than 50 mV or go below Vb by more than 50 mV The Chip Select control input This input is active low and enables the WR RD and S H functions The Read control input With both CS and RD low the TRI-STATE output buffers are enabled and the INT output is reset high The Write control input The conversion is started on the rising edge of the WR pulse when CS is low When this control line is used the end of the analog input voltage acquisition window is internally controlled by the ADC12451 The sample and hold control input This control input can also be used to start a conversion With CS low the falling edge of S H starts the analog input acquisition window The rising edge of S H ends the acquisition window and starts a conversion The external clock input pin The typical clock frequency range is 500 kHz to 6 0 MHz The Auto-Calibration control input When CAL is low the ADC12451 is reset and a calibration cycle is initiated During the calibration cycle the values of the comparator offset voltage and the mismatch errors in the capacitor reference ladder are determined and stored in RAM These values are used to correct the errors during a normal cycle of A D conversion The Auto-Zero control input With the AZ pin held low during a conversion the ADC12451 goes into an auto-zero cycle before the actual A D conversion is started This Auto-Zero cycle corrects for the comparator offset voltage The total conversion time (tC) is increased by 26 clock periods when Auto-Zero is used EOC (22) The End-of-Conversion control output This output is low during a conversion or a calibration cycle The Interrupt control output This output goes low when a conversion has been completed and indicates that the conversion result is available in the output latches Reading the result or starting a conversion or calibration cycle will reset this output high The TRI-STATE output pins Twelve bit plus sign output data access is accomplished using two successive RDs of one byte each high byte first (DB8 – DB12) The data format used is two’s complement sign bit extended with DB12 the sign bit DB11 the MSB and DB0 the LSB INT (21) V b (5) DB0 DB8 DB7 DB12 (13 – 20) DGND (12) AGND (3) VREF (2) 2 0 Functional Description The ADC12451 is a 12-bit plus sign A D converter with the capability of doing Auto-Zero or Auto-Calibration routines to minimize zero full-scale and linearity errors It is a successive-approximation A D converter consisting of a DAC comparator and a successive-approximation register (SAR) Auto-Zero is an internal calibration sequence that corrects for the A D’s zero error caused by the comparator’s offset voltage Auto-Cal is a calibration cycle that not only corrects zero error but also corrects for full-scale and linearity errors caused by DAC inaccuracies Auto-Cal minimizes the errors of the ADC12451 without the need of trimming during its fabrication An Auto-Cal cycle can restore the accuracy of the ADC12451 at any time which ensures accuracy over temperature and time 2 1 DIGITAL INTERFACE On power up a calibration sequence should be initiated by pulsing CAL low with CS and S H high To acknowledge the CAL signal EOC goes low after the falling edge of CAL and remains low during the calibration cycle of 1399 clock periods During the calibration sequence first the comparator’s offset is determined then the capacitive DAC’s mismatch error is found Correction factors for these errors are then stored in internal RAM A conversion is initiated by taking CS and WR low If AZ is low an Auto-Zero cycle which takes approximately 26 clock periods is inserted before the analog input is sampled and the actual conversion is started AZ must remain low during the complete conversion sequence After Auto-Zero the acquisition opens and the analog input is sampled for appproximately 7 clock periods If AZ is high the Auto-Zero cycle is not inserted after the rising edge of WR In this case the acquisition window opens when the ADC12451 completes a conversion signaled by the rising edge of EOC At the end of the acquisition window EOC goes low signaling that the analog input is no longer being sampled and that the A D successive approximation conversion has started VIN (1) CS (10) RD (23) WR (7) S H (11) CLKIN (8) CAL (9) AZ (6) 12 2 0 Functional Description (Continued) A conversion sequence can also be controlled by the S H and CS inputs Taking CS and S H low starts the acquisition window for the analog input voltage The rising edge of S H immediately puts the A D in the hold mode and starts the conversion Using S H will simplify synchronizing the end of the acquisition window to other signals which may be necessary in a DSP environment During a conversion the sampled input voltage is successively compared to the output of the DAC First the acquired input voltage is compared to analog ground to determine its polarity The sign bit is set low for positive input voltages and high for negative Next the MSB of the DAC is set high with the rest of the bits low If the input voltage is greater than the output of the DAC then the MSB is left high otherwise it is set low The next bit is set high making the output of the DAC three quarters or one quarter of full scale A comparison is done and if the input is greater than the new DAC value this bit remains high if the input is less than the new DAC value the bit is set low This process continues until each bit has been tested The result is then stored in the output latch of the ADC12451 Next INT goes low and EOC goes high to signal the end of the conversion The result can now be read by taking CS and RD low to enable the DB0 DB8–DB7 DB12 output buffers The high byte of data is relayed first on the data bus outputs as shown below DB0 DB8 Bit 8 DB1 DB9 Bit 9 DB2 DB3 DB10 DB11 Bit 10 MSB DB4 DB12 DB5 DB12 DB6 DB12 DB7 DB12 the operation of the ADC12451 Care should be taken not to inadvertently be in this mode since DB2 DB3 DB5 and DB6 become active outputs which may cause data bus contention 2 2 RESETTING THE A D The ADC12451 is reset whenever a new conversion is started by taking CS and WR or S H low If this is done when the analog input is being sampled or when EOC is low the Auto-Cal correction factors may be corrupted therefore requiring an Auto-Cal cycle before the next conversion When using WR or S H without Auto-Zero (AZ e 1) to start a conversion a new conversion can be restarted only after EOC has gone high signaling the end of the current conversion When using WR with Auto-Zero (AZ e 0) a new conversion can be restarted during the first 26 clock periods after the rising edge of WR (tZ) or after EOC has returned high without corrupting the Auto-Cal correction factors The Calibration Cycle cannot be reset once started On power-up the ADC12451 automatically goes through a Calibration Cycle that takes typically 1399 clock cycles For reasons that will be discussed in Section 3 8 a new calibration cycle needs to be started after the completion of the automatic one 3 0 Analog Considerations 3 1 REFERENCE VOLTAGE The voltage applied to the reference input of the converter defines the voltage span of the analog input (the difference between VIN and AGND) over which 4095 positive output codes and 4096 negative output codes exist The A-to-D can be used in either ratiometric or absolute reference applications The voltage source driving VREF must have a very low output impedance and very low noise The circuit in Figure 4a is an example of a very stable reference that is appropriate for use with the ADC12451 The simple reference circuit of Figure 4b may be used when the application does not require a low full-scale error Sign Bit Sign Bit Sign Bit Sign Bit Taking CS and RD low a second time will relay the low byte of data on the data bus outputs as shown below DB0 DB8 LSB DB1 DB9 Bit 1 DB2 DB10 Bit 2 DB3 DB11 Bit 3 DB4 DB12 Bit 4 DB5 DB12 Bit 5 DB6 DB12 Bit 6 DB7 DB12 Bit 7 The table in Figure 3 summarizes the effect of the digital control inputs on the function of the ADC12451 The Test Mode where RD and S H are high and CS and CAL are low is used during manufacture to thoroughly check out Digital Control Inputs CS WR 1 1 1 X X SH 1 1 1 1 1 X RD 1 1 1 X 1 CAL 1 1 1 1 1 0 AZ 1 1 1 0 0 X X A D Function Start Conversion without Auto-Zero Start Conversion synchronous with rising edge of S H without Auto-Zero Read Conversion Result without Auto-Zero Start Conversion with Auto-Zero Read Conversion Result with Auto-Zero Start Calibration Cycle Test Mode (DB2 DB3 DB5 and DB6 become active) 1 0 FIGURE 3 Function of the A D Control Inputs 13 3 0 Analog Considerations (Continued) TL H 11025 – 21 TL H 11025 – 20 FIGURE 4a Low Drift Extremely Stable Reference Circuit In a ratiometric system the analog input voltage is proportional to the voltage used for the A D reference When this voltage is the system power supply the VREF pin can be tied to VCC This technique relaxes the stability requirement of the system reference as the analog input and A D reference move together maintaining the same output code for a given input condition For absolute accuracy where the analog input varies between very specific voltage limits the reference pin can be biased with a time and temperature stable voltage source In general the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors 3 2 ACQUISITION WINDOW As shown in the timing diagrams there are three different methods of starting a conversion each of which affects the acquisition window and timing With Auto-Zero high a conversion can be started with the WR or S H controls In either method of starting a conversion the rising edge of EOC signals the actual beginning of the acquisition window At this time a voltage spike may be noticed on the analog input of the ADC12451 whose amplitude is dependent on the input voltage and the source resistance The timing diagrams for these two methods of starting a conversion do not show the acquisition window starting at this time because the acquisition time (tA) must start after the conversion result high and low bytes have been read This is necessary since activating and deactivating the digital outputs (DB0 DB7–DB8 DB12) causes current fluctuations in the ADC12451’s internal DVCC lines This generates digital noise which couples into the capacitive ladder that stores the analog input voltage Therefore the time interval between the rising edge of EOC and the second read is inappropriate for analog input voltage acquisition When WR is used to start a conversion with AZ low the Auto-Zero cycle is inserted before the acquisition window In Errors without any trims b 40 C to a 85 C 25 C g 0 075% g 0 2% Full Scale g 0 024% g 0 024% Zero g g Linearity LSB LSB FIGURE 4b Simple Reference Circuit this method the acquisition window is internally controlled by the ADC12451 and lasts for approximately 7 clock periods Since the acquisition window needs to be at least 3 5 ms at all times when using Auto-Zero the maximum clock frequency is limited to 2 MHz The zero error with the Auto-Zero cycle is production tested at a clock frequency of 1 75 MHz This accommodates easy switching between a conversion with the Auto-Zero cycle (fCLK e 1 75 MHz) and without (fCLK e 3 5 MHz) as shown in Figure 5 TL H 11025 – 22 FIGURE 5 Switching between a Conversion with and without Auto-Zero when Using WR Control 3 3 INPUT CURRENT Because the input network of the ADC12451 is made up of a switch and a network of capacitors a charging current will flow into or out of (depending on the input voltage polarity) of the analog input pin (VIN) on the start of the analog input sampling period The peak value of this current will depend on the actual input voltage applied and the source resistance 3 4 NOISE The leads to the analog input pin should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to this input can cause errors Input filtering can be used to reduce the effects of these noise sources 14 3 0 Analog Considerations (Continued) 3 5 INPUT BYPASS CAPACITORS An external capacitor can be used to filter out any noise due to inductive pickup by a long input lead and will not degrade the accuracy of the conversion result 3 6 INPUT SOURCE RESISTANCE The analog input can be modeled as shown in Figure 6 External RS will lengthen the time period necessary for the voltage on CREF to settle to within LSB of the analog input voltage With tA e 3 5 ms RS s 1 kX will allow a 5V analog input voltage to settle properly 3 7 POWER SUPPLIES b Noise spikes on the VCC and V supply lines can cause conversion errors as the comparator will respond to this noise The A D is especially sensitive during the Auto-Zero or -Cal procedures to any power supply spikes Low inductance tantalum capacitors of 10 mF or greater paralleled with 0 1 mF ceramic capacitors are recommended for supply bypassing Separate bypass capacitors should be placed b close to the DVCC AVCC and V pins If an unregulated voltage source is available in the system a separate LM340LAZ-5 0 voltage regulator for the A-to-D’s VCC (and other analog circuitry) will greatly reduce digital noise on the supply line 3 8 THE CALIBRATION CYCLE On power up the ADC12451 goes through an Auto-Cal cycle which cannot be interrupted Since the power supply reference and clock will not be stable at power up this first calibration cycle will not result in an accurate calibration of the A D A new calibration cycle needs to be started after the power supplies reference and clock have been given enough time to stabilize During the calibration cycle correction values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors These values are stored in internal RAM and used during an analog-to-digital conversion to bring the overall full-scale offset and linearity errors down to the specified limits Fullscale error typically changes g 0 2 LSB over temperature and linearity error changes even less therefore it should be necessary to go through the calibration cycle only once after power up if Auto-Zero is used to correct the zero error change Since Auto-Zero cannot be activated with S H conversion method it may be necessary to do a calibration cycle more than once 3 9 THE AUTO-ZERO CYCLE To correct for any change in the zero (offset) error of the A D the auto-zero cycle can be used It may be necessary to do an auto-zero cycle whenever the ambient temperature changes significantly (See the curve titled ‘‘Zero Error Change vs Ambient Temperature’’ in the Typical Performance Characteristics ) A change in the ambient temperature will cause the VOS of the sampled data comparator to change which may cause the zero error of the A D to be greater than g 1 LSB An auto-zero cycle will typically maintain the zero error to g 1 LSB or less 4 0 Dynamic Performance Many applications require the A D converter to digitize ac signals but the standard dc integral and differential nonlinearity specifications will not accurately predict the A D converter’s performance with ac input signals The important specifications for ac applications reflect the converter’s ability to digitize ac signals without significant spectral errors and without adding noise to the digitized signal Dynamic characteristics such as signal-to-noise (S N) signal-tonoise a distortion ratio (S (N a D)) effective bits full power bandwidth aperture time and aperture jitter are quantitative measures of the A D converter’s capability An A D converter’s ac performance can be measured using Fast Fourier Transform (FFT) methods A sinusoidal waveform is applied to the A D converter’s input and the transform is then performed on the digitized waveform S (N a D) and S N are calculated from the resulting FFT data and a spectral plot may also be obtained Typical values for S N are shown in the table of Electrical Characteristics and spectral plots of S (N a D) are included in the typical performance curves The A D converter’s noise and distortion levels will change with the frequency of the input signal with more distortion and noise occurring at higher signal frequencies This can be seen in the S (N a D) versus frequency curves These curves will also give an indication of the full power bandwidth (the frequency at which the S (N a D) or S N drops 3 dB) TL H 11025 – 23 FIGURE 6 Analog Input Equivalent Circuit 15 4 0 Dynamic Performance (Continued) Effective number of bits can also be useful in describing the A D’s noise performance An ideal A D converter will have some amount of quantization noise determined by its resolution which will yield an optimum S N ratio given by the following equation S N e (6 02 c n a 1 8) dB where n is the A D’s resolution in bits The effective bits of a real A D converter therefore can be found by S N(dB)b1 8 6 02 As an example an ADC12451 with a g 5V 10 kHz sine wave input signal will typically have a S N of 78 dB which is equivalent to 12 6 effective bits n(effective) e Two sample hold specifications aperture time and aperture jitter are included in the Dynamic Characteristics table since the ADC12451 has the ability to track and hold the analog input voltage Aperture time is the delay for the A D to respond to the hold command In the case of the ADC12451 the hold command is internally generated When the Auto-Zero function is not being used the hold command occurs at the end of the acquisition window or seven clock periods after the rising edge of the WR The delay between the internally generated hold command and the time that the ADC12451 actually holds the input signal is the aperture time For the ADC12451 this time is typically 100 ns Aperture jitter is the change in the aperture time from sample to sample Aperture jitter is useful in determining the maximum slew rate of the input signal for a given accuracy For example an ADC12451 with 100 ps of aperture jitter operating with a 5V reference can have an effective gain variation of about 1 LSB with an input signal whose slew rate is 12 V ms 5 0 Typical Applications Power Supply Bypassing TL H 11025 – 24 Protecting the Analog Inputs TL H 11025 – 25 Note External protection diodes should be able to withstand the op amp current limit 16 17 ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A D Converter with Sample-and-Hold Physical Dimensions inches (millimeters) Order Number ADC12451CMJ ADC12451CMJ 883 or ADC12451CIJ NS Package Number J24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and 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