LMH6580VS

LMH6580/LMH6581 8x4 500 MHz Analog Crosspoint Switch, Gain of 1, Gain of 2 September 2007 LMH6580/LMH6581 8x4 500 MHz Analog Crosspoint Switch, Gain of 1, Gain of 2 General Description The family of products is joined by the LMH6580 and the LMH6581, high speed, non-blocking, analog, crosspoint switches. The LMH6580/LMH6581 are designed for high speed, DC coupled, analog signals such as high resolution video (UXGA and higher). The LMH6580/LMH6581 each has eight inputs and four outputs. The non-blocking architecture allows any output to be connected to any input, including an input that is already selected. With fully buffered inputs the LMH6580/LMH6581 can be impedance matched to nearly any source impedance. The buffered outputs of the LMH6580/LMH6581 can drive up to two back terminated video loads (75Ω load). The outputs and inputs also feature high impedance inactive states allowing high performance input and output expansion for array sizes such as 8 x 8 or 16 x 4 by combining two devices. The LMH6580/LMH6581 are controlled with a 4 pin serial interface that can be configured as a 3 wire interface. Both serial mode and addressed modes are available. The LMH6580/LMH6581 come in 48-pin TQFP packages. They also have diagonally symmetrical pin assignments to facilitate double sided board layouts and easy pin connections for expansion. LMH® Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 8 inputs and 4 outputs 48-pin TQFP package −3 dB bandwidth (VOUT = 2 VPP, RL = 1 kΩ) 500 MHz −3 dB bandwidth (VOUT = 2 VPP, RL = 150Ω) 450 MHz Fast slew rate 2100 V/μs Channel to channel crosstalk (10/100 MHz) −70/ −52 dBc All hostile crosstalk (10/100 MHz) −55/−45 dBc Easy to use serial programming 4 wire bus Two programming modes Serial & addressed modes Symmetrical pinout facilitates expansion. Output current ±70 mA Two gain options AV = 1 or AV = 2 Applications ■ ■ ■ ■ ■ ■ ■ ■ Studio monitoring/production video systems Conference room multimedia video systems KVM (keyboard video mouse) systems Security/surveillance systems Multi-antenna diversity radio Video test equipment Medical imaging Wide-band routers & switches Connection Diagram Block Diagram 30007211 30007202 LMH® is a registered trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 300072 www.national.com LMH6580/LMH6581 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model VS IIN (Input Pins) IOUT Input Voltage Range Maximum Junction Temperature 2000V 200V ±6V ±20 mA (Note 3) V− to V+ +150°C (Note 5) Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) Wave Soldering (10 sec.) −65°C to +150°C 235°C 260°C Operating Ratings Temperature Range (Note 4) Supply Voltage Range Thermal Resistance 48-Pin TQFP (Note 1) −40°C to +85°C ±3V to ±5.5V θJA 44°C/W θJC 12°C/W ±3.3V Electrical Characteristics Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) 425 500 MHz 450 70 Max (Note 8) Units Frequency Domain Performance SSBW LSBW −3 dB Bandwidth VOUT = 0.5 VPP LMH6580 VOUT = 1 VPP, LMH6581 V OUT = 2 VPP, RL = 1 kΩ LMH6580 VOUT = 1 VPP, LMH6581 VOUT = 2 VPP, RL = 150Ω GF 0.1 dB Gain Flatness LMH6580 VOUT = 1 VPP, LMH6581 V OUT = 2 VPP, RL = 150Ω Time Domain Response tr tf OS SR Rise Time Fall Time Overshoot Slew Rate Slew Rate ts HD2 HD3 en in XTLK ISOL AV VOS TCVOS IB TCIB Settling Time 2nd Harmonic Distortion 3rd Harmonic Distortion Input Referred Voltage Noise Input Referred Noise Current Crosstalk Off Isolation Gain Input Offset Voltage Input Offset Voltage Average Drift (Note 10) Input Bias Current Input Bias Current Average Drift Non-Inverting (Note 9) Non-Inverting (Note 10) LMH6580 1V Step, LMH6581 2V Step, 10% to 90% LMH6580 1V Step, LMH6581 2V Step, 10% to 90% 2V Step LMH6580, 2 VPP, 40% to 60% (Note 6) LMH6581, 2 VPP, 40% to 60% (Note 6) 2V Step, VOUT within 0.5% 2 VPP, 10 MHz 2 VPP, 10 MHz >1 MHz >1 MHz All Hostile, f = 100 MHz f = 100 MHz LMH6581 LMH6580 1.986 0.994 3.1 1.4 2.0V Non-Inverting Non-Inverting Closed Loop, Enabled LMH6580 LMH6581 1100 Miscellaneous Performance RIN CIN RO RO CMVR IO VIH VIL VOH VOL TS TH Input Resistance Input Capacitance Output Resistance Enabled Output Resistance Disabled Input Common Mode Voltage Range Output Current Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Switching Time Setup Time Hold Time (Note 5) >2.0 1 MHz All Hostile, f = 100 MHz Channel to Channel, f = 100 MHz f = 100 MHz LMH6581 LMH6580 Min (Note 8) Typ (Note 7) 1200 2100 6 −80 −70 12 2 −45 −52 −65 Max (Note 8) Units V/µs V/µs ns dBc dBc nV/ pA/ dBc dBc dBc Settling Time 2nd Harmonic Distortion 3rd Harmonic Distortion Input Referred Voltage Noise Input Referred Noise Current Cross Talk Off Isolation Gain Input Offset Voltage Distortion And Noise Response Static, DC Performance 1.986 0.995 2.00 1.00 ±2 38 −5 −12 ±3.4 ±2.9 ±3.7 ±2.9 −42 −62 −60 ±3.6 ±3.0 ±3.9 ±3.0 −45 −90 −90 54 50 14 100 1 300 50 1100 1300 ±3.0 Sourcing, VO = 0 V ±60 2.0 0.8 >2.4 2.0V 2.014 1.005 ±17 mV µV/°C µA nA/°C Input Offset Voltage Average Drift (Note 10) Input Bias Current Input Bias Current Average Drift Output Voltage Range Digital Control www.national.com 4 LMH6580/LMH6581 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. Note 4: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 5: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested. Note 6: Slew Rate is the average of the rising and falling edges. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: Room Temperature limits are 100% production tested at 25°C. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 9: Negative input current implies current flowing out of the device. Note 10: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Note 11: This parameter is guaranteed by design and/or characterization and is not tested in production. Ordering Information Package 48-Pin QFP Part Number LMH6580VS LMH6581VS Package Marking LMH6580VS LMH6581VS Transport Media 250 Units/Tray 250 Units/Tray NSC Drawing VBC48A 5 www.national.com LMH6580/LMH6581 Typical Performance Characteristics LMH6580 1 VPP Frequency Response 1 VPP Frequency Response 30007253 30007254 1 VPP Frequency Response Broadcast 1 VPP Frequency Response Broadcast 30007255 30007256 Frequency Response 1 kΩ Load Frequency Response 1kΩ Load 30007252 30007274 www.national.com 6 LMH6580/LMH6581 Frequency Response with Input Expansion Frequency Response with Input Expansion 30007276 30007275 2 VPP Pulse Response 2 VPP Pulse Response 30007265 30007263 2 VPP Pulse Response, Broadcast Mode 2 VPP Pulse Response, Broadcast Mode 30007258 30007264 7 www.national.com LMH6580/LMH6581 1 VPP Pulse Response 1 VPP Pulse Response 30007261 30007259 Channel to Channel Crosstalk All Hostile Crosstalk 30007277 30007278 Second Order Distortion (HD2) vs. Frequency Third Order Distortion (HD3) vs. Frequency 30007272 30007270 www.national.com 8 LMH6580/LMH6581 Second Order Distortion (HD2) vs. Frequency Third Order Distortion (HD3) vs. Frequency 30007271 30007273 Positive Voltage Swing over Temperature Negative Voltage Swing over Temperature 30007266 30007267 Positive Voltage Swing over Temperature Negative Voltage Swing over Temperature 30007268 30007269 9 www.national.com LMH6580/LMH6581 Enabled Output Impedance Enabled Output Impedance 30007279 30007281 Disabled Output Impedance Disabled Output Impedance 30007282 30007280 Switching Time 30007257 www.national.com 10 LMH6580/LMH6581 Typical Performance Characteristics LMH6581 2 VPP Frequency Response 2 VPP Frequency Response 30007248 30007249 Large Signal Bandwidth Large Signal Bandwidth 30007222 30007223 Small Signal Bandwidth Small Signal Bandwidth 30007224 30007225 11 www.national.com LMH6580/LMH6581 Frequency Response 1 kΩ Load Group Delay 30007245 30007241 2 VPP Pulse Response 2 VPP Pulse Response 30007214 30007213 4 VPP Pulse Response 4 VPP Pulse Response Broadcast 30007216 30007217 www.national.com 12 LMH6580/LMH6581 4 VPP Pulse Response 6 VPP Pulse Response 30007215 30007218 Off Isolation All Hostile Crosstalk 30007219 30007221 Second Order Distortion (HD2) vs. Frequency Third Order Distortion (HD3) vs. Frequency 30007227 30007226 13 www.national.com LMH6580/LMH6581 Second Order Distortion vs. Frequency Third Order Distortion vs. Frequency 30007228 30007229 No Load Output Swing Positive Swing over Temperature 30007234 30007238 Negative Swing Over Temperature No Load Output Swing 30007239 30007231 www.national.com 14 LMH6580/LMH6581 Positive Swing over Temperature Negative Swing over Temperature 30007236 30007237 Enabled Output Impedance Disabled Output Impedance 30007250 30007251 Switching Time 30007257 15 www.national.com LMH6580/LMH6581 Application Information INTRODUCTION The LMH6580/LMH6581 are high speed, fully buffered, nonblocking, analog crosspoint switches. Having fully buffered inputs allows the LMH6580/LMH6581 to accept signals from low or high impedance sources without the worry of loading the signal source. The fully buffered outputs will drive 75Ω or 50Ω back terminated transmission lines with no external components other than the termination resistor. When disabled, the outputs are in a high impedance state. The LMH6580/ LMH6581 can have any input connected to any (or all) output (s). Conversely, a given output can have only one associated input. INPUT AND OUTPUT EXPANSION The LMH6580/LMH6581 have high impedance inactive states for both inputs and outputs allowing maximum flexibility for crosspoint expansion. In addition the LMH6580/LMH6581 employ diagonal symmetry in pin assignments. The diagonal symmetry makes it easy to use direct pin to pin vias when the parts are mounted on opposite sides of a board. As an example two LMH6580/LMH6581 chips can be combined on one board to form either an 8 x 8 crosspoint or a 16 x 4 crosspoint. To make an 8 x 8 crosspoint all 8 input pins would be tied together (Input 0 on side 1 to input 7 on side 2 and so on) while the 4 output pins on each chip would be left separate. To make the 16 x 4 crosspoint, the 4 outputs would be tied together while all 16 inputs would remain independent. In the 16 x 4 configuration it is important not to have 2 connected outputs active at the same time. With the 8 x 8 configuration, on the other hand, having two connected inputs active is a valid state. Crosspoint expansion as detailed above has the advantage that the signal will go through only one crosspoint. Expansion methods that have cascaded stages will suffer bandwidth loss far greater than the small loading effect of parallel expansion. Output expansion as shown in Figure 1 is very straight forward. Connecting the inputs of two crosspoint switches has a very minor impact on performance. Input expansion requires more planning. Input expansion, as show in Figure 2 and Figure 3 gives the option of two ways to connect the outputs of the crosspoint switches. In Figure 2 the crosspoint switch outputs are connected directly together and share one termination resistor. This is the easiest configurarion to implement and has only one drawback. Because the disabled output of the unused crosspoint (only one output can be active at a time) has a small amount of capacitance, the frequency response of the active crosspoint will show peaking. This is illustrated in Figure 4 and Figure 5. In most cases this small amount of peaking is not a problem. As illustrated in Figure 3 each crosspoint output can be given its own termination resistor. This results in a frequency response nearly identical to the non expansion case. There is one drawback for the gain of 2 crosspoint, and that is gain error. With a 75Ω termination resistor the 1250Ω resistance of the disabled crosspoint output will cause a gain error. In order to counter act this the termination resistors of both crosspoints should be adjusted to approximately 80Ω. This will provide very good matching, but the gain accuracy of the system will now be dependent on the process variations of the crosspoint resistors which have a variability of approximately ±20%. 30007242 FIGURE 1. Output Expansion 30007243 FIGURE 2. Input Expansion with Shared Termination Resistors www.national.com 16 LMH6580/LMH6581 30007247 FIGURE 5. Input Expansion Frequency Response DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Capacitive loads of 5 pF to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Since most capacitive loading is due to undesired parasitic capacitances the values of the capacitive loading will not usually be known exactly. It is best to start with a conservative value of ROUT and decrease the value until the bandwidth shows slight peaking. At this point the value of the isloation resistor will be determined by whether flat frequency response or maximum bandwidth is the desired goal. Smaller values of ROUT will produce some peaking, but maximum bandwidth. Larger resistor values will decrease bandwidth and suppress peaking. As starting values, a capacitive load of 5 pF should have around 75 Ω of isolation resistance. A value of 120 pF would require around 12Ω. When driving transmission lines, the output termination resistor is normally sufficient. 30007244 FIGURE 3. Input Expansion with Separate Termination Resistors 30007246 FIGURE 4. Input Expansion Frequency Response 17 www.national.com LMH6580/LMH6581 USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH AND INCREASE REBIABILITY The LMH6580/LMH6581 crosspoint switch can offer enhanced bandwidth and reliability with the use of external buffers on the outputs. The bandwidth is increased by unloading the outputs and driving the high impedance of an external buffer. See the Frequency Response 1 kΩ Load curve in the Typical Performance section for an example of bandwidth achieved with less loading on the outputs. For this technique to provide maximum benefit a very high speed amplifier such as the LMH6703 should be used. As shown in Figure 6 the resistor RL is placed between the crosspoint output and the buffer amplifier. This resistor will provide a load for the crosspoint output buffer and reduce peaking caused by the buffer input capacitance. A recommended value for RL is 500Ω to 1000Ω. Higher values of RL will give higher bandwidth, but also higher peaking. The optimum value of RL will depend greatly on board layout and the input capacitance of the buffer amplifier. Besides offering enhanced bandwidth performance using an external buffer provides greater system reliability. The first advantage is to reduce thermal loading on the crosspoint switch. This reduced die temperature will increase the life of the crosspoint. The second advantage is enhanced ESD reliability. It is very difficult to build high speed devices that can withstand all possible ESD events. With external buffers the crosspoint switch is isolated from ESD events on the external system connectors. DIGITAL CONTROL Block Diagram 30007211 FIGURE 7. Logic Pins Pin Name Level Sensitive CLK CS DATA IN DATA OUT CFG MODE RST BCST Yes Yes Yes Yes Yes Yes Yes Yes CLK rising edge CLK falling edge CLK rising edge Edge Triggered Triggered by 30007240 FIGURE 6. Buffered Output CROSSTALK When designing a large system such as a video router crosstalk can be a very serious problem. Extensive testing in our lab has shown that most crosstalk is related to board layout rather than occurring in the crosspoint switch. There are many ways to reduce board related crosstalk. Using controlled impedance lines is an important step. Using well decoupled power and ground planes will help as well. When crosstalk does occur within the crosspoint switch itself it is often due to signals coupling into the power supply pins. Using appropriate supply bypassing will help to reduce this mode of coupling. Another suggestion is to place as much grounded copper as possible between input and output signal traces. Care must be taken, though, not to influence the signal trace impedances by placing shielding copper too closely. One other caveat to consider is that as shielding materials come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low. Using thin signal traces will result in unacceptable losses due to trace resistance. This effect becomes even more pronounced at higher frequencies due to the skin effect. The skin effect reduces the effective thickness of the trace as frequency increases. Resistive losses make crosstalk worse because as the desired signal is attenuated with higher frequencies crosstalk increases at higher frequencies. www.national.com 18 There are two modes for programing the LMH6580/ LMH6581, Serial Mode and Addressed Mode. The LMH6580/ LMH6581 have internal control registers that store the programming states of the crosspoint switch. The logic is two staged to allow for maximum programming flexibility. The first stage of the control logic is tied directly to the crosspoint switching matrix. This logic consists of one register for each output that stores the on/off state and the address of which input to connect to. These registers are not directly accessible to the user. The second level of logic is another bank of registers identical to the first, but set up as shift registers. These registers are accessed by the user via the serial input bus. The LMH6580/LMH6581 is programmed via a serial input bus with the support of four other digital control pins. The Serial bus consists of a clock pin (CLK), a serial data in pin (DIN), and a serial data out pin (DOUT). The serial bus is gated by a chip select pin (CS). The chip select pin is active low. While the chip select pin is high all data on the serial input pin and clock pins is ignored. When the chip select pin is brought low the internal logic is set to begin receiving data by the first positive transition (0 to 1) of the clock signal. The chip select pin must be brought low at least 5 ns before the first rising edge of the clock signal. The first data bit is clocked in on the next negative transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the clock signal. Once the last valid data has been clocked in, either the LMH6580/LMH6581 chip select pin must go high or, the clock signal must stop. Otherwise invalid data will be clocked into the chip. The data clocked into the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of the state of the MODE pin. The CFG pin is not dependent on the state of the Chip select pin. If no new data is clocked into the chip subsequent pulses on the CFG pin will have no effect on device operation. The programming format of the incoming serial data is selected by the MODE pin. When the MODE pin is HIGH the crosspoint can be programmed one output at a time by entering a string of data that contains the address of the output that is going to be changed (Addressed Mode). When the mode pin is LOW the crosspoint is in Serial Mode. In this mode the crosspoint accepts a 16 bit array of data that programs all of the outputs. In both modes the data fed into the chip does not change the chip operation until the Configure pin is pulsed high. The configure and mode pins are independent of the chip select pin. THREE WIRE VS. FOUR WIRE CONTROL There are two ways to connect the serial data pins. The first way is to control all four pins separately, and the second option is to connect the CFG and the CS pins together for a 3 wire interface. The benefit of the 4-wire interface is that the chip can be configured independently using the CS pin. This would be an advantage in a system with multiple crosspoint chips where all of them could be programmed ahead of time and then configured simultaneously. The 4-wire solution is also helpful in a system that has a free running clock on the CLK pin. In this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being clocked into the chip. The 3-wire option provides the advantage of one less pin to control at the expense of having less flexibility with the con- figure pin. One way around this loss of flexibility would be if the clock signal is generated by an FPGA or microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip select function is provided by the presence or absence of the clock signal. SERIAL PROGRAMMING MODE Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 16-bits programs all four outputs of the crosspoint. The data is fed to the chip as shown in the Serial Mode Data Frame tables below (two tables are required to show the entire data frame). The table is arranged such that the first bit clocked into the crosspoint register is labeled bit number 0. The register labeled Load Register in the block diagram is a shift register. If the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then additional data will be shifted into the register, and the desired data will be shifted out. Also illustrated is the timing relationships for the digital pins in the Timing Diagram for Serial Mode shown below. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid data from being clocked into the chip. Another way to accomplish the same thing is to strobe the clock pin with only the desired number of pulses starting and ending with clock in the low condition. The configure (CFG) pin timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. 30007209 Timing Diagram for Serial Mode 19 www.national.com LMH6580/LMH6581 Serial Mode Data Frame (First Two Words) Output 0 Input Address LSB 0 1 MSB 2 On = 0 Off = 1 3 Output 1 Input Address LSB 4 LSB 5 6 On = 0 Off = 1 7 Off = TRI-STATE®, Bit 0 is first bit clocked into device. Serial Mode Data Frame (Continued) Output 2 Input Address LSB 8 9 MSB 10 On = 0 Off = 1 11 Output 3 Input Address LSB 12 13 MSB 14 On = 0 Off = 1 15 ADDRESSED PROGRAMMING MODE Addressed programming mode makes it possible to change only one output register at a time. To utilize this mode the mode pin must be High. All other pins function the same as in serial programming mode except that the word clocked in is 5 bits and is directed only at the output specified. In addressed mode the data format is shown below in the table titled Addressed Mode Word Format. Also illustrated is the timing relationships for the digital pins in the Timing Diagram for Addressed Mode shown below. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid data from being clocked into the chip. Also, in addressed mode is it necessary for the clock signal to make a low to high transition after the chip select pin has been brought high. If there is not a low to high transition of the clock after the chip select pin goes high subsequent data wil not be loaded into the chip properly. The configure (CFG) pin timing is not critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. 30007210 Timing Diagram for Addressed Mode www.national.com 20 LMH6580/LMH6581 Addressed Mode Word Format Output Address LSB 0 Bit 0 is first bit clocked into device. Input Address LSB 2 3 MSB 4 TRI-STATE 1 = TRI-STATE 0 = On 5 MSB 1 DAISY CHAIN OPTION IN SERIAL MODE The LMH6580/LMH6581 supports daisy chaining of the serial data stream between multiple chips. This feature is available only in the Serial Programming Mode. To use this feature serial data is clocked into the first chip DIN pin, and the next chip DIN pin is connected to the DOUT pin of the first chip. Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select pin goes low on both chips a double length word is clocked into the first chip. As the first word is clocking into the first chip the second chip is receiving the data that was originally in the shift register of the first chip (invalid data). When a full 16 bits have been clocked into the first chip the next clock cycle begins moving the first frame of the new configuration data into the second chip. With a full 32 clock cycles both chips have valid data and the chip select pin of both chips should be brought high to prevent the data from overshooting. A configure pulse will activate the new configuration on both chips simultaneously, or each chip can be configured separately. The mode, chip select, configure and clock pins of both chips can be tied together and driven from the same sources. SPECIAL CONTROL PINS The LMH6580/LMH6581 have two special control pins that function independent of the serial control bus. One of these pins is the reset (RST) pin. The RST pin is active high meaning that at logic 1 level the chip is configured with all outputs disabled and in a high impedance state. The RST pin programs all the registers with input address 0 and all the outputs are turned off. In this configuration the device draws only 11mA. The RST pin can be used as a shutdown function to reduce power consumption. The other special control pin is the broadcast (BCST) pin. The BCST pin is also active high and sets all the outputs to the on state connected to input 0. This is sometimes referred to as broadcast mode, where input 0 is broadcast to all eight outputs. THERMAL MANAGEMENT The LMH6580/LMH6581 are high performance devices that produce a significant amount of heat. With ±5V supplies, the LMH6580/LMH6581 will dissipate approximately 0.5 W of idling power with all outputs enabled. Idling power is calcu- lated based on the typical supply current of 50 mA and a 10V supply voltage. This power dissipation will vary within the range of 0.4 W to 0.6 W due to process variations. In addition, each equivalent video load (150Ω) connected to the outputs should be budgeted 30 mW of power. For a typical application with one video load for each output this would be a total power of 0.62 W. With a θJA of 44 °C/W this will result in the silicon being 27°C over the ambient temperature. A more aggressive application would be two video loads per output which would result in 0.74 W of power dissipation. This would result in a 33°C temperature rise. For heavier loading, the TQFP package thermal performance can be significantly enhanced with an external heat sink and by providing for moving air ventilation. Also, be sure to calculate the increase in ambient temperature from all devices operating in the system case. Because of the high power output of this device, thermal management should be considered very early in the design process. Generous passive venting and vertical board orientation may avoid the need for fan cooling or heat sinks. Also, the LMH6580/LMH6581 can be operated with a ±3.3V power supply. This will cut power dissipation substantially while only reducing bandwidth by about 10% (2 VPP output). The LMH6580/LMH6581 are fully characterized and factory tested at the ±3.3V power supply condition for applications where reduced power is desired. PRINTED CIRCUIT LAYOUT Generally, a good high frequency layout will keep power supply and ground traces away from the input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 for more information). If digital control lines must cross analog signal lines (particularly inputs) it is best if they cross perpendicularly. National Semiconductor suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Device LMH6580 Package 48–Pin Evaluation Board Part Number LMH730164EF 21 www.national.com LMH6580/LMH6581 Physical Dimensions inches (millimeters) unless otherwise noted 48-Pin QFP NS Package Number VBC48A www.national.com 22 LMH6580/LMH6581 Notes 23 www.national.com LMH6580/LMH6581 8x4 500 MHz Analog Crosspoint Switch, Gain of 1, Gain of 2 Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com