LMS75ALS176A

LMS75ALS176A Differential Bus Transceivers April 2003 LMS75ALS176A Differential Bus Transceivers General Description The LMS75ALS176A is a differential bus/line transceiver designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines. It meets ANSI Standards TIA/EIA RS422-B, TIA/ EIA RS485-A and ITU recommendation V.11 and X.27. The LMS75ALS176A combines a TRI-STATE™ differential line driver and differential input receiver, both of which operate from a single 5.0V power supply. The driver and receiver have an active high and active low enable, respectively, that can be externally connected to function as a direction control. The driver and receiver differential inputs are internally connected to form differential input/output (I/O) bus ports that are designed to offer minimum loading to bus whenever the driver is disabled or when VCC = 0V. These ports feature wide positive and negative common mode voltage ranges, making the device suitable for multipoint applications in noisy environments. The LMS75ALS176A is available in a 8-Pin SOIC package. It is a drop-in socket replacement to TI’s SN75ALS176A. Features n n n n n n n n n n n n n n n Bidirectional transceiver Meet ANSI standard RS-485-A and RS-422-B Low skew, 2ns Low supply current, 8mA (max.) Wide input and output voltage range High output drive capacity ± 60mA Thermal shutdown protection Open circuit fail-safe for receiver Receiver input sensitivity ± 200mV Receiver input hysteresis 10mV (min.) Single supply voltage operation, 5V Glitch free power-up and power-down operation Data rates up to 35 Mbaud Pin and functional compatible with TI’s SN75ALS176A 8-Pin SOIC Applications n n n n n Network hubs, bridges, and routers Point of sales equipment (ATM, barcode readers,…) Industrial programmable logic controllers High speed parallel and serial applications Multipoint applications with noisy environment Typical Application 20047801 A Typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable. Pull up and pull down resistors maybe required at the end of the bus to provide failsafe biasing. The biasing resistors provide a bias to the cable when all drivers are in TRI-STATE, See National Application Note, AN-847 for further information. © 2003 National Semiconductor Corporation DS200478 www.national.com LMS75ALS176A Connection Diagram 8-Pin SOIC 20047802 Top View Ordering Information Package 8-Pin SOIC Part Number LMS75ALS176AM LMS75ALS176AMX Package Marking LMS75LS176A Transport Media Rail 2.5k Units Tape and Reel NSC Drawing M08A Truth Table DRIVER SECTION RE X X X RECEIVER SECTION RE L L H L Note: * = Non Terminated, Open Input only X = Irrelevant Z = TRI-STATE H = High level L = Low level DE H H L DE L L X L DI H L X A-B ≥ +0.2V ≤ −0.2V X OPEN * A H L Z B L H Z RO H L Z H www.national.com 2 LMS75ALS176A Absolute Maximum Ratings (Note 1) Operating Ratings Min Nom Max Supply Voltage, VCC Voltage at any Bus Terminal (Separately or Common Mode) VIN or VIC High-Level Input Voltage, VIH (Note 5) Low-Level Input Voltage, VIL (Note 5) Differential Input Voltage, VID (Note 6) High-Level Output Driver, IOH −60 −400 60 8 mA µA mA mA Receiver, IOH Low-Level Output Driver, IOL Receiver, IOL 2 0.8 V V V 4.75 5.0 5.25 12 −7 V V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC (Note 2) Voltage Range at Any Bus Terminal Package Thermal Impedance, θJA Junction Temperature (Note 3) Operating Free-Air Temperature Range, TA Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) ESD Rating (Note 4) 235˚C 2KV 7V −7V to 12V 125C/W 150˚C 0˚C to 70˚C −65˚C to 150˚C Input Voltage, VIN (DI, DE, or RE) −0.3V to VCC + 0.3V ± 12 Electrical Characteristics VCC = 5V, TA = 0˚C to 70˚C Symbol Driver Section VCL VO | VOD1 | | VOD2 | VOD3 ∆VOD Input Clamp Voltage Output Voltage Differential Output Voltage Differential Output Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage (Note 7) Common-Mode Output Voltage Change in Magnitude of Differential Output Voltage (Note 7) Output Current High-Level Input Current Low-Level Input Current Short-Circuit Output Current II = −18mA IO = 0 IO = 0 RL = 100Ω, RL = 54Ω VTEST = −7V to 12 V RL = 54Ω or 100Ω 0 1.5 2 1.5 1.5 1.9 5 5 −1.5 6 6 V V V V V V Parameter Conditions Min Typ Max Units ± 0.2 VOC ∆VOC RL = 54Ω or 100Ω RL = 54Ω or 100Ω 3 −1 V V ± 0.2 IO IIH IIL IOSD Output Disabled (Note 8) VIN = 2.4V VIN = 0.4V VO = −7V VO = 0 VO = VCC VO = 8V VO = 12V VO = −7V 1 −0.8 20 −400 −250 −150 250 250 mA µA µA mA ICC Supply Current No Load Outputs Enabled or Disabled 3 4.8 8 mA Switching Characteristics td (OD) Differential Output Delay Time RL = 54Ω , CL = 50pF 7 14 ns 3 www.national.com LMS75ALS176A Electrical Characteristics VCC = 5V, TA = 0˚C to 70˚C Symbol tt (OD) tsk(p) tsk(lim) tPZH tPZL tPHZ tPLZ Parameter Differential Output Transition Time Pulse Skew Output Enable Time to High Level Output Enable Time to Low Level Output Disable Time from High Level Output Disable Time from Low Level Positive-Going Input Threshold Voltage Negative-Going Input Threshold Voltage Hysteresis Voltage (VTH+ - VTH−) Enable-Input Clamp Voltage High-Level Output Voltage Low-Level Output Voltage (Continued) Conditions Min Typ 8 0 4 18 18 9 10 50 35 35 17 3 Max Units ns ns ns ns ns ns ns RL = 54Ω, CL = 50pF Pulse Skew, (|td(ODH - td(ODL|) RL = 54Ω, CL = 50pF RL = 54Ω, CL = 50pF (Note 9) RL = 110Ω, CL = 50pF RL = 110Ω, CL = 50pF RL = 110Ω, CL = 50pF RL = 110Ω, CL = 50pF Receiver Section VTH+ VTH− ∆VTH VCL VOH VOL IOZ IIN IIH IIL RIN IOSR ICC VO = 2.7V, IO = −0.4mA VO = 0.5V, IO = 8mA −0.2 10 II = −18mA VID = 200mV, IOH = −400µA VID = −200mV, IOL = 8mA 2.7 0.45 1.5 0.2 V V mV V V V µA High-Impedance-State Output VO = 0.4V to 2.4V Current Line Input Current High-Level Enable-Input Current Low-Level Enable-Input Current Input Resistance Short-Circuit Output Current Supply Current VID = 200mV, VO = 0V No Load Outputs Enabled or Disabled Other Input = 0V, (Note 5) VIH = 2.7V VIL = 0.4V 12 −15 4.8 20 VIN = 12V VIN = −7V ± 20 1 −0.8 20 −100 mA µA µA kΩ −85 8 mA mA Switching Characteristics tPD tsk(p) tsk(lim) tPZH tPZL tPHZ tPLZ Propagation Delay Time Pulse Skew (|tPLH - tPHL|) Pulse Skew Output Enable Time to High Level Output Enable Time to Low Level Output Disable Time from High Level Output Disable Time from Low Level VID = −1.5V to 1.5V, CL = 15pF VID = −1.5V to 1.5V, CL = 15pF RL = 54Ω , CL = 50pF (Note 9) CL = 15pF CL = 15pF CL = 15pF CL = 15pF 8 18 2 7.5 5 5 20 10 35 35 35 17 30 ns ns ns ns ns ns ns www.national.com 4 LMS75ALS176A Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ. Note 5: Voltage limits apply to DI, DE, RE pins. Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B. Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels. Note 8: Applies to both power on and off (ANSI Standard RS-485 conditions). Does not apply to TIA/EIA-422-B for a combined driver and receiver combination. Note 9: Skew limit is the maximum difference in propagation delay between any two channels of any two devices. Typical Performance Characteristics Driver High-Level Output Voltage vs. High-Level Output Current Driver Low-Level Output Voltage vs. Low-Level Output Current 20047812 20047813 Driver Differential Output Voltage vs. Output Current Receiver High-Level Output Voltage vs. High-Level Output Current 20047814 20047815 5 www.national.com LMS75ALS176A Typical Performance Characteristics Receiver High-Level Output Voltage vs. Free-Air Temperature (Continued) Receiver Low-Level Output Voltage vs. Low-Level Output Current 20047816 20047817 Receiver Low-Level Output Voltage vs. Free-Air Temperature Receiver Output Voltage vs. Enable Voltage 20047818 20047819 Receiver Output Voltage vs. Enable Voltage 20047820 www.national.com 6 LMS75ALS176A Parameter Measuring Information 20047803 FIGURE 1. Test Circuit for VOD2 and VOC 20047804 FIGURE 2. Test Circuit for VOD3 20047805 FIGURE 3. Test Circuit for Driver Differential Output Delay and Transition Times 20047806 FIGURE 4. Test Circuit for Driver TPZH and TPHZ 7 www.national.com LMS75ALS176A Parameter Measuring Information (Continued) 20047807 FIGURE 5. Test Circuit for TPZL and TPLZ 20047808 FIGURE 6. Test Circuit for Receiver VOH and VOL 20047809 FIGURE 7. Test Circuit for TPLH and TPHL www.national.com 8 LMS75ALS176A Parameter Measuring Information (Continued) Test Circuit 20047810 Voltage Waveforms 20047811 FIGURE 8. Test Circuit for Receiver TPZH/ TPZL and TPHZ/TPLZ 9 www.national.com LMS75ALS176A Application Information POWER LINE NOISE FILTERING A factor to consider in designing power and ground is noise filtering. A noise filtering circuit is designed to prevent noise generated by the integrated circuit (IC) as well as noise entering the IC from other devices. A common filtering method is to place by-pass capacitors (Cbp) between the power and ground lines. Placing a by-pass capacitor (Cbp) with the correct value at the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon the desired noise filtering range. Since capacitors are not ideal, they may act more like inductors or resistors over a specific frequency range. Thus, many times two by-pass capacitors may be used to filter a wider bandwidth of noise. It is highly recommended to place a larger capacitor, such as 10µF, between the power supply pin and ground to filter out low frequencies and a 0.1µF to filter out high frequencies. By pass-capacitors must be mounted as close as possible to the IC to be effective. Long leads produce higher impedance at higher frequencies due to stray inductance. Thus, this will reduce the by-pass capacitor’s effectiveness. Surface mounted chip capacitors are the best solution because they have lower inductance. 20047821 FIGURE 9. Placement of by-pass Capacitors, Cbp www.national.com 10 LMS75ALS176A Differential Bus Transceivers Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.