74ALVCH162827DGG:1

74ALVCH162827 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state Rev. 2 — 19 January 2018 1 Product data sheet General description The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND output enables (nOE1 and nOE2) for maximum control flexibility. The 74ALVCH162827 is designed with 30 Ω series resisters in both the pull-up and pulldown output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters. To ensure the high impedance state during power up or power down, nOEn should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The 74ALVCH162827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits • • • • • • • • CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Direct interface with TTL levels (2.7 V to 3.6 V) Bus hold on data inputs Current drive ± 12 mA at 3.0 V Integrated 30 Ω termination resistors Complies with JEDEC standards: – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V) • ESD protection: – HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V – CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1. Ordering information Type number 74ALVCH162827DGG Package Temperature range Name Description Version −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 4 Functional diagram 1 1OE1 56 1OE2 28 2OE1 29 2OE2 55 54 52 51 49 48 47 45 44 43 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 2 3 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 31 30 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 15 16 17 19 20 21 23 24 26 27 1 1OE1 56 1OE2 28 2OE1 29 2OE2 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 & EN1 & 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 EN2 1 1 1 2 aaa-028075 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 aaa-028076 Figure 1. Logic symbol Figure 2. IEC logic symbol nA0 nA1 nA2 nA3 nA4 nA5 nA6 nA7 nA8 nY0 nY1 nY2 nY3 nY4 nY5 nY6 nY7 nY8 nA9 nOE1 nOE2 nY9 aaa-028077 Figure 3. Logic diagram VCC data input to internal circuit mna705 Figure 4. Bus hold circuit 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 5 Pinning information 5.1 Pinning 74ALVCH162827 1OE1 1 56 1OE2 1Y0 2 55 1A0 1Y1 3 54 1A1 GND 4 53 GND 1Y2 5 52 1A2 1Y3 6 51 1A3 VCC 7 1Y4 8 50 VCC 49 1A4 1Y5 9 48 1A5 1Y6 10 47 1A6 GND 11 46 GND 1Y7 12 45 1A7 1Y8 13 44 1A8 1Y9 14 43 1A9 2Y0 15 42 2A0 2Y1 16 41 2A1 2Y2 17 40 2A2 GND 18 39 GND 2Y3 19 38 2A3 2Y4 20 37 2A4 2Y5 21 36 2A5 VCC 22 2Y6 23 35 VCC 34 2A6 2Y7 24 33 2A7 GND 25 32 GND 2Y8 26 31 2A8 2Y9 27 30 2A9 2OE1 28 29 2OE2 aaa-028078 Figure 5. Pin configuration SOT364-1 (TSSOP56) 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7, 1A8, 1A9 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7, 2A8, 2A9 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input 1Y0, 1Y1, 1Y2, 1Y3, 1Y4, 1Y5, 1Y6, 1Y7, 1Y8, 1Y9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 data output 2Y0, 2Y1, 2Y2, 2Y3, 2Y4, 2Y5, 2Y6, 2Y7, 2Y8, 2Y9 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output 1OE1, 1OE2, 2OE1, 2OE2 1, 56, 28, 29 output enable input (active-LOW) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 positive voltage supply 6 Functional description Table 3. Function table X = don’t care; Z = High-impedance OFF-state; H = HIGH voltage level; L = LOW voltage level. Operating mode Input Output nOEn nAn nYn transparent L L L transparent L H H High-impedance H X Z 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 4 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +4.6 V input voltage [1] −0.5 +4.6 V VO output voltage [1] −0.5 IIK input clamping current VI < 0 V IOK output clamping current IO output current ICC VI VCC + 0.5 V −50 - mA VO > VCC or VO < 0 V - ±50 mA VO = 0 V to VCC - ±50 mA supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 600 mW Ptot total power dissipation Tamb = −40 °C to +85 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage For maximum speed performance at CL = 30 pF 2.3 2.7 V For maximum speed performance at CL = 50 pF 3.0 3.6 V VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature in free air −40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 20 ns/V VCC = 3.0 V to 3.6 V 0 10 ns/V 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 5 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 9 Static characteristics Table 6. Static characteristics At recommended operating conditions. Tamb = −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter Conditions Min Typ VIH HIGH-level input voltage VCC = 2.3 to 2.7 V 1.7 1.2 - V VCC = 2.7 to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 to 2.7 V - 1.2 0.7 V VCC = 2.7 to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -4 mA; VCC = 2.3 V VCC - 0.4 VCC - 0.11 - V IO = -6 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.17 - V IO = -4 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.09 - V IO = -8 mA; VCC = 2.7 V VCC - 0.7 VCC - 0.19 - V IO = -6 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.13 - V IO = -12 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.27 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 4 mA; VCC = 2.3 V - 0.07 0.40 V IO = 6 mA; VCC = 2.3 V - 0.11 0.55 V IO = 4 mA; VCC = 2.7 V - 0.06 0.40 V IO = 8 mA; VCC = 2.7 V - 0.13 0.60 V IO = 6 mA; VCC = 3.0 V - 0.09 0.55 V IO = 12 mA; VCC = 3.0 V - 0.19 0.80 V - 0.1 5 μA VIL VOH VOL LOW-level output voltage Max Unit VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V 45 - - μA IBHH bus hold HIGH current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V -500 - - μA IOZ OFF-state output current VCC = 2.3 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA CI input capacitance - 5.0 - pF [1] All typical values are measured at Tamb = 25 °C. 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 6 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 10 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C. For test circuit, see Figure 8. Symbol tpd Parameter propagation delay Conditions Min nAn to nYn; see Figure 6 4.6 ns - 3.1 4.7 ns 1.5 2.9 4.2 ns 1.4 3.9 6.4 ns - 4.4 6.5 ns 1.6 3.7 5.4 ns 1.7 2.2 5.9 ns - 3.2 5.2 ns 1.8 3.0 4.7 ns output enabled - 14 - pF output disabled - 3 - pF nOEn to nYn; see Figure 7 [2] VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V disable time nOEn to nYn; see Figure 7 [2] VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V CPD power dissipation capacitance Unit 2.9 VCC = 3.0 V to 3.6 V tdis Max 1.0 VCC = 2.7 V enable time [1] [2] VCC = 2.3 V to 2.7 V ten Typ per latch; VI = GND to VCC [3] [1] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V [2] tpd is the same as tPHL and tPLH; ten is the same as tPZH and tPZL; tdis is the same as tPHZ and tPLZ. [3] CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 7 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 10.1 Waveforms and test circuit VI nAn input VM VM GND tPLH tPHL VOH VM nYn output VM VOL mna171 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 6. Input (nAn) to output (nYn) propagation delays VI nOEn input VM GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPZL VM VX tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND tPZH VY VM outputs enabled outputs enabled outputs disabled col015 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 7. The 3-state output enable and disable times Table 8. Measurement points Supply voltage Input VCC VI VM VM VX VY 2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVCH162827 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 8 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Figure 8. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH162827 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 9 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 11 Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 9. Package outline SOT364-1 (TSSOP56) 74ALVCH162827 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 10 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 12 Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date 74ALVCH162827 v.2 20180119 Modifications: Product data sheet Change notice Supersedes Product data sheet - 74ALVCH162827 v.1 • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74ALVCH162827 v.1 19980929 74ALVCH162827 Data sheet status Product specification - All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 - © Nexperia B.V. 2018. All rights reserved. 11 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74ALVCH162827 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 12 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74ALVCH162827 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 January 2018 © Nexperia B.V. 2018. All rights reserved. 13 / 14 74ALVCH162827 Nexperia 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 5 Recommended operating conditions ................ 5 Static characteristics .......................................... 6 Dynamic characteristics .....................................7 Waveforms and test circuit ................................ 8 Package outline .................................................10 Abbreviations .................................................... 11 Revision history ................................................ 11 Legal information .............................................. 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 19 January 2018 Document identifier: 74ALVCH162827