74ALVCH16501DL

74ALVCH16501 18-bit universal bus transceiver; 3-state Rev. 03 — 2 April 2010 Product data sheet 1. General description The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW. To ensure the high-impedance state during power-up or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard JESD8-B CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at VCC = 3.0 V Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode All inputs have bus hold circuitry Output drive capability 50 Ω transmission lines at 85 °C 3-state non-inverting outputs for bus-oriented applications NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74ALVCH16501DGG 74ALVCH16501DL −40 °C to +85 °C −40 °C to +85 °C Name TSSOP56 SSOP56 Description plastic thin shrink small outline package; 56 leads; body width 6.1 mm plastic shrink small outline package; 56 leads; body width 7.5 mm Version SOT364-1 SOT371-1 Type number 4. Functional diagram 1 55 2 OEAB CPAB LEAB EN1 2C3 C3 G2 OEBA 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 CPBA 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 1 2 55 OEAB LEAB CPAB OEBA LEBA CPBA 27 28 30 A15 A16 A17 A0 LEBA 27 30 28 EN4 5C6 C6 G5 3 3D 4 1 1 1 6D 54 B0 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 001aal718 001aal717 Fig 1. Logic symbol Fig 2. IEC logic symbol 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 2 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state VCC data input to internal circuit 001aal733 Fig 3. Bus hold circuit OEAB CPBA LEBA CPAB LEAB OEBA C1 A1 1D C1 B1 1D C1 1D C1 1D 18 IDENTICAL CHANNELS 001aal719 Fig 4. Logic diagram 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 3 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 74ALVCH16501 OEAB LEAB A0 GND A1 A2 VCC A3 A4 1 2 3 4 5 6 7 8 9 56 GND 55 CPAB 54 B0 53 GND 52 B1 51 B2 50 VCC 49 B3 48 B4 47 B5 46 GND 45 B6 44 B7 43 B8 42 B9 41 B10 40 B11 39 GND 38 B12 37 B13 36 B14 35 VCC 34 B15 33 B16 32 GND 31 B17 30 CPBA 29 GND 001aal716 A5 10 GND 11 A6 12 A7 13 A8 14 A9 15 A10 16 A11 17 GND 18 A12 19 A13 20 A14 21 VCC 22 A15 23 A16 24 GND 25 A17 26 OEBA 27 LEBA 28 Fig 5. Pin configuration 5.2 Pin description Table 2. Symbol OEAB LEAB A0 to A17 GND VCC OEBA LEBA 74ALVCH16501_3 Pin description Pin 1 2 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 4, 11, 18, 25, 29, 32, 39, 46, 53, 56 7, 22, 35, 50 27 28 All information provided in this document is subject to legal disclaimers. Description output enable A-to-B input latch enable A-to-B input data inputs or outputs ground (0 V) positive supply voltage output enable B-to-A latch enable B-to-A © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 4 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state Table 2. Symbol CPBA B0 to B17 CPAB Pin description …continued Pin 30 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 55 Description clock input B-to-A data inputs or outputs clock input A-to-B 6. Functional description 6.1 Function table Table 3. Inputs OEAB L H H H H H H H H [1] Function table[1] Output LEAB X H H CPAB X X X X X ↑ ↑ H or L H or L An X H L h l h l X X Bn Z H L H L H L H L hold data and display clock data and display latch data and display disabled transparent Operating mode ↓ ↓ L L L L A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the enable or clock transition; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW clock transition; ↑ = LOW-to-HIGH clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC 74ALVCH16501_3 Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current Conditions VI < 0 V control inputs data inputs VO > VCC or VO < 0 V [1] [1] [1] Min −0.5 −50 −0.5 −0.5 −0.5 - Max +4.6 +4.6 VCC + 0.5 ±50 VCC + 0.5 ±50 100 Unit V mA V V mA V mA mA VO = 0 V to VCC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 5 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol IGND Tstg Ptot Parameter ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C SSOP package TSSOP package [1] [2] [3] [2] [3] Conditions Min −100 −65 - Max +150 850 600 Unit mA °C mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Above 55 °C the value of Ptot derates linearly with 11.3 mW/K. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions maximum speed performance CL = 30 pF CL = 50 pF low-voltage applications VI VO Tamb Δt/ΔV input voltage output voltage ambient temperature input transition rise and fall rate in free air VCC = 2.3 V to 3.0 V VCC = 3.0 V to 3.6 V 2.3 3.0 1.2 0 0 −40 0 0 2.7 3.6 3.6 VCC VCC +85 20 10 V V V V V °C ns/V ns/V Min Typ Max Unit 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 6 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI = VIH or VIL IO = −100 μA; VCC = 2.3 V to 3.6 V IO = −6 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −12 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 μA; VCC = 2.3 V to 3.6 V IO = 6 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 2.3 V to 3.6 V VI = VIH or VIL; VO = VCC or GND; VCC = 2.7 V to 3.6 V VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A per data I/O pin; VCC = 2.3 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A VCC = 2.3 V; VI = 0.7 V VCC = 3.0 V; VI = 0.8 V IBHH IBHLO IBHHO CI CI/O [1] [2] [2] [2] [2] [2] [2] [2] Min 1.7 2.0 VCC − 0.2 VCC − 0.3 VCC − 0.6 VCC − 0.5 VCC − 0.6 VCC − 1.0 - Typ[1] 1.2 1.5 1.2 1.5 VCC VCC − 0.08 VCC − 0.26 VCC − 0.14 VCC − 0.09 VCC − 0.28 GND 0.07 0.15 0.14 0.27 0.1 0.1 Max 0.7 0.8 0.20 0.40 0.70 0.40 0.55 5 10 Unit V V V V V V V V V V V V V V V μA μA Tamb = −40 °C to +85 °C ICC ΔICC supply current additional supply current - 0.2 150 40 750 μA μA IBHL bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current input capacitance input/output capacitance All typical values are measured at Tamb = 25 °C. Valid for data inputs of bus hold parts only. 45 75 −45 −75 500 −500 - 150 −175 4.0 8.0 - μA μA μA μA μA μA pF pF VCC = 2.3 V; VI = 1.7 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V VCC = 3.6 V 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 7 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10. Symbol fmax Parameter maximum frequency Conditions see Figure 8 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V tpd propagation delay An to Bn; Bn to An; see Figure 6 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V LEAB, LEBA to Bn, An; see Figure 8 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V CPAB, CPBA to Bn, An; see Figure 8 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V ten enable time OEBA to An; see Figure 7 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V OEAB to Bn; see Figure 7 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V tdis disable time OEBA to An; see Figure 7 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V OEAB to Bn; see Figure 7 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V [2] [3] [4] [2] [3] [2] [3] [4] [2] [3] [2] [3] [2] [3] [4] [2] [3] [2] [3] Min Typ[1] Max Unit Tamb = −40 °C to +85 °C 150 150 150 1.0 1.0 1.1 1.3 1.0 1.4 1.3 1.1 1.0 1.0 1.3 1.3 1.5 1.4 333 340 333 2.8 3.0 3.0 3.5 3.4 3.6 3.3 3.3 3.4 2.8 2.5 3.3 2.5 2.4 2.7 2.5 3.1 3.3 2.5 2.9 3.6 5.1 4.2 4.6 6.1 4.8 5.3 6.1 4.9 5.6 6.3 5.0 6.0 5.8 4.6 5.3 5.3 4.2 4.6 6.2 5.0 5.7 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 8 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state Table 7. Dynamic characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10. Symbol tW Parameter pulse width Conditions LEAB, LEBA HIGH; see Figure 8 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V CPAB, CPBA HIGH or LOW; see Figure 8 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V tsu set-up time An, Bn to CPAB, CPBA; see Figure 9 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V An, Bn to LEAB, LEBA; see Figure 9 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V th hold time An, Bn to CPAB, CPBA; see Figure 9 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V An, Bn to LEAB, LEBA; see Figure 9 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V CPD power dissipation capacitance per buffer; VI = GND to VCC outputs enabled outputs disabled [1] [2] [3] [4] All typical values are measured at Tamb = 25 °C. Typical values are measured at VCC = 2.5 V. Typical values are measured at VCC = 3.3 V. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. [5] [2] [3] [2] [3] [2] [3] [2] [3] [2] [3] [2] [3] Min 3.3 3.3 3.3 3.3 3.3 3.3 1.7 1.3 1.4 1.1 1.0 1.0 1.7 1.3 1.6 1.6 1.2 1.5 - Typ[1] 0.8 0.9 0.7 2.0 1.1 1.4 0.1 −0.3 −0.1 0.1 0.3 −0.2 0.3 0.4 0.3 0.3 0.1 0.1 21 3 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 9 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 11. Waveforms VI An, Bn input GND tPHL VOH Bn, An output VOL VM VM 001aal734 VM VM tPLH Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 6. Propagation delay, data input (An, Bn) to data output (Bn, An) VI OEAB, OEBA input GND VM VM tPLZ VCC tPZL An, Bn output LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ VOH tPZH VY VM An, Bn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aal721 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 7. 3-state output enable and disable times 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 10 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 1 / fmax VI LExx input CPxx input GND VM tW tPHL VM VM tPLH VOH An, Bn output VOL VM VM 001aal720 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output, and pulse width VI An, Bn input VM GND VI tsu th VM VM tsu th VM CPxx, LExx input VM GND VM 001aal722 Measurement points are given in Table 8. Fig 9. Table 8. VCC Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs) Measurement points Input VI VCC 2.7 V 2.7 V VM 0.5 2.7 V 2.7 V Output VM 0.5 1.5 V 1.5 V VX VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.15 V VOH − 0.3 V VOH − 0.3 V Supply voltage 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 11 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 12. Test information VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to Zo of pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuit for measuring switching times Table 9. VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V Test data Input VI VCC 2.7 V 2.7 V tr, tf ≤ 2.0 ns 2.5 ns 2.5 ns Load CL 30 pF 50 pF 50 pF RL 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND Supply voltage 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 12 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 13. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y HE vMA Z 56 29 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp wM 28 detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT364-1 (TSSOP56) 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 13 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE vM A Z 56 29 Q A2 A1 (A 3) θ Lp 1 28 A pin 1 index L wM detail X e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC MO-118 A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 18.55 18.30 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 12. Package outline SOT371-1 (SSOP56) 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 14 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 14. Abbreviations Table 10. Acronym CMOS DUT TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date Data sheet status 20100402 Product data sheet Change notice Order number Supersedes 74ALVCH16501_2 Document ID 74ALVCH16501_3 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3 “Ordering information”: Added type 74ALVCH16501DL. Quick reference section removed. Product specification Product specification 74ALVCH16501_1 - 74ALVCH16501_2 74ALVCH16501_1 19980929 19980929 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 15 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ALVCH16501_3 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 16 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 17 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 April 2010 Document identifier: 74ALVCH16501_3